3 * Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
23 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * RC32434 Ethernet interface driver
36 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/systm.h>
39 #include <sys/sockio.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/taskqueue.h>
48 #include <net/if_arp.h>
49 #include <net/ethernet.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
52 #include <net/if_types.h>
56 #include <machine/bus.h>
57 #include <machine/resource.h>
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 MODULE_DEPEND(kr, ether, 1, 1, 1);
68 MODULE_DEPEND(kr, miibus, 1, 1, 1);
70 #include "miibus_if.h"
72 #include <mips/idt/if_krreg.h>
76 static int kr_attach(device_t);
77 static int kr_detach(device_t);
78 static int kr_ifmedia_upd(struct ifnet *);
79 static void kr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
80 static int kr_ioctl(struct ifnet *, u_long, caddr_t);
81 static void kr_init(void *);
82 static void kr_init_locked(struct kr_softc *);
83 static void kr_link_task(void *, int);
84 static int kr_miibus_readreg(device_t, int, int);
85 static void kr_miibus_statchg(device_t);
86 static int kr_miibus_writereg(device_t, int, int, int);
87 static int kr_probe(device_t);
88 static void kr_reset(struct kr_softc *);
89 static int kr_resume(device_t);
90 static int kr_rx_ring_init(struct kr_softc *);
91 static int kr_tx_ring_init(struct kr_softc *);
92 static int kr_shutdown(device_t);
93 static void kr_start(struct ifnet *);
94 static void kr_start_locked(struct ifnet *);
95 static void kr_stop(struct kr_softc *);
96 static int kr_suspend(device_t);
98 static void kr_rx(struct kr_softc *);
99 static void kr_tx(struct kr_softc *);
100 static void kr_rx_intr(void *);
101 static void kr_tx_intr(void *);
102 static void kr_rx_und_intr(void *);
103 static void kr_tx_ovr_intr(void *);
104 static void kr_tick(void *);
106 static void kr_dmamap_cb(void *, bus_dma_segment_t *, int, int);
107 static int kr_dma_alloc(struct kr_softc *);
108 static void kr_dma_free(struct kr_softc *);
109 static int kr_newbuf(struct kr_softc *, int);
110 static __inline void kr_fixup_rx(struct mbuf *);
112 static device_method_t kr_methods[] = {
113 /* Device interface */
114 DEVMETHOD(device_probe, kr_probe),
115 DEVMETHOD(device_attach, kr_attach),
116 DEVMETHOD(device_detach, kr_detach),
117 DEVMETHOD(device_suspend, kr_suspend),
118 DEVMETHOD(device_resume, kr_resume),
119 DEVMETHOD(device_shutdown, kr_shutdown),
122 DEVMETHOD(miibus_readreg, kr_miibus_readreg),
123 DEVMETHOD(miibus_writereg, kr_miibus_writereg),
124 DEVMETHOD(miibus_statchg, kr_miibus_statchg),
129 static driver_t kr_driver = {
132 sizeof(struct kr_softc)
135 static devclass_t kr_devclass;
137 DRIVER_MODULE(kr, obio, kr_driver, kr_devclass, 0, 0);
138 DRIVER_MODULE(miibus, kr, miibus_driver, miibus_devclass, 0, 0);
141 kr_probe(device_t dev)
144 device_set_desc(dev, "RC32434 Ethernet interface");
149 kr_attach(device_t dev)
151 uint8_t eaddr[ETHER_ADDR_LEN];
157 sc = device_get_softc(dev);
158 unit = device_get_unit(dev);
161 mtx_init(&sc->kr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
163 callout_init_mtx(&sc->kr_stat_callout, &sc->kr_mtx, 0);
164 TASK_INIT(&sc->kr_link_task, 0, kr_link_task, sc);
165 pci_enable_busmaster(dev);
167 /* Map control/status registers. */
169 sc->kr_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->kr_rid,
172 if (sc->kr_res == NULL) {
173 device_printf(dev, "couldn't map memory\n");
178 sc->kr_btag = rman_get_bustag(sc->kr_res);
179 sc->kr_bhandle = rman_get_bushandle(sc->kr_res);
181 /* Allocate interrupts */
183 sc->kr_rx_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, KR_RX_IRQ,
184 KR_RX_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
186 if (sc->kr_rx_irq == NULL) {
187 device_printf(dev, "couldn't map rx interrupt\n");
193 sc->kr_tx_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, KR_TX_IRQ,
194 KR_TX_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
196 if (sc->kr_tx_irq == NULL) {
197 device_printf(dev, "couldn't map tx interrupt\n");
203 sc->kr_rx_und_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
204 KR_RX_UND_IRQ, KR_RX_UND_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
206 if (sc->kr_rx_und_irq == NULL) {
207 device_printf(dev, "couldn't map rx underrun interrupt\n");
213 sc->kr_tx_ovr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
214 KR_TX_OVR_IRQ, KR_TX_OVR_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
216 if (sc->kr_tx_ovr_irq == NULL) {
217 device_printf(dev, "couldn't map tx overrun interrupt\n");
222 /* Allocate ifnet structure. */
223 ifp = sc->kr_ifp = if_alloc(IFT_ETHER);
226 device_printf(dev, "couldn't allocate ifnet structure\n");
231 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
232 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
233 ifp->if_ioctl = kr_ioctl;
234 ifp->if_start = kr_start;
235 ifp->if_init = kr_init;
237 /* XXX: add real size */
238 IFQ_SET_MAXLEN(&ifp->if_snd, 9);
239 ifp->if_snd.ifq_maxlen = 9;
240 IFQ_SET_READY(&ifp->if_snd);
242 ifp->if_capenable = ifp->if_capabilities;
251 if (kr_dma_alloc(sc) != 0) {
256 /* TODO: calculate prescale */
257 CSR_WRITE_4(sc, KR_ETHMCP, (165000000 / (1250000 + 1)) & ~1);
259 CSR_WRITE_4(sc, KR_MIIMCFG, KR_MIIMCFG_R);
261 CSR_WRITE_4(sc, KR_MIIMCFG, 0);
264 error = mii_attach(dev, &sc->kr_miibus, ifp, kr_ifmedia_upd,
265 kr_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
267 device_printf(dev, "attaching PHYs failed\n");
271 /* Call MI attach routine. */
272 ether_ifattach(ifp, eaddr);
274 /* Hook interrupt last to avoid having to lock softc */
275 error = bus_setup_intr(dev, sc->kr_rx_irq, INTR_TYPE_NET | INTR_MPSAFE,
276 NULL, kr_rx_intr, sc, &sc->kr_rx_intrhand);
279 device_printf(dev, "couldn't set up rx irq\n");
284 error = bus_setup_intr(dev, sc->kr_tx_irq, INTR_TYPE_NET | INTR_MPSAFE,
285 NULL, kr_tx_intr, sc, &sc->kr_tx_intrhand);
288 device_printf(dev, "couldn't set up tx irq\n");
293 error = bus_setup_intr(dev, sc->kr_rx_und_irq,
294 INTR_TYPE_NET | INTR_MPSAFE, NULL, kr_rx_und_intr, sc,
295 &sc->kr_rx_und_intrhand);
298 device_printf(dev, "couldn't set up rx underrun irq\n");
303 error = bus_setup_intr(dev, sc->kr_tx_ovr_irq,
304 INTR_TYPE_NET | INTR_MPSAFE, NULL, kr_tx_ovr_intr, sc,
305 &sc->kr_tx_ovr_intrhand);
308 device_printf(dev, "couldn't set up tx overrun irq\n");
321 kr_detach(device_t dev)
323 struct kr_softc *sc = device_get_softc(dev);
324 struct ifnet *ifp = sc->kr_ifp;
326 KASSERT(mtx_initialized(&sc->kr_mtx), ("vr mutex not initialized"));
328 /* These should only be active if attach succeeded */
329 if (device_is_attached(dev)) {
334 taskqueue_drain(taskqueue_swi, &sc->kr_link_task);
338 device_delete_child(dev, sc->kr_miibus);
339 bus_generic_detach(dev);
341 if (sc->kr_rx_intrhand)
342 bus_teardown_intr(dev, sc->kr_rx_irq, sc->kr_rx_intrhand);
344 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_rx_irq);
345 if (sc->kr_tx_intrhand)
346 bus_teardown_intr(dev, sc->kr_tx_irq, sc->kr_tx_intrhand);
348 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_tx_irq);
349 if (sc->kr_rx_und_intrhand)
350 bus_teardown_intr(dev, sc->kr_rx_und_irq,
351 sc->kr_rx_und_intrhand);
352 if (sc->kr_rx_und_irq)
353 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_rx_und_irq);
354 if (sc->kr_tx_ovr_intrhand)
355 bus_teardown_intr(dev, sc->kr_tx_ovr_irq,
356 sc->kr_tx_ovr_intrhand);
357 if (sc->kr_tx_ovr_irq)
358 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->kr_tx_ovr_irq);
361 bus_release_resource(dev, SYS_RES_MEMORY, sc->kr_rid,
369 mtx_destroy(&sc->kr_mtx);
376 kr_suspend(device_t dev)
379 panic("%s", __func__);
384 kr_resume(device_t dev)
387 panic("%s", __func__);
392 kr_shutdown(device_t dev)
396 sc = device_get_softc(dev);
406 kr_miibus_readreg(device_t dev, int phy, int reg)
408 struct kr_softc * sc = device_get_softc(dev);
412 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
416 device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
418 CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);
421 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
425 device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
427 CSR_WRITE_4(sc, KR_MIIMCMD, KR_MIIMCMD_RD);
430 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
434 device_printf(dev, "phy mii read is timed out %d:%d\n", phy,
437 if (CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_NV)
438 printf("phy mii readreg failed %d:%d: data not valid\n",
441 result = CSR_READ_4(sc , KR_MIIMRDD);
442 CSR_WRITE_4(sc, KR_MIIMCMD, 0);
448 kr_miibus_writereg(device_t dev, int phy, int reg, int data)
450 struct kr_softc * sc = device_get_softc(dev);
454 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
458 device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
460 CSR_WRITE_4(sc, KR_MIIMADDR, (phy << 8) | reg);
463 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
467 device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
469 CSR_WRITE_4(sc, KR_MIIMWTD, data);
472 while ((CSR_READ_4(sc, KR_MIIMIND) & KR_MIIMIND_BSY) && i)
476 device_printf(dev, "phy mii is busy %d:%d\n", phy, reg);
482 kr_miibus_statchg(device_t dev)
486 sc = device_get_softc(dev);
487 taskqueue_enqueue(taskqueue_swi, &sc->kr_link_task);
491 kr_link_task(void *arg, int pending)
494 struct mii_data *mii;
496 /* int lfdx, mfdx; */
498 sc = (struct kr_softc *)arg;
501 mii = device_get_softc(sc->kr_miibus);
503 if (mii == NULL || ifp == NULL ||
504 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
509 if (mii->mii_media_status & IFM_ACTIVE) {
510 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
511 sc->kr_link_status = 1;
513 sc->kr_link_status = 0;
519 kr_reset(struct kr_softc *sc)
523 CSR_WRITE_4(sc, KR_ETHINTFC, 0);
525 for (i = 0; i < KR_TIMEOUT; i++) {
527 if (!(CSR_READ_4(sc, KR_ETHINTFC) & ETH_INTFC_RIP))
532 device_printf(sc->kr_dev, "reset time out\n");
538 struct kr_softc *sc = xsc;
546 kr_init_locked(struct kr_softc *sc)
548 struct ifnet *ifp = sc->kr_ifp;
549 struct mii_data *mii;
553 mii = device_get_softc(sc->kr_miibus);
558 CSR_WRITE_4(sc, KR_ETHINTFC, ETH_INTFC_EN);
560 /* Init circular RX list. */
561 if (kr_rx_ring_init(sc) != 0) {
562 device_printf(sc->kr_dev,
563 "initialization failed: no memory for rx buffers\n");
568 /* Init tx descriptors. */
571 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_S, 0);
572 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_NDPTR, 0);
573 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_DPTR,
574 sc->kr_rdata.kr_rx_ring_paddr);
577 KR_DMA_CLEARBITS_REG(KR_DMA_RXCHAN, DMA_SM,
578 DMA_SM_H | DMA_SM_E | DMA_SM_D) ;
580 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_S, 0);
581 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_NDPTR, 0);
582 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_DPTR, 0);
583 KR_DMA_CLEARBITS_REG(KR_DMA_TXCHAN, DMA_SM,
584 DMA_SM_F | DMA_SM_E);
587 /* Accept only packets destined for THIS Ethernet device address */
588 CSR_WRITE_4(sc, KR_ETHARC, 1);
591 * Set all Ethernet address registers to the same initial values
592 * set all four addresses to 66-88-aa-cc-dd-ee
594 CSR_WRITE_4(sc, KR_ETHSAL0, 0x42095E6B);
595 CSR_WRITE_4(sc, KR_ETHSAH0, 0x0000000C);
597 CSR_WRITE_4(sc, KR_ETHSAL1, 0x42095E6B);
598 CSR_WRITE_4(sc, KR_ETHSAH1, 0x0000000C);
600 CSR_WRITE_4(sc, KR_ETHSAL2, 0x42095E6B);
601 CSR_WRITE_4(sc, KR_ETHSAH2, 0x0000000C);
603 CSR_WRITE_4(sc, KR_ETHSAL3, 0x42095E6B);
604 CSR_WRITE_4(sc, KR_ETHSAH3, 0x0000000C);
606 CSR_WRITE_4(sc, KR_ETHMAC2,
607 KR_ETH_MAC2_PEN | KR_ETH_MAC2_CEN | KR_ETH_MAC2_FD);
609 CSR_WRITE_4(sc, KR_ETHIPGT, KR_ETHIPGT_FULL_DUPLEX);
610 CSR_WRITE_4(sc, KR_ETHIPGR, 0x12); /* minimum value */
612 CSR_WRITE_4(sc, KR_MIIMCFG, KR_MIIMCFG_R);
614 CSR_WRITE_4(sc, KR_MIIMCFG, 0);
616 /* TODO: calculate prescale */
617 CSR_WRITE_4(sc, KR_ETHMCP, (165000000 / (1250000 + 1)) & ~1);
619 /* FIFO Tx threshold level */
620 CSR_WRITE_4(sc, KR_ETHFIFOTT, 0x30);
622 CSR_WRITE_4(sc, KR_ETHMAC1, KR_ETH_MAC1_RE);
624 sc->kr_link_status = 0;
627 ifp->if_drv_flags |= IFF_DRV_RUNNING;
628 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
630 callout_reset(&sc->kr_stat_callout, hz, kr_tick, sc);
634 kr_start(struct ifnet *ifp)
641 kr_start_locked(ifp);
646 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
647 * pointers to the fragment pointers.
650 kr_encap(struct kr_softc *sc, struct mbuf **m_head)
652 struct kr_txdesc *txd;
653 struct kr_desc *desc, *prev_desc;
654 bus_dma_segment_t txsegs[KR_MAXFRAGS];
656 int error, i, nsegs, prod, si, prev_prod;
660 prod = sc->kr_cdata.kr_tx_prod;
661 txd = &sc->kr_cdata.kr_txdesc[prod];
662 error = bus_dmamap_load_mbuf_sg(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap,
663 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
664 if (error == EFBIG) {
666 } else if (error != 0)
674 /* Check number of available descriptors. */
675 if (sc->kr_cdata.kr_tx_cnt + nsegs >= (KR_TX_RING_CNT - 1)) {
676 bus_dmamap_unload(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap);
681 bus_dmamap_sync(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap,
682 BUS_DMASYNC_PREWRITE);
687 * Make a list of descriptors for this packet. DMA controller will
688 * walk through it while kr_link is not zero. The last one should
689 * have COF flag set, to pickup next chain from NDPTR
692 desc = prev_desc = NULL;
693 for (i = 0; i < nsegs; i++) {
694 desc = &sc->kr_rdata.kr_tx_ring[prod];
695 desc->kr_ctl = KR_DMASIZE(txsegs[i].ds_len) | KR_CTL_IOF;
697 desc->kr_devcs = KR_DMATX_DEVCS_FD;
698 desc->kr_ca = txsegs[i].ds_addr;
700 /* link with previous descriptor */
702 prev_desc->kr_link = KR_TX_RING_ADDR(sc, prod);
704 sc->kr_cdata.kr_tx_cnt++;
706 KR_INC(prod, KR_TX_RING_CNT);
710 * Set COF for last descriptor and mark last fragment with LD flag
713 desc->kr_ctl |= KR_CTL_COF;
714 desc->kr_devcs |= KR_DMATX_DEVCS_LD;
717 /* Update producer index. */
718 sc->kr_cdata.kr_tx_prod = prod;
720 /* Sync descriptors. */
721 bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
722 sc->kr_cdata.kr_tx_ring_map,
723 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
725 /* Start transmitting */
726 /* Check if new list is queued in NDPTR */
727 if (KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_NDPTR) == 0) {
728 /* NDPTR is not busy - start new list */
729 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_NDPTR,
730 KR_TX_RING_ADDR(sc, si));
733 link_addr = KR_TX_RING_ADDR(sc, si);
734 /* Get previous descriptor */
735 si = (si + KR_TX_RING_CNT - 1) % KR_TX_RING_CNT;
736 desc = &sc->kr_rdata.kr_tx_ring[si];
737 desc->kr_link = link_addr;
744 kr_start_locked(struct ifnet *ifp)
754 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
755 IFF_DRV_RUNNING || sc->kr_link_status == 0 )
758 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
759 sc->kr_cdata.kr_tx_cnt < KR_TX_RING_CNT - 2; ) {
760 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
764 * Pack the data into the transmit ring. If we
765 * don't have room, set the OACTIVE flag and wait
766 * for the NIC to drain the ring.
768 if (kr_encap(sc, &m_head)) {
771 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
772 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
778 * If there's a BPF listener, bounce a copy of this frame
781 ETHER_BPF_MTAP(ifp, m_head);
786 kr_stop(struct kr_softc *sc)
794 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
795 callout_stop(&sc->kr_stat_callout);
797 /* mask out RX interrupts */
798 KR_DMA_SETBITS_REG(KR_DMA_RXCHAN, DMA_SM,
799 DMA_SM_D | DMA_SM_H | DMA_SM_E);
801 /* mask out TX interrupts */
802 KR_DMA_SETBITS_REG(KR_DMA_TXCHAN, DMA_SM,
803 DMA_SM_F | DMA_SM_E);
805 /* Abort RX DMA transactions */
806 if (KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_C) & DMA_C_R) {
807 /* Set ABORT bit if trunsuction is in progress */
808 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_C, DMA_C_ABORT);
809 /* XXX: Add timeout */
810 while ((KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_S) & DMA_S_H) == 0)
812 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_S, 0);
814 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_DPTR, 0);
815 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_NDPTR, 0);
817 /* Abort TX DMA transactions */
818 if (KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_C) & DMA_C_R) {
819 /* Set ABORT bit if trunsuction is in progress */
820 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_C, DMA_C_ABORT);
821 /* XXX: Add timeout */
822 while ((KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_S) & DMA_S_H) == 0)
824 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_S, 0);
826 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_DPTR, 0);
827 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_NDPTR, 0);
829 CSR_WRITE_4(sc, KR_ETHINTFC, 0);
834 kr_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
836 struct kr_softc *sc = ifp->if_softc;
837 struct ifreq *ifr = (struct ifreq *) data;
838 struct mii_data *mii;
845 if (ifp->if_flags & IFF_UP) {
846 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
847 if ((ifp->if_flags ^ sc->kr_if_flags) &
848 (IFF_PROMISC | IFF_ALLMULTI))
851 if (sc->kr_detach == 0)
855 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
858 sc->kr_if_flags = ifp->if_flags;
874 mii = device_get_softc(sc->kr_miibus);
875 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
880 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
881 if ((mask & IFCAP_HWCSUM) != 0) {
882 ifp->if_capenable ^= IFCAP_HWCSUM;
883 if ((IFCAP_HWCSUM & ifp->if_capenable) &&
884 (IFCAP_HWCSUM & ifp->if_capabilities))
885 ifp->if_hwassist = KR_CSUM_FEATURES;
887 ifp->if_hwassist = 0;
889 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
890 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
891 if (IFCAP_VLAN_HWTAGGING & ifp->if_capenable &&
892 IFCAP_VLAN_HWTAGGING & ifp->if_capabilities &&
893 ifp->if_drv_flags & IFF_DRV_RUNNING) {
899 VLAN_CAPABILITIES(ifp);
903 error = ether_ioctl(ifp, command, data);
914 kr_ifmedia_upd(struct ifnet *ifp)
917 struct mii_data *mii;
918 struct mii_softc *miisc;
923 mii = device_get_softc(sc->kr_miibus);
924 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
926 error = mii_mediachg(mii);
933 * Report current media status.
936 kr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
938 struct kr_softc *sc = ifp->if_softc;
939 struct mii_data *mii;
941 mii = device_get_softc(sc->kr_miibus);
944 ifmr->ifm_active = mii->mii_media_active;
945 ifmr->ifm_status = mii->mii_media_status;
949 struct kr_dmamap_arg {
950 bus_addr_t kr_busaddr;
954 kr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
956 struct kr_dmamap_arg *ctx;
961 ctx->kr_busaddr = segs[0].ds_addr;
965 kr_dma_alloc(struct kr_softc *sc)
967 struct kr_dmamap_arg ctx;
968 struct kr_txdesc *txd;
969 struct kr_rxdesc *rxd;
972 /* Create parent DMA tag. */
973 error = bus_dma_tag_create(
974 bus_get_dma_tag(sc->kr_dev), /* parent */
975 1, 0, /* alignment, boundary */
976 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
977 BUS_SPACE_MAXADDR, /* highaddr */
978 NULL, NULL, /* filter, filterarg */
979 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
981 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
983 NULL, NULL, /* lockfunc, lockarg */
984 &sc->kr_cdata.kr_parent_tag);
986 device_printf(sc->kr_dev, "failed to create parent DMA tag\n");
989 /* Create tag for Tx ring. */
990 error = bus_dma_tag_create(
991 sc->kr_cdata.kr_parent_tag, /* parent */
992 KR_RING_ALIGN, 0, /* alignment, boundary */
993 BUS_SPACE_MAXADDR, /* lowaddr */
994 BUS_SPACE_MAXADDR, /* highaddr */
995 NULL, NULL, /* filter, filterarg */
996 KR_TX_RING_SIZE, /* maxsize */
998 KR_TX_RING_SIZE, /* maxsegsize */
1000 NULL, NULL, /* lockfunc, lockarg */
1001 &sc->kr_cdata.kr_tx_ring_tag);
1003 device_printf(sc->kr_dev, "failed to create Tx ring DMA tag\n");
1007 /* Create tag for Rx ring. */
1008 error = bus_dma_tag_create(
1009 sc->kr_cdata.kr_parent_tag, /* parent */
1010 KR_RING_ALIGN, 0, /* alignment, boundary */
1011 BUS_SPACE_MAXADDR, /* lowaddr */
1012 BUS_SPACE_MAXADDR, /* highaddr */
1013 NULL, NULL, /* filter, filterarg */
1014 KR_RX_RING_SIZE, /* maxsize */
1016 KR_RX_RING_SIZE, /* maxsegsize */
1018 NULL, NULL, /* lockfunc, lockarg */
1019 &sc->kr_cdata.kr_rx_ring_tag);
1021 device_printf(sc->kr_dev, "failed to create Rx ring DMA tag\n");
1025 /* Create tag for Tx buffers. */
1026 error = bus_dma_tag_create(
1027 sc->kr_cdata.kr_parent_tag, /* parent */
1028 sizeof(uint32_t), 0, /* alignment, boundary */
1029 BUS_SPACE_MAXADDR, /* lowaddr */
1030 BUS_SPACE_MAXADDR, /* highaddr */
1031 NULL, NULL, /* filter, filterarg */
1032 MCLBYTES * KR_MAXFRAGS, /* maxsize */
1033 KR_MAXFRAGS, /* nsegments */
1034 MCLBYTES, /* maxsegsize */
1036 NULL, NULL, /* lockfunc, lockarg */
1037 &sc->kr_cdata.kr_tx_tag);
1039 device_printf(sc->kr_dev, "failed to create Tx DMA tag\n");
1043 /* Create tag for Rx buffers. */
1044 error = bus_dma_tag_create(
1045 sc->kr_cdata.kr_parent_tag, /* parent */
1046 KR_RX_ALIGN, 0, /* alignment, boundary */
1047 BUS_SPACE_MAXADDR, /* lowaddr */
1048 BUS_SPACE_MAXADDR, /* highaddr */
1049 NULL, NULL, /* filter, filterarg */
1050 MCLBYTES, /* maxsize */
1052 MCLBYTES, /* maxsegsize */
1054 NULL, NULL, /* lockfunc, lockarg */
1055 &sc->kr_cdata.kr_rx_tag);
1057 device_printf(sc->kr_dev, "failed to create Rx DMA tag\n");
1061 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1062 error = bus_dmamem_alloc(sc->kr_cdata.kr_tx_ring_tag,
1063 (void **)&sc->kr_rdata.kr_tx_ring, BUS_DMA_WAITOK |
1064 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->kr_cdata.kr_tx_ring_map);
1066 device_printf(sc->kr_dev,
1067 "failed to allocate DMA'able memory for Tx ring\n");
1072 error = bus_dmamap_load(sc->kr_cdata.kr_tx_ring_tag,
1073 sc->kr_cdata.kr_tx_ring_map, sc->kr_rdata.kr_tx_ring,
1074 KR_TX_RING_SIZE, kr_dmamap_cb, &ctx, 0);
1075 if (error != 0 || ctx.kr_busaddr == 0) {
1076 device_printf(sc->kr_dev,
1077 "failed to load DMA'able memory for Tx ring\n");
1080 sc->kr_rdata.kr_tx_ring_paddr = ctx.kr_busaddr;
1082 /* Allocate DMA'able memory and load the DMA map for Rx ring. */
1083 error = bus_dmamem_alloc(sc->kr_cdata.kr_rx_ring_tag,
1084 (void **)&sc->kr_rdata.kr_rx_ring, BUS_DMA_WAITOK |
1085 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->kr_cdata.kr_rx_ring_map);
1087 device_printf(sc->kr_dev,
1088 "failed to allocate DMA'able memory for Rx ring\n");
1093 error = bus_dmamap_load(sc->kr_cdata.kr_rx_ring_tag,
1094 sc->kr_cdata.kr_rx_ring_map, sc->kr_rdata.kr_rx_ring,
1095 KR_RX_RING_SIZE, kr_dmamap_cb, &ctx, 0);
1096 if (error != 0 || ctx.kr_busaddr == 0) {
1097 device_printf(sc->kr_dev,
1098 "failed to load DMA'able memory for Rx ring\n");
1101 sc->kr_rdata.kr_rx_ring_paddr = ctx.kr_busaddr;
1103 /* Create DMA maps for Tx buffers. */
1104 for (i = 0; i < KR_TX_RING_CNT; i++) {
1105 txd = &sc->kr_cdata.kr_txdesc[i];
1107 txd->tx_dmamap = NULL;
1108 error = bus_dmamap_create(sc->kr_cdata.kr_tx_tag, 0,
1111 device_printf(sc->kr_dev,
1112 "failed to create Tx dmamap\n");
1116 /* Create DMA maps for Rx buffers. */
1117 if ((error = bus_dmamap_create(sc->kr_cdata.kr_rx_tag, 0,
1118 &sc->kr_cdata.kr_rx_sparemap)) != 0) {
1119 device_printf(sc->kr_dev,
1120 "failed to create spare Rx dmamap\n");
1123 for (i = 0; i < KR_RX_RING_CNT; i++) {
1124 rxd = &sc->kr_cdata.kr_rxdesc[i];
1126 rxd->rx_dmamap = NULL;
1127 error = bus_dmamap_create(sc->kr_cdata.kr_rx_tag, 0,
1130 device_printf(sc->kr_dev,
1131 "failed to create Rx dmamap\n");
1141 kr_dma_free(struct kr_softc *sc)
1143 struct kr_txdesc *txd;
1144 struct kr_rxdesc *rxd;
1148 if (sc->kr_cdata.kr_tx_ring_tag) {
1149 if (sc->kr_cdata.kr_tx_ring_map)
1150 bus_dmamap_unload(sc->kr_cdata.kr_tx_ring_tag,
1151 sc->kr_cdata.kr_tx_ring_map);
1152 if (sc->kr_cdata.kr_tx_ring_map &&
1153 sc->kr_rdata.kr_tx_ring)
1154 bus_dmamem_free(sc->kr_cdata.kr_tx_ring_tag,
1155 sc->kr_rdata.kr_tx_ring,
1156 sc->kr_cdata.kr_tx_ring_map);
1157 sc->kr_rdata.kr_tx_ring = NULL;
1158 sc->kr_cdata.kr_tx_ring_map = NULL;
1159 bus_dma_tag_destroy(sc->kr_cdata.kr_tx_ring_tag);
1160 sc->kr_cdata.kr_tx_ring_tag = NULL;
1163 if (sc->kr_cdata.kr_rx_ring_tag) {
1164 if (sc->kr_cdata.kr_rx_ring_map)
1165 bus_dmamap_unload(sc->kr_cdata.kr_rx_ring_tag,
1166 sc->kr_cdata.kr_rx_ring_map);
1167 if (sc->kr_cdata.kr_rx_ring_map &&
1168 sc->kr_rdata.kr_rx_ring)
1169 bus_dmamem_free(sc->kr_cdata.kr_rx_ring_tag,
1170 sc->kr_rdata.kr_rx_ring,
1171 sc->kr_cdata.kr_rx_ring_map);
1172 sc->kr_rdata.kr_rx_ring = NULL;
1173 sc->kr_cdata.kr_rx_ring_map = NULL;
1174 bus_dma_tag_destroy(sc->kr_cdata.kr_rx_ring_tag);
1175 sc->kr_cdata.kr_rx_ring_tag = NULL;
1178 if (sc->kr_cdata.kr_tx_tag) {
1179 for (i = 0; i < KR_TX_RING_CNT; i++) {
1180 txd = &sc->kr_cdata.kr_txdesc[i];
1181 if (txd->tx_dmamap) {
1182 bus_dmamap_destroy(sc->kr_cdata.kr_tx_tag,
1184 txd->tx_dmamap = NULL;
1187 bus_dma_tag_destroy(sc->kr_cdata.kr_tx_tag);
1188 sc->kr_cdata.kr_tx_tag = NULL;
1191 if (sc->kr_cdata.kr_rx_tag) {
1192 for (i = 0; i < KR_RX_RING_CNT; i++) {
1193 rxd = &sc->kr_cdata.kr_rxdesc[i];
1194 if (rxd->rx_dmamap) {
1195 bus_dmamap_destroy(sc->kr_cdata.kr_rx_tag,
1197 rxd->rx_dmamap = NULL;
1200 if (sc->kr_cdata.kr_rx_sparemap) {
1201 bus_dmamap_destroy(sc->kr_cdata.kr_rx_tag,
1202 sc->kr_cdata.kr_rx_sparemap);
1203 sc->kr_cdata.kr_rx_sparemap = 0;
1205 bus_dma_tag_destroy(sc->kr_cdata.kr_rx_tag);
1206 sc->kr_cdata.kr_rx_tag = NULL;
1209 if (sc->kr_cdata.kr_parent_tag) {
1210 bus_dma_tag_destroy(sc->kr_cdata.kr_parent_tag);
1211 sc->kr_cdata.kr_parent_tag = NULL;
1216 * Initialize the transmit descriptors.
1219 kr_tx_ring_init(struct kr_softc *sc)
1221 struct kr_ring_data *rd;
1222 struct kr_txdesc *txd;
1226 sc->kr_cdata.kr_tx_prod = 0;
1227 sc->kr_cdata.kr_tx_cons = 0;
1228 sc->kr_cdata.kr_tx_cnt = 0;
1229 sc->kr_cdata.kr_tx_pkts = 0;
1232 bzero(rd->kr_tx_ring, KR_TX_RING_SIZE);
1233 for (i = 0; i < KR_TX_RING_CNT; i++) {
1234 if (i == KR_TX_RING_CNT - 1)
1235 addr = KR_TX_RING_ADDR(sc, 0);
1237 addr = KR_TX_RING_ADDR(sc, i + 1);
1238 rd->kr_tx_ring[i].kr_ctl = KR_CTL_IOF;
1239 rd->kr_tx_ring[i].kr_ca = 0;
1240 rd->kr_tx_ring[i].kr_devcs = 0;
1241 rd->kr_tx_ring[i].kr_link = 0;
1242 txd = &sc->kr_cdata.kr_txdesc[i];
1246 bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
1247 sc->kr_cdata.kr_tx_ring_map,
1248 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1254 * Initialize the RX descriptors and allocate mbufs for them. Note that
1255 * we arrange the descriptors in a closed ring, so that the last descriptor
1256 * points back to the first.
1259 kr_rx_ring_init(struct kr_softc *sc)
1261 struct kr_ring_data *rd;
1262 struct kr_rxdesc *rxd;
1266 sc->kr_cdata.kr_rx_cons = 0;
1269 bzero(rd->kr_rx_ring, KR_RX_RING_SIZE);
1270 for (i = 0; i < KR_RX_RING_CNT; i++) {
1271 rxd = &sc->kr_cdata.kr_rxdesc[i];
1273 rxd->desc = &rd->kr_rx_ring[i];
1274 if (i == KR_RX_RING_CNT - 1)
1275 addr = KR_RX_RING_ADDR(sc, 0);
1277 addr = KR_RX_RING_ADDR(sc, i + 1);
1278 rd->kr_rx_ring[i].kr_ctl = KR_CTL_IOD;
1279 if (i == KR_RX_RING_CNT - 1)
1280 rd->kr_rx_ring[i].kr_ctl |= KR_CTL_COD;
1281 rd->kr_rx_ring[i].kr_devcs = 0;
1282 rd->kr_rx_ring[i].kr_ca = 0;
1283 rd->kr_rx_ring[i].kr_link = addr;
1284 if (kr_newbuf(sc, i) != 0)
1288 bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
1289 sc->kr_cdata.kr_rx_ring_map,
1290 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1296 * Initialize an RX descriptor and attach an MBUF cluster.
1299 kr_newbuf(struct kr_softc *sc, int idx)
1301 struct kr_desc *desc;
1302 struct kr_rxdesc *rxd;
1304 bus_dma_segment_t segs[1];
1308 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1311 m->m_len = m->m_pkthdr.len = MCLBYTES;
1312 m_adj(m, sizeof(uint64_t));
1314 if (bus_dmamap_load_mbuf_sg(sc->kr_cdata.kr_rx_tag,
1315 sc->kr_cdata.kr_rx_sparemap, m, segs, &nsegs, 0) != 0) {
1319 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1321 rxd = &sc->kr_cdata.kr_rxdesc[idx];
1322 if (rxd->rx_m != NULL) {
1323 bus_dmamap_sync(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap,
1324 BUS_DMASYNC_POSTREAD);
1325 bus_dmamap_unload(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap);
1327 map = rxd->rx_dmamap;
1328 rxd->rx_dmamap = sc->kr_cdata.kr_rx_sparemap;
1329 sc->kr_cdata.kr_rx_sparemap = map;
1330 bus_dmamap_sync(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap,
1331 BUS_DMASYNC_PREREAD);
1334 desc->kr_ca = segs[0].ds_addr;
1335 desc->kr_ctl |= KR_DMASIZE(segs[0].ds_len);
1336 rxd->saved_ca = desc->kr_ca ;
1337 rxd->saved_ctl = desc->kr_ctl ;
1342 static __inline void
1343 kr_fixup_rx(struct mbuf *m)
1346 uint16_t *src, *dst;
1348 src = mtod(m, uint16_t *);
1351 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1354 m->m_data -= ETHER_ALIGN;
1359 kr_tx(struct kr_softc *sc)
1361 struct kr_txdesc *txd;
1362 struct kr_desc *cur_tx;
1364 uint32_t ctl, devcs;
1369 cons = sc->kr_cdata.kr_tx_cons;
1370 prod = sc->kr_cdata.kr_tx_prod;
1374 bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
1375 sc->kr_cdata.kr_tx_ring_map,
1376 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1380 * Go through our tx list and free mbufs for those
1381 * frames that have been transmitted.
1383 for (; cons != prod; KR_INC(cons, KR_TX_RING_CNT)) {
1384 cur_tx = &sc->kr_rdata.kr_tx_ring[cons];
1385 ctl = cur_tx->kr_ctl;
1386 devcs = cur_tx->kr_devcs;
1387 /* Check if descriptor has "finished" flag */
1388 if ((ctl & KR_CTL_F) == 0)
1391 sc->kr_cdata.kr_tx_cnt--;
1392 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1394 txd = &sc->kr_cdata.kr_txdesc[cons];
1396 if (devcs & KR_DMATX_DEVCS_TOK)
1400 /* collisions: medium busy, late collision */
1401 if ((devcs & KR_DMATX_DEVCS_EC) ||
1402 (devcs & KR_DMATX_DEVCS_LC))
1403 ifp->if_collisions++;
1406 bus_dmamap_sync(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap,
1407 BUS_DMASYNC_POSTWRITE);
1408 bus_dmamap_unload(sc->kr_cdata.kr_tx_tag, txd->tx_dmamap);
1410 /* Free only if it's first descriptor in list */
1415 /* reset descriptor */
1416 cur_tx->kr_ctl = KR_CTL_IOF;
1417 cur_tx->kr_devcs = 0;
1419 cur_tx->kr_link = 0;
1422 sc->kr_cdata.kr_tx_cons = cons;
1424 bus_dmamap_sync(sc->kr_cdata.kr_tx_ring_tag,
1425 sc->kr_cdata.kr_tx_ring_map, BUS_DMASYNC_PREWRITE);
1430 kr_rx(struct kr_softc *sc)
1432 struct kr_rxdesc *rxd;
1433 struct ifnet *ifp = sc->kr_ifp;
1434 int cons, prog, packet_len, count, error;
1435 struct kr_desc *cur_rx;
1440 cons = sc->kr_cdata.kr_rx_cons;
1442 bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
1443 sc->kr_cdata.kr_rx_ring_map,
1444 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1446 for (prog = 0; prog < KR_RX_RING_CNT; KR_INC(cons, KR_RX_RING_CNT)) {
1447 cur_rx = &sc->kr_rdata.kr_rx_ring[cons];
1448 rxd = &sc->kr_cdata.kr_rxdesc[cons];
1451 if ((cur_rx->kr_ctl & KR_CTL_D) == 0)
1456 packet_len = KR_PKTSIZE(cur_rx->kr_devcs);
1457 count = m->m_len - KR_DMASIZE(cur_rx->kr_ctl);
1458 /* Assume it's error */
1461 if (packet_len != count)
1463 else if (count < 64)
1465 else if ((cur_rx->kr_devcs & KR_DMARX_DEVCS_LD) == 0)
1467 else if ((cur_rx->kr_devcs & KR_DMARX_DEVCS_ROK) != 0) {
1469 bus_dmamap_sync(sc->kr_cdata.kr_rx_tag, rxd->rx_dmamap,
1470 BUS_DMASYNC_PREREAD);
1473 m->m_pkthdr.rcvif = ifp;
1474 /* Skip 4 bytes of CRC */
1475 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
1479 (*ifp->if_input)(ifp, m);
1484 /* Restore CONTROL and CA values, reset DEVCS */
1485 cur_rx->kr_ctl = rxd->saved_ctl;
1486 cur_rx->kr_ca = rxd->saved_ca;
1487 cur_rx->kr_devcs = 0;
1490 /* Reinit descriptor */
1491 cur_rx->kr_ctl = KR_CTL_IOD;
1492 if (cons == KR_RX_RING_CNT - 1)
1493 cur_rx->kr_ctl |= KR_CTL_COD;
1494 cur_rx->kr_devcs = 0;
1496 if (kr_newbuf(sc, cons) != 0) {
1497 device_printf(sc->kr_dev,
1498 "Failed to allocate buffer\n");
1503 bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
1504 sc->kr_cdata.kr_rx_ring_map,
1505 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1510 sc->kr_cdata.kr_rx_cons = cons;
1512 bus_dmamap_sync(sc->kr_cdata.kr_rx_ring_tag,
1513 sc->kr_cdata.kr_rx_ring_map,
1514 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1519 kr_rx_intr(void *arg)
1521 struct kr_softc *sc = arg;
1526 /* mask out interrupts */
1527 KR_DMA_SETBITS_REG(KR_DMA_RXCHAN, DMA_SM,
1528 DMA_SM_D | DMA_SM_H | DMA_SM_E);
1530 status = KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_S);
1531 if (status & (DMA_S_D | DMA_S_E | DMA_S_H)) {
1534 if (status & DMA_S_E)
1535 device_printf(sc->kr_dev, "RX DMA error\n");
1539 status = KR_DMA_READ_REG(KR_DMA_RXCHAN, DMA_S);
1541 /* restart DMA RX if it has been halted */
1542 if (status & DMA_S_H) {
1543 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_DPTR,
1544 KR_RX_RING_ADDR(sc, sc->kr_cdata.kr_rx_cons));
1547 KR_DMA_WRITE_REG(KR_DMA_RXCHAN, DMA_S, ~status);
1549 /* Enable F, H, E interrupts */
1550 KR_DMA_CLEARBITS_REG(KR_DMA_RXCHAN, DMA_SM,
1551 DMA_SM_D | DMA_SM_H | DMA_SM_E);
1557 kr_tx_intr(void *arg)
1559 struct kr_softc *sc = arg;
1564 /* mask out interrupts */
1565 KR_DMA_SETBITS_REG(KR_DMA_TXCHAN, DMA_SM,
1566 DMA_SM_F | DMA_SM_E);
1568 status = KR_DMA_READ_REG(KR_DMA_TXCHAN, DMA_S);
1569 if (status & (DMA_S_F | DMA_S_E)) {
1571 if (status & DMA_S_E)
1572 device_printf(sc->kr_dev, "DMA error\n");
1575 KR_DMA_WRITE_REG(KR_DMA_TXCHAN, DMA_S, ~status);
1577 /* Enable F, E interrupts */
1578 KR_DMA_CLEARBITS_REG(KR_DMA_TXCHAN, DMA_SM,
1579 DMA_SM_F | DMA_SM_E);
1586 kr_rx_und_intr(void *arg)
1589 panic("interrupt: %s\n", __func__);
1593 kr_tx_ovr_intr(void *arg)
1596 panic("interrupt: %s\n", __func__);
1602 struct kr_softc *sc = xsc;
1603 struct mii_data *mii;
1607 mii = device_get_softc(sc->kr_miibus);
1609 callout_reset(&sc->kr_stat_callout, hz, kr_tick, sc);