1 /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
4 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
33 * 1. Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in the
37 * documentation and/or other materials provided with the distribution.
38 * 3. All advertising materials mentioning features or use of this software
39 * must display the following acknowledgement:
40 * This product includes software developed by Per Fogelstrom.
41 * 4. The name of the author may not be used to endorse or promote products
42 * derived from this software without specific prior written permission
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
59 #ifndef _MACHINE_CPUFUNC_H_
60 #define _MACHINE_CPUFUNC_H_
62 #include <sys/types.h>
63 #include <machine/cpuregs.h>
66 * These functions are required by user-land atomi ops
72 #if defined(CPU_CNMIPS) || defined(CPU_RMI) || defined(CPU_NLM)
75 __asm __volatile (".set noreorder\n\t"
92 __asm __volatile (__XSTRING(COP0_SYNC));
98 #if defined(CPU_CNMIPS)
99 __asm __volatile (".set noreorder\n\t"
104 __asm __volatile ("sync" : : : "memory");
112 * It would be nice to add variants that read/write register_t, to avoid some
115 #if defined(__mips_n32) || defined(__mips_n64)
116 #define MIPS_RW64_COP0(n,r) \
117 static __inline uint64_t \
118 mips_rd_ ## n (void) \
121 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
126 static __inline void \
127 mips_wr_ ## n (uint64_t a0) \
129 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
130 __XSTRING(COP0_SYNC)";" \
138 #define MIPS_RW64_COP0_SEL(n,r,s) \
139 static __inline uint64_t \
140 mips_rd_ ## n(void) \
143 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
148 static __inline void \
149 mips_wr_ ## n(uint64_t a0) \
151 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
152 __XSTRING(COP0_SYNC)";" \
158 #if defined(__mips_n64)
159 MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC);
160 MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
161 MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
163 MIPS_RW64_COP0_SEL(cvmcount, MIPS_COP_0_COUNT, 6);
164 MIPS_RW64_COP0_SEL(cvmctl, MIPS_COP_0_COUNT, 7);
165 MIPS_RW64_COP0_SEL(cvmmemctl, MIPS_COP_0_COMPARE, 7);
166 MIPS_RW64_COP0_SEL(icache_err, MIPS_COP_0_CACHE_ERR, 0);
167 MIPS_RW64_COP0_SEL(dcache_err, MIPS_COP_0_CACHE_ERR, 1);
170 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
171 MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
172 MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
174 MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
176 #undef MIPS_RW64_COP0
177 #undef MIPS_RW64_COP0_SEL
180 #define MIPS_RW32_COP0(n,r) \
181 static __inline uint32_t \
182 mips_rd_ ## n (void) \
185 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
190 static __inline void \
191 mips_wr_ ## n (uint32_t a0) \
193 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
194 __XSTRING(COP0_SYNC)";" \
202 #define MIPS_RW32_COP0_SEL(n,r,s) \
203 static __inline uint32_t \
204 mips_rd_ ## n(void) \
207 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
212 static __inline void \
213 mips_wr_ ## n(uint32_t a0) \
215 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
216 __XSTRING(COP0_SYNC)";" \
225 static __inline void mips_sync_icache (void)
230 ".word 0x041f0000\n" /* xxx ICACHE */
237 MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE);
238 MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG);
239 MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
240 MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
241 MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
243 MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4);
246 MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6);
247 MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7);
249 MIPS_RW32_COP0(count, MIPS_COP_0_COUNT);
250 MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX);
251 MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
252 MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE);
253 #if !defined(__mips_n64)
254 MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC);
256 MIPS_RW32_COP0(status, MIPS_COP_0_STATUS);
258 /* XXX: Some of these registers are specific to MIPS32. */
259 #if !defined(__mips_n64)
260 MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
261 MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
264 MIPS_RW32_COP0_SEL(pagegrain, MIPS_COP_0_TLB_PG_MASK, 1);
266 #if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
267 MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
268 MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
270 MIPS_RW32_COP0(prid, MIPS_COP_0_PRID);
272 MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
273 MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
274 MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
275 MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
276 MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
277 MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
278 MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
279 MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
280 MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
282 MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
283 MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
284 MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
285 MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
287 #undef MIPS_RW32_COP0
288 #undef MIPS_RW32_COP0_SEL
290 static __inline register_t
295 s = mips_rd_status();
296 mips_wr_status(s & ~MIPS_SR_INT_IE);
298 return (s & MIPS_SR_INT_IE);
301 static __inline register_t
306 s = mips_rd_status();
307 mips_wr_status(s | MIPS_SR_INT_IE);
313 intr_restore(register_t ie)
315 if (ie == MIPS_SR_INT_IE) {
320 static __inline uint32_t
321 set_intr_mask(uint32_t mask)
325 ostatus = mips_rd_status();
326 mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
327 mips_wr_status(mask);
331 static __inline uint32_t
335 return (mips_rd_status() & MIPS_SR_INT_MASK);
341 __asm __volatile ("break");
344 #if defined(__GNUC__) && !defined(__mips_o32)
345 #define mips3_ld(a) (*(const volatile uint64_t *)(a))
346 #define mips3_sd(a, v) (*(volatile uint64_t *)(a) = (v))
348 uint64_t mips3_ld(volatile uint64_t *va);
349 void mips3_sd(volatile uint64_t *, uint64_t);
350 #endif /* __GNUC__ */
354 #define readb(va) (*(volatile uint8_t *) (va))
355 #define readw(va) (*(volatile uint16_t *) (va))
356 #define readl(va) (*(volatile uint32_t *) (va))
357 #if defined(__GNUC__) && !defined(__mips_o32)
358 #define readq(a) (*(volatile uint64_t *)(a))
361 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
362 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
363 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
364 #if defined(__GNUC__) && !defined(__mips_o32)
365 #define writeq(va, d) (*(volatile uint64_t *) (va) = (d))
368 #endif /* !_MACHINE_CPUFUNC_H_ */