1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
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11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
38 * Machine dependent constants.
40 * Copyright (C) 1989 Digital Equipment Corporation.
41 * Permission to use, copy, modify, and distribute this software and
42 * its documentation for any purpose and without fee is hereby granted,
43 * provided that the above copyright notice appears in all copies.
44 * Digital Equipment Corporation makes no representations about the
45 * suitability of this software for any purpose. It is provided "as is"
46 * without express or implied warranty.
48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
58 #ifndef _MIPS_CPUREGS_H_
59 #define _MIPS_CPUREGS_H_
63 * 32-bit mips CPUS partition their 32-bit address space into four segments:
65 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
66 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
67 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
68 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
70 * Caching of mapped addresses is controlled by bits in the TLB entry.
73 #define MIPS_KSEG0_LARGEST_PHYS (0x20000000)
74 #define MIPS_KSEG0_PHYS_MASK (0x1fffffff)
75 #define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */
76 #define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff)
79 #define MIPS_KUSEG_START 0x00000000
80 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000)
81 #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff)
82 #define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000)
83 #define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff)
84 #define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000)
85 #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff)
86 #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000)
87 #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff)
88 #define MIPS_KSEG2_START MIPS_KSSEG_START
89 #define MIPS_KSEG2_END MIPS_KSSEG_END
92 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
93 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
94 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
95 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
97 #define MIPS_IS_KSEG0_ADDR(x) \
98 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
99 ((vm_offset_t)(x) <= MIPS_KSEG0_END))
100 #define MIPS_IS_KSEG1_ADDR(x) \
101 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
102 ((vm_offset_t)(x) <= MIPS_KSEG1_END))
103 #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
104 MIPS_IS_KSEG1_ADDR(x))
107 * Cache Coherency Attributes:
109 * UA: Uncached accelerated.
110 * C: Cacheable, coherency unspecified.
111 * CNC: Cacheable non-coherent.
112 * CC: Cacheable coherent.
113 * CCE: Cacheable coherent, exclusive read.
114 * CCEW: Cacheable coherent, exclusive write.
115 * CCUOW: Cacheable coherent, update on write.
117 * Note that some bits vary in meaning across implementations (and that the
118 * listing here is no doubt incomplete) and that the optimal cached mode varies
119 * between implementations. 0x02 is required to be UC and 0x03 is required to
122 * We define the following logical bits:
124 * The optimal uncached mode for the target CPU type. This must
125 * be suitable for use in accessing memory-mapped devices.
126 * CACHED: The optional cached mode for the target CPU type.
129 #define MIPS_CCA_UC 0x02 /* Uncached. */
130 #define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
132 #if defined(CPU_R4000) || defined(CPU_R10000)
133 #define MIPS_CCA_CNC 0x03
134 #define MIPS_CCA_CCE 0x04
135 #define MIPS_CCA_CCEW 0x05
138 #define MIPS_CCA_CCUOW 0x06
142 #define MIPS_CCA_UA 0x07
145 #define MIPS_CCA_CACHED MIPS_CCA_CCEW
146 #endif /* defined(CPU_R4000) || defined(CPU_R10000) */
149 #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
152 #if defined(CPU_MIPS74KC)
153 #define MIPS_CCA_UNCACHED 0x02
154 #define MIPS_CCA_CACHED 0x00
157 #ifndef MIPS_CCA_UNCACHED
158 #define MIPS_CCA_UNCACHED MIPS_CCA_UC
162 * If we don't know which cached mode to use and there is a cache coherent
163 * mode, use it. If there is not a cache coherent mode, use the required
166 #ifndef MIPS_CCA_CACHED
168 #define MIPS_CCA_CACHED MIPS_CCA_CC
170 #define MIPS_CCA_CACHED MIPS_CCA_C
174 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
175 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
176 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
177 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x))
178 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
179 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x))
181 #define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK)
183 #define MIPS_XKPHYS_START 0x8000000000000000
184 #define MIPS_XKPHYS_END 0xbfffffffffffffff
185 #define MIPS_XUSEG_START 0x0000000000000000
186 #define MIPS_XUSEG_END 0x0000010000000000
187 #define MIPS_XKSEG_START 0xc000000000000000
188 #define MIPS_XKSEG_END 0xc00000ff80000000
189 #define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000
190 #define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff
191 #define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff)
194 #define MIPS_DIRECT_MAPPABLE(pa) 1
195 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa)
196 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa)
197 #define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va)
199 #define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS)
200 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa)
201 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa)
202 #define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va)
205 /* CPU dependent mtc0 hazard hook */
206 #if defined(CPU_CNMIPS) || defined(CPU_RMI)
208 #elif defined(CPU_NLM)
209 #define COP0_SYNC .word 0xc0 /* ehb */
210 #elif defined(CPU_SB1)
211 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
212 #elif defined(CPU_MIPS74KC)
213 #define COP0_SYNC .word 0xc0 /* ehb */
216 * Pick a reasonable default based on the "typical" spacing described in the
217 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
219 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0;
221 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
224 * The bits in the cause register.
226 * Bits common to r3000 and r4000:
228 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
229 * MIPS_CR_COP_ERR Coprocessor error.
230 * MIPS_CR_IP Interrupt pending bits defined below.
231 * (same meaning as in CAUSE register).
232 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
235 * r3k has 4 bits of execption type, r4k has 5 bits.
237 #define MIPS_CR_BR_DELAY 0x80000000
238 #define MIPS_CR_COP_ERR 0x30000000
239 #define MIPS_CR_EXC_CODE 0x0000007C /* five bits */
240 #define MIPS_CR_IP 0x0000FF00
241 #define MIPS_CR_EXC_CODE_SHIFT 2
242 #define MIPS_CR_COP_ERR_SHIFT 28
245 * The bits in the status register. All bits are active when set to 1.
247 * R3000 status register fields:
248 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
249 * MIPS_SR_TS TLB shutdown.
251 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
254 * r3k has cache control is via frobbing SR register bits, whereas the
255 * r4k cache control is via explicit instructions.
256 * r3k has a 3-entry stack of kernel/user bits, whereas the
257 * r4k has kernel/supervisor/user.
259 #define MIPS_SR_COP_USABILITY 0xf0000000
260 #define MIPS_SR_COP_0_BIT 0x10000000
261 #define MIPS_SR_COP_1_BIT 0x20000000
262 #define MIPS_SR_COP_2_BIT 0x40000000
264 /* r4k and r3k differences, see below */
266 #define MIPS_SR_MX 0x01000000 /* MIPS64 */
267 #define MIPS_SR_PX 0x00800000 /* MIPS64 */
268 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
269 #define MIPS_SR_TS 0x00200000
270 #define MIPS_SR_DE 0x00010000
272 #define MIPS_SR_INT_IE 0x00000001
273 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
274 #define MIPS_SR_INT_MASK 0x0000ff00
277 * R4000 status register bit definitons,
278 * where different from r2000/r3000.
280 #define MIPS_SR_XX 0x80000000
281 #define MIPS_SR_RP 0x08000000
282 #define MIPS_SR_FR 0x04000000
283 #define MIPS_SR_RE 0x02000000
285 #define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */
286 #define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */
287 #define MIPS_SR_SR 0x00100000
288 #define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */
289 #define MIPS_SR_DIAG_CH 0x00040000
290 #define MIPS_SR_DIAG_CE 0x00020000
291 #define MIPS_SR_DIAG_PE 0x00010000
292 #define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */
293 #define MIPS_SR_KX 0x00000080
294 #define MIPS_SR_SX 0x00000040
295 #define MIPS_SR_UX 0x00000020
296 #define MIPS_SR_KSU_MASK 0x00000018
297 #define MIPS_SR_KSU_USER 0x00000010
298 #define MIPS_SR_KSU_SUPER 0x00000008
299 #define MIPS_SR_KSU_KERNEL 0x00000000
300 #define MIPS_SR_ERL 0x00000004
301 #define MIPS_SR_EXL 0x00000002
304 * The interrupt masks.
305 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
307 #define MIPS_INT_MASK 0xff00
308 #define MIPS_INT_MASK_5 0x8000
309 #define MIPS_INT_MASK_4 0x4000
310 #define MIPS_INT_MASK_3 0x2000
311 #define MIPS_INT_MASK_2 0x1000
312 #define MIPS_INT_MASK_1 0x0800
313 #define MIPS_INT_MASK_0 0x0400
314 #define MIPS_HARD_INT_MASK 0xfc00
315 #define MIPS_SOFT_INT_MASK_1 0x0200
316 #define MIPS_SOFT_INT_MASK_0 0x0100
319 * The bits in the MIPS3 config register.
321 * bit 0..5: R/W, Bit 6..31: R/O
324 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
325 #define MIPS_CONFIG_K0_MASK 0x00000007
328 * R/W Update on Store Conditional
329 * 0: Store Conditional uses coherency algorithm specified by TLB
330 * 1: Store Conditional uses cacheable coherent update on write
332 #define MIPS_CONFIG_CU 0x00000008
334 #define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */
335 #define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */
336 #define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
337 (((config) & (bit)) ? 32 : 16)
339 #define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
340 #define MIPS_CONFIG_DC_SHIFT 6
341 #define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
342 #define MIPS_CONFIG_IC_SHIFT 9
343 #define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
345 /* Cache size mode indication: available only on Vr41xx CPUs */
346 #define MIPS_CONFIG_CS 0x00001000
347 #define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
348 #define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
349 ((base) << (((config) & (mask)) >> (shift)))
351 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
352 #define MIPS_CONFIG_SE 0x00001000
354 /* Block ordering: 0: sequential, 1: sub-block */
355 #define MIPS_CONFIG_EB 0x00002000
357 /* ECC mode - 0: ECC mode, 1: parity mode */
358 #define MIPS_CONFIG_EM 0x00004000
360 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
361 #define MIPS_CONFIG_BE 0x00008000
363 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
364 #define MIPS_CONFIG_SM 0x00010000
366 /* Secondary Cache - 0: present, 1: not present */
367 #define MIPS_CONFIG_SC 0x00020000
369 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
370 #define MIPS_CONFIG_EW_MASK 0x000c0000
371 #define MIPS_CONFIG_EW_SHIFT 18
373 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
374 #define MIPS_CONFIG_SW 0x00100000
376 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
377 #define MIPS_CONFIG_SS 0x00200000
379 /* Secondary Cache line size */
380 #define MIPS_CONFIG_SB_MASK 0x00c00000
381 #define MIPS_CONFIG_SB_SHIFT 22
382 #define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
383 (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
385 /* Write back data rate */
386 #define MIPS_CONFIG_EP_MASK 0x0f000000
387 #define MIPS_CONFIG_EP_SHIFT 24
389 /* System clock ratio - this value is CPU dependent */
390 #define MIPS_CONFIG_EC_MASK 0x70000000
391 #define MIPS_CONFIG_EC_SHIFT 28
393 /* Master-Checker Mode - 1: enabled */
394 #define MIPS_CONFIG_CM 0x80000000
397 * The bits in the MIPS4 config register.
401 * Location of exception vectors.
403 * Common vectors: reset and UTLB miss.
405 #define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000)
406 #define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000)
409 * MIPS-III exception vectors
411 #define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080)
412 #define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100)
413 #define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180)
416 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
418 #define MIPS_INTR_EXC_VEC 0x80000200
421 * Coprocessor 0 registers:
423 * v--- width for mips I,III,32,64
424 * (3=32bit, 6=64bit, i=impl dep)
425 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
426 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
427 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
428 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
429 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
430 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
431 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
432 * 7 MIPS_COP_0_INFO ..33 Info registers
433 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
434 * 9 MIPS_COP_0_COUNT .333 Count register.
435 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
436 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
437 * 12 MIPS_COP_0_STATUS 3333 Status register.
438 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
439 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
440 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
441 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
442 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
443 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
444 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
445 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4.
446 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
447 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
448 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
449 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
450 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
451 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
452 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
453 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
454 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
455 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
456 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
457 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
458 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
459 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
460 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
461 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
462 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
463 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
464 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
467 /* Deal with inclusion from an assembly file. */
468 #if defined(_LOCORE) || defined(LOCORE)
475 #define MIPS_COP_0_TLB_INDEX _(0)
476 #define MIPS_COP_0_TLB_RANDOM _(1)
477 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
479 #define MIPS_COP_0_TLB_CONTEXT _(4)
480 /* $5 and $6 new with MIPS-III */
481 #define MIPS_COP_0_BAD_VADDR _(8)
482 #define MIPS_COP_0_TLB_HI _(10)
483 #define MIPS_COP_0_STATUS _(12)
484 #define MIPS_COP_0_CAUSE _(13)
485 #define MIPS_COP_0_EXC_PC _(14)
486 #define MIPS_COP_0_PRID _(15)
489 #define MIPS_COP_0_TLB_LO0 _(2)
490 #define MIPS_COP_0_TLB_LO1 _(3)
492 #define MIPS_COP_0_TLB_PG_MASK _(5)
493 #define MIPS_COP_0_TLB_WIRED _(6)
495 #define MIPS_COP_0_COUNT _(9)
496 #define MIPS_COP_0_COMPARE _(11)
498 #define MIPS_COP_0_CONFIG _(16)
499 #define MIPS_COP_0_LLADDR _(17)
500 #define MIPS_COP_0_WATCH_LO _(18)
501 #define MIPS_COP_0_WATCH_HI _(19)
502 #define MIPS_COP_0_TLB_XCONTEXT _(20)
503 #define MIPS_COP_0_ECC _(26)
504 #define MIPS_COP_0_CACHE_ERR _(27)
505 #define MIPS_COP_0_TAG_LO _(28)
506 #define MIPS_COP_0_TAG_HI _(29)
507 #define MIPS_COP_0_ERROR_PC _(30)
510 #define MIPS_COP_0_INFO _(7)
511 #define MIPS_COP_0_DEBUG _(23)
512 #define MIPS_COP_0_DEPC _(24)
513 #define MIPS_COP_0_PERFCNT _(25)
514 #define MIPS_COP_0_DATA_LO _(28)
515 #define MIPS_COP_0_DATA_HI _(29)
516 #define MIPS_COP_0_DESAVE _(31)
518 /* MIPS32 Config register definitions */
519 #define MIPS_MMU_NONE 0x00 /* No MMU present */
520 #define MIPS_MMU_TLB 0x01 /* Standard TLB */
521 #define MIPS_MMU_BAT 0x02 /* Standard BAT */
522 #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
524 #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
525 #define MIPS_CONFIG0_MT_SHIFT 7
526 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
527 #define MIPS_CONFIG0_VI 0x00000004 /* instruction cache is virtual */
529 #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
530 #define MIPS_CONFIG1_TLBSZ_SHIFT 25
532 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */
533 #define MIPS_CONFIG1_IS_SHIFT 22
534 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */
535 #define MIPS_CONFIG1_IL_SHIFT 19
536 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */
537 #define MIPS_CONFIG1_IA_SHIFT 16
538 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */
539 #define MIPS_CONFIG1_DS_SHIFT 13
540 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */
541 #define MIPS_CONFIG1_DL_SHIFT 10
542 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */
543 #define MIPS_CONFIG1_DA_SHIFT 7
544 #define MIPS_CONFIG1_LOWBITS 0x0000007F
545 #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */
546 #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */
547 #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */
548 #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */
549 #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */
550 #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */
551 #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */
553 #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */
554 #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */
555 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */
558 * Values for the code field in a break instruction.
560 #define MIPS_BREAK_INSTR 0x0000000d
561 #define MIPS_BREAK_VAL_MASK 0x03ff0000
562 #define MIPS_BREAK_VAL_SHIFT 16
563 #define MIPS_BREAK_KDB_VAL 512
564 #define MIPS_BREAK_SSTEP_VAL 513
565 #define MIPS_BREAK_BRKPT_VAL 514
566 #define MIPS_BREAK_SOVER_VAL 515
567 #define MIPS_BREAK_DDB_VAL 516
568 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
569 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
570 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
571 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
572 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
573 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
574 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
575 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
576 #define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \
577 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT))
580 * Mininum and maximum cache sizes.
582 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
583 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
584 #define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
587 * The floating point version and status registers.
589 #define MIPS_FPU_ID $0
590 #define MIPS_FPU_CSR $31
593 * The floating point coprocessor status register bits.
595 #define MIPS_FPU_ROUNDING_BITS 0x00000003
596 #define MIPS_FPU_ROUND_RN 0x00000000
597 #define MIPS_FPU_ROUND_RZ 0x00000001
598 #define MIPS_FPU_ROUND_RP 0x00000002
599 #define MIPS_FPU_ROUND_RM 0x00000003
600 #define MIPS_FPU_STICKY_BITS 0x0000007c
601 #define MIPS_FPU_STICKY_INEXACT 0x00000004
602 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
603 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
604 #define MIPS_FPU_STICKY_DIV0 0x00000020
605 #define MIPS_FPU_STICKY_INVALID 0x00000040
606 #define MIPS_FPU_ENABLE_BITS 0x00000f80
607 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
608 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
609 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
610 #define MIPS_FPU_ENABLE_DIV0 0x00000400
611 #define MIPS_FPU_ENABLE_INVALID 0x00000800
612 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
613 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
614 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
615 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
616 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
617 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
618 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
619 #define MIPS_FPU_COND_BIT 0x00800000
620 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
621 #define MIPS_FPC_MBZ_BITS 0xfe7c0000
625 * Constants to determine if have a floating point instruction.
627 #define MIPS_OPCODE_SHIFT 26
628 #define MIPS_OPCODE_C1 0x11
630 #endif /* _MIPS_CPUREGS_H_ */