2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_PTE_H_
30 #define _MACHINE_PTE_H_
33 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
34 typedef uint64_t pt_entry_t;
36 typedef uint32_t pt_entry_t;
38 typedef pt_entry_t *pd_entry_t;
42 * TLB and PTE management. Most things operate within the context of
43 * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi
44 * start with TLBHI_. PTE bits begin with PTE_.
46 * Note that we use the same size VM and TLB pages.
48 #define TLB_PAGE_SHIFT (PAGE_SHIFT)
49 #define TLB_PAGE_SIZE (1 << TLB_PAGE_SHIFT)
50 #define TLB_PAGE_MASK (TLB_PAGE_SIZE - 1)
53 * TLB PageMask register. Has mask bits set above the default, 4K, page mask.
55 #define TLBMASK_SHIFT (13)
56 #define TLBMASK_MASK ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
59 * PFN for EntryLo register. Upper bits are 0, which is to say that
60 * bit 28 is the last hardware bit; Bits 29 and upwards (EntryLo is
61 * 64 bit though it can be referred to in 32-bits providing 3 software
62 * bits safely. We use it as 64 bits to get many software bits, and
63 * god knows what else.) are unacknowledged by hardware. They may be
64 * written as anything, but otherwise they have as much meaning as
67 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
68 #define TLBLO_SWBITS_SHIFT (34)
69 #define TLBLO_PFN_MASK 0x3FFFFFFC0ULL
71 #define TLBLO_SWBITS_SHIFT (29)
72 #define TLBLO_PFN_MASK (0x1FFFFFC0)
74 #define TLBLO_PFN_SHIFT (6)
75 #define TLBLO_SWBITS_MASK ((pt_entry_t)0x7 << TLBLO_SWBITS_SHIFT)
76 #define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
77 #define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
78 #define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK)
79 #define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
82 * XXX This comment is not correct for anything more modern than R4K.
84 * VPN for EntryHi register. Upper two bits select user, supervisor,
85 * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to
86 * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12
87 * to bit 8 there is a 5-bit 0 field. Low byte is ASID.
89 * XXX This comment is not correct for FreeBSD.
90 * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
92 #define TLBHI_ASID_MASK (0xff)
93 #if defined(__mips_n64)
94 #define TLBHI_R_SHIFT 62
95 #define TLBHI_R_USER (0x00UL << TLBHI_R_SHIFT)
96 #define TLBHI_R_SUPERVISOR (0x01UL << TLBHI_R_SHIFT)
97 #define TLBHI_R_KERNEL (0x03UL << TLBHI_R_SHIFT)
98 #define TLBHI_R_MASK (0x03UL << TLBHI_R_SHIFT)
99 #define TLBHI_VA_R(va) ((va) & TLBHI_R_MASK)
100 #define TLBHI_FILL_SHIFT 40
101 #define TLBHI_VPN2_SHIFT (TLB_PAGE_SHIFT + 1)
102 #define TLBHI_VPN2_MASK (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT))
103 #define TLBHI_VA_TO_VPN2(va) ((va) & TLBHI_VPN2_MASK)
104 #define TLBHI_ENTRY(va, asid) ((TLBHI_VA_R((va))) /* Region. */ | \
105 (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
106 ((asid) & TLBHI_ASID_MASK))
107 #else /* !defined(__mips_n64) */
108 #define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1)
109 #define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
110 #endif /* defined(__mips_n64) */
113 * TLB flags managed in hardware:
114 * C: Cache attribute.
115 * D: Dirty bit. This means a page is writable. It is not
116 * set at first, and a write is trapped, and the dirty
117 * bit is set. See also PTE_RO.
118 * V: Valid bit. Obvious, isn't it?
119 * G: Global bit. This means that this mapping is present
120 * in EVERY address space, and to ignore the ASID when
123 #define PTE_C(attr) ((attr & 0x07) << 3)
124 #define PTE_C_UNCACHED (PTE_C(MIPS_CCA_UNCACHED))
125 #define PTE_C_CACHE (PTE_C(MIPS_CCA_CACHED))
131 * VM flags managed in software:
132 * RO: Read only. Never set PTE_D on this page, and don't
133 * listen to requests to write to it.
135 * MANAGED:Managed. This PTE maps a managed page.
137 #define PTE_RO ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT)
138 #define PTE_W ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT)
139 #define PTE_MANAGED ((pt_entry_t)0x04 << TLBLO_SWBITS_SHIFT)
142 * PTE management functions for bits defined above.
144 #define pte_clear(pte, bit) (*(pte) &= ~(bit))
145 #define pte_set(pte, bit) (*(pte) |= (bit))
146 #define pte_test(pte, bit) ((*(pte) & (bit)) == (bit))
148 /* Assembly support for PTE access*/
150 #if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
152 #define PTE2MASK 0xff0 /* for the 2-page lo0/lo1 */
153 #define PTEMASK 0xff8
156 #define PTE_MTC0 dmtc0
157 #define CLEAR_PTE_SWBITS(pr)
160 #define PTE2MASK 0xff8 /* for the 2-page lo0/lo1 */
161 #define PTEMASK 0xffc
164 #define PTE_MTC0 mtc0
165 #define CLEAR_PTE_SWBITS(r) sll r, 3; srl r, 3 /* remove 3 high bits */
166 #endif /* defined(__mips_n64) || defined(__mips_n32) */
168 #if defined(__mips_n64)
170 #define PDEPTRMASK 0xff8
173 #define PDEPTRMASK 0xffc
177 #endif /* !_MACHINE_PTE_H_ */