1 /* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */
4 * Copyright 2001, 2002 Wasabi Systems, Inc.
7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
39 * Copyright 2000, 2001
40 * Broadcom Corporation. All rights reserved.
42 * This software is furnished under license and may be used and copied only
43 * in accordance with the following terms and conditions. Subject to these
44 * conditions, you may download, copy, install, use, modify and distribute
45 * modified or unmodified copies of this software in source and/or binary
46 * form. No title or ownership is transferred hereby.
48 * 1) Any source code used, modified or distributed must reproduce and
49 * retain this copyright notice and list of conditions as they appear in
52 * 2) No right is granted to use any trade name, trademark, or logo of
53 * Broadcom Corporation. The "Broadcom Corporation" name may not be
54 * used to endorse or promote products derived from this software
55 * without the prior written permission of Broadcom Corporation.
57 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
58 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
59 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
60 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
61 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
62 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
65 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
66 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
67 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70 #include <sys/cdefs.h>
71 __FBSDID("$FreeBSD$");
73 #include <sys/types.h>
74 #include <sys/systm.h>
76 #include <machine/cpuinfo.h>
77 #include <machine/cache.h>
79 struct mips_cache_ops mips_cache_ops;
81 #if defined(MIPS_DISABLE_L1_CACHE) || defined(CPU_RMI) || defined(CPU_NLM)
83 cache_noop(vm_offset_t va, vm_size_t size)
89 mips_config_cache(struct mips_cpuinfo * cpuinfo)
92 switch (cpuinfo->l1.ic_linesize) {
94 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16;
95 mips_cache_ops.mco_icache_sync_range =
96 mipsNN_icache_sync_range_16;
97 mips_cache_ops.mco_icache_sync_range_index =
98 mipsNN_icache_sync_range_index_16;
101 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32;
102 mips_cache_ops.mco_icache_sync_range =
103 mipsNN_icache_sync_range_32;
104 mips_cache_ops.mco_icache_sync_range_index =
105 mipsNN_icache_sync_range_index_32;
109 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128;
110 mips_cache_ops.mco_icache_sync_range =
111 mipsNN_icache_sync_range_128;
112 mips_cache_ops.mco_icache_sync_range_index =
113 mipsNN_icache_sync_range_index_128;
117 #ifdef MIPS_DISABLE_L1_CACHE
119 mips_cache_ops.mco_icache_sync_all = cache_noop;
120 mips_cache_ops.mco_icache_sync_range =
121 (void (*)(vaddr_t, vsize_t))cache_noop;
122 mips_cache_ops.mco_icache_sync_range_index =
123 (void (*)(vaddr_t, vsize_t))cache_noop;
127 panic("no Icache ops for %d byte lines",
128 cpuinfo->l1.ic_linesize);
131 switch (cpuinfo->l1.dc_linesize) {
133 mips_cache_ops.mco_pdcache_wbinv_all =
134 mips_cache_ops.mco_intern_pdcache_wbinv_all =
135 mipsNN_pdcache_wbinv_all_16;
136 mips_cache_ops.mco_pdcache_wbinv_range =
137 mipsNN_pdcache_wbinv_range_16;
138 mips_cache_ops.mco_pdcache_wbinv_range_index =
139 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
140 mipsNN_pdcache_wbinv_range_index_16;
141 mips_cache_ops.mco_pdcache_inv_range =
142 mipsNN_pdcache_inv_range_16;
143 mips_cache_ops.mco_pdcache_wb_range =
144 mips_cache_ops.mco_intern_pdcache_wb_range =
145 mipsNN_pdcache_wb_range_16;
148 mips_cache_ops.mco_pdcache_wbinv_all =
149 mips_cache_ops.mco_intern_pdcache_wbinv_all =
150 mipsNN_pdcache_wbinv_all_32;
151 #if defined(CPU_RMI) || defined(CPU_NLM)
152 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop;
154 mips_cache_ops.mco_pdcache_wbinv_range =
155 mipsNN_pdcache_wbinv_range_32;
157 #if defined(CPU_RMI) || defined(CPU_NLM)
158 mips_cache_ops.mco_pdcache_wbinv_range_index =
159 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop;
160 mips_cache_ops.mco_pdcache_inv_range = cache_noop;
162 mips_cache_ops.mco_pdcache_wbinv_range_index =
163 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
164 mipsNN_pdcache_wbinv_range_index_32;
165 mips_cache_ops.mco_pdcache_inv_range =
166 mipsNN_pdcache_inv_range_32;
168 #if defined(CPU_RMI) || defined(CPU_NLM)
169 mips_cache_ops.mco_pdcache_wb_range =
170 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop;
172 mips_cache_ops.mco_pdcache_wb_range =
173 mips_cache_ops.mco_intern_pdcache_wb_range =
174 mipsNN_pdcache_wb_range_32;
179 mips_cache_ops.mco_pdcache_wbinv_all =
180 mips_cache_ops.mco_intern_pdcache_wbinv_all =
181 mipsNN_pdcache_wbinv_all_128;
182 mips_cache_ops.mco_pdcache_wbinv_range =
183 mipsNN_pdcache_wbinv_range_128;
184 mips_cache_ops.mco_pdcache_wbinv_range_index =
185 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
186 mipsNN_pdcache_wbinv_range_index_128;
187 mips_cache_ops.mco_pdcache_inv_range =
188 mipsNN_pdcache_inv_range_128;
189 mips_cache_ops.mco_pdcache_wb_range =
190 mips_cache_ops.mco_intern_pdcache_wb_range =
191 mipsNN_pdcache_wb_range_128;
194 #ifdef MIPS_DISABLE_L1_CACHE
196 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
197 mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop;
198 mips_cache_ops.mco_pdcache_wbinv_range =
199 (void (*)(vaddr_t, vsize_t))cache_noop;
200 mips_cache_ops.mco_pdcache_wbinv_range_index =
201 (void (*)(vaddr_t, vsize_t))cache_noop;
202 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
203 (void (*)(vaddr_t, vsize_t))cache_noop;
204 mips_cache_ops.mco_pdcache_inv_range =
205 (void (*)(vaddr_t, vsize_t))cache_noop;
206 mips_cache_ops.mco_pdcache_wb_range =
207 (void (*)(vaddr_t, vsize_t))cache_noop;
208 mips_cache_ops.mco_intern_pdcache_wb_range =
209 (void (*)(vaddr_t, vsize_t))cache_noop;
213 panic("no Dcache ops for %d byte lines",
214 cpuinfo->l1.dc_linesize);
217 mipsNN_cache_init(cpuinfo);
221 (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) {
223 printf(" Dcache is coherent\n");
225 mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
226 mips_cache_ops.mco_pdcache_wbinv_range =
227 (void (*)(vaddr_t, vsize_t))cache_noop;
228 mips_cache_ops.mco_pdcache_wbinv_range_index =
229 (void (*)(vaddr_t, vsize_t))cache_noop;
230 mips_cache_ops.mco_pdcache_inv_range =
231 (void (*)(vaddr_t, vsize_t))cache_noop;
232 mips_cache_ops.mco_pdcache_wb_range =
233 (void (*)(vaddr_t, vsize_t))cache_noop;
235 if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
237 printf(" Icache is coherent against Dcache\n");
239 mips_cache_ops.mco_intern_pdcache_wbinv_all =
241 mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
242 (void (*)(vaddr_t, vsize_t))cache_noop;
243 mips_cache_ops.mco_intern_pdcache_wb_range =
244 (void (*)(vaddr_t, vsize_t))cache_noop;
248 /* Check that all cache ops are set up. */
249 /* must have primary Icache */
250 if (cpuinfo->l1.ic_size) {
252 if (!mips_cache_ops.mco_icache_sync_all)
253 panic("no icache_sync_all cache op");
254 if (!mips_cache_ops.mco_icache_sync_range)
255 panic("no icache_sync_range cache op");
256 if (!mips_cache_ops.mco_icache_sync_range_index)
257 panic("no icache_sync_range_index cache op");
259 /* must have primary Dcache */
260 if (cpuinfo->l1.dc_size) {
261 if (!mips_cache_ops.mco_pdcache_wbinv_all)
262 panic("no pdcache_wbinv_all");
263 if (!mips_cache_ops.mco_pdcache_wbinv_range)
264 panic("no pdcache_wbinv_range");
265 if (!mips_cache_ops.mco_pdcache_wbinv_range_index)
266 panic("no pdcache_wbinv_range_index");
267 if (!mips_cache_ops.mco_pdcache_inv_range)
268 panic("no pdcache_inv_range");
269 if (!mips_cache_ops.mco_pdcache_wb_range)
270 panic("no pdcache_wb_range");
273 /* XXXMIPS: No secondary cache handlers yet */
275 if (mips_sdcache_size) {
276 if (!mips_cache_ops.mco_sdcache_wbinv_all)
277 panic("no sdcache_wbinv_all");
278 if (!mips_cache_ops.mco_sdcache_wbinv_range)
279 panic("no sdcache_wbinv_range");
280 if (!mips_cache_ops.mco_sdcache_wbinv_range_index)
281 panic("no sdcache_wbinv_range_index");
282 if (!mips_cache_ops.mco_sdcache_inv_range)
283 panic("no sdcache_inv_range");
284 if (!mips_cache_ops.mco_sdcache_wb_range)
285 panic("no sdcache_wb_range");