1 /* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
6 * This code is derived from software contributed to Berkeley by
7 * Digital Equipment Corporation and Ralph Campbell.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (C) 1989 Digital Equipment Corporation.
34 * Permission to use, copy, modify, and distribute this software and
35 * its documentation for any purpose and without fee is hereby granted,
36 * provided that the above copyright notice appears in all copies.
37 * Digital Equipment Corporation makes no representations about the
38 * suitability of this software for any purpose. It is provided "as is"
39 * without express or implied warranty.
41 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
42 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
43 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
44 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
45 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
46 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
47 * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
48 * JNPR: exception.S,v 1.5 2007/01/08 04:58:37 katta
53 * Contains code that is the first executed at boot time plus
54 * assembly language support routines.
58 #include "opt_kdtrace.h"
59 #include <machine/asm.h>
60 #include <machine/cpu.h>
61 #include <machine/regnum.h>
62 #include <machine/cpuregs.h>
63 #include <machine/pte.h>
67 .set noreorder # Noreorder is default style!
71 .globl dtrace_invop_jump_addr
73 .type dtrace_invop_jump_addr, @object
74 .size dtrace_invop_jump_addr, 8
75 dtrace_invop_jump_addr:
78 .globl dtrace_invop_calltrap_addr
80 .type dtrace_invop_calltrap_addr, @object
81 .size dtrace_invop_calltrap_addr, 8
82 dtrace_invop_calltrap_addr:
92 #define INTRCNT_COUNT 256
96 *----------------------------------------------------------------------------
100 * Vector code for the TLB-miss exception vector 0x80000000.
102 * This code is copied to the TLB exception vector address to
103 * which the CPU jumps in response to an exception or a TLB miss.
104 * NOTE: This code must be position independent!!!
108 VECTOR(MipsTLBMiss, unknown)
112 MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
114 VECTOR_END(MipsTLBMiss)
117 *----------------------------------------------------------------------------
121 * This is the real TLB Miss Handler code.
122 * 'segbase' points to the base of the segment table for user processes.
124 * Don't check for invalid pte's here. We load them as well and
125 * let the processor trap to load the correct value after service.
126 *----------------------------------------------------------------------------
131 bltz k0, 1f #02: k0<0 -> 1f (kernel fault)
132 PTR_SRL k0, k0, SEGSHIFT - PTRSHIFT #03: k0=seg offset (almost)
135 PTR_L k1, PC_SEGBASE(k1)
136 beqz k1, 2f #05: make sure segbase is not null
137 andi k0, k0, PDEPTRMASK #06: k0=seg offset
138 PTR_ADDU k1, k0, k1 #07: k1=seg entry address
140 PTR_L k1, 0(k1) #08: k1=seg entry
141 MFC0 k0, MIPS_COP_0_BAD_VADDR #09: k0=bad address (again)
142 beq k1, zero, 2f #0a: ==0 -- no page table
144 PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=VPN
145 andi k0, k0, PDEPTRMASK # k0=pde offset
146 PTR_ADDU k1, k0, k1 # k1=pde entry address
147 PTR_L k1, 0(k1) # k1=pde entry
148 MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
149 beq k1, zero, 2f # ==0 -- no page table
151 PTR_SRL k0, PAGE_SHIFT - PTESHIFT #0b: k0=VPN (aka va>>10)
152 andi k0, k0, PTE2MASK #0c: k0=page tab offset
153 PTR_ADDU k1, k1, k0 #0d: k1=pte address
154 PTE_L k0, 0(k1) #0e: k0=lo0 pte
155 PTE_L k1, PTESIZE(k1) #0f: k1=lo0 pte
157 PTE_MTC0 k0, MIPS_COP_0_TLB_LO0 #12: lo0 is loaded
160 PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded
162 tlbwr #1a: write to tlb
164 eret #1f: retUrn from exception
165 1: j MipsTLBMissException #20: kernel exception
166 nop #21: branch delay slot
167 2: j SlowFault #22: no page table present
168 nop #23: branch delay slot
172 * This code is copied to the general exception vector address to
173 * handle all execptions except RESET and TLBMiss.
174 * NOTE: This code must be position independent!!!
176 VECTOR(MipsException, unknown)
178 * Find out what mode we came from and jump to the proper handler.
181 mfc0 k0, MIPS_COP_0_STATUS # Get the status register
182 mfc0 k1, MIPS_COP_0_CAUSE # Get the cause register value.
183 and k0, k0, MIPS_SR_KSU_USER # test for user mode
184 # sneaky but the bits are
186 sll k0, k0, 3 # shift user bit for cause index
187 and k1, k1, MIPS_CR_EXC_CODE # Mask out the cause bits.
188 or k1, k1, k0 # change index to user table
189 #if defined(__mips_n64)
190 PTR_SLL k1, k1, 1 # shift to get 8-byte offset
193 PTR_LA k0, _C_LABEL(machExceptionTable) # get base of the jump table
194 PTR_ADDU k0, k0, k1 # Get the address of the
195 # function entry. Note that
196 # the cause is already
197 # shifted left by 2 bits so
198 # we dont have to shift.
199 PTR_L k0, 0(k0) # Get the function address
201 j k0 # Jump to the function.
204 VECTOR_END(MipsException)
207 * We couldn't find a TLB entry.
208 * Find out what mode we came from and call the appropriate handler.
212 mfc0 k0, MIPS_COP_0_STATUS
214 and k0, k0, MIPS_SR_KSU_USER
215 bne k0, zero, _C_LABEL(MipsUserGenException)
222 /*----------------------------------------------------------------------------
224 * MipsKernGenException --
226 * Handle an exception from kernel mode.
234 *----------------------------------------------------------------------------
237 #define SAVE_REG(reg, offs, base) \
238 REG_S reg, CALLFRAME_SIZ + (SZREG * offs) (base)
240 #if defined(CPU_CNMIPS)
241 #define CLEAR_STATUS \
242 mfc0 a0, MIPS_COP_0_STATUS ;\
243 li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
245 li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER) ; \
247 mtc0 a0, MIPS_COP_0_STATUS ; \
249 #elif defined(CPU_RMI) || defined(CPU_NLM)
250 #define CLEAR_STATUS \
251 mfc0 a0, MIPS_COP_0_STATUS ;\
252 li a2, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT) ; \
254 li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER) ; \
256 mtc0 a0, MIPS_COP_0_STATUS ; \
259 #define CLEAR_STATUS \
260 mfc0 a0, MIPS_COP_0_STATUS ;\
261 li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | MIPS_SR_KSU_USER) ; \
263 mtc0 a0, MIPS_COP_0_STATUS ; \
268 * Save CPU and CP0 register state.
270 * This is straightforward except for saving the exception program
271 * counter. The ddb backtrace code looks for the first instruction
272 * matching the form "sw ra, (off)sp" to figure out the address of the
273 * calling function. So we must make sure that we save the exception
274 * PC by staging it through 'ra' as opposed to any other register.
277 SAVE_REG(AT, AST, sp) ;\
279 SAVE_REG(v0, V0, sp) ;\
280 SAVE_REG(v1, V1, sp) ;\
281 SAVE_REG(a0, A0, sp) ;\
282 SAVE_REG(a1, A1, sp) ;\
283 SAVE_REG(a2, A2, sp) ;\
284 SAVE_REG(a3, A3, sp) ;\
285 SAVE_REG(t0, T0, sp) ;\
286 SAVE_REG(t1, T1, sp) ;\
287 SAVE_REG(t2, T2, sp) ;\
288 SAVE_REG(t3, T3, sp) ;\
289 SAVE_REG(ta0, TA0, sp) ;\
290 SAVE_REG(ta1, TA1, sp) ;\
291 SAVE_REG(ta2, TA2, sp) ;\
292 SAVE_REG(ta3, TA3, sp) ;\
293 SAVE_REG(t8, T8, sp) ;\
294 SAVE_REG(t9, T9, sp) ;\
295 SAVE_REG(gp, GP, sp) ;\
296 SAVE_REG(s0, S0, sp) ;\
297 SAVE_REG(s1, S1, sp) ;\
298 SAVE_REG(s2, S2, sp) ;\
299 SAVE_REG(s3, S3, sp) ;\
300 SAVE_REG(s4, S4, sp) ;\
301 SAVE_REG(s5, S5, sp) ;\
302 SAVE_REG(s6, S6, sp) ;\
303 SAVE_REG(s7, S7, sp) ;\
304 SAVE_REG(s8, S8, sp) ;\
307 mfc0 a0, MIPS_COP_0_STATUS ;\
308 mfc0 a1, MIPS_COP_0_CAUSE ;\
309 MFC0 a2, MIPS_COP_0_BAD_VADDR;\
310 MFC0 a3, MIPS_COP_0_EXC_PC ;\
311 SAVE_REG(v0, MULLO, sp) ;\
312 SAVE_REG(v1, MULHI, sp) ;\
313 SAVE_REG(a0, SR, sp) ;\
314 SAVE_REG(a1, CAUSE, sp) ;\
315 SAVE_REG(a2, BADVADDR, sp) ;\
318 SAVE_REG(ra, PC, sp) ;\
320 SAVE_REG(ra, RA, sp) ;\
321 PTR_ADDU v0, sp, KERN_EXC_FRAME_SIZE ;\
322 SAVE_REG(v0, SP, sp) ;\
324 PTR_ADDU a0, sp, CALLFRAME_SIZ ;\
327 #define RESTORE_REG(reg, offs, base) \
328 REG_L reg, CALLFRAME_SIZ + (SZREG * offs) (base)
330 #define RESTORE_CPU \
332 RESTORE_REG(k0, SR, sp) ;\
333 RESTORE_REG(t0, MULLO, sp) ;\
334 RESTORE_REG(t1, MULHI, sp) ;\
337 MTC0 v0, MIPS_COP_0_EXC_PC ;\
339 RESTORE_REG(AT, AST, sp) ;\
340 RESTORE_REG(v0, V0, sp) ;\
341 RESTORE_REG(v1, V1, sp) ;\
342 RESTORE_REG(a0, A0, sp) ;\
343 RESTORE_REG(a1, A1, sp) ;\
344 RESTORE_REG(a2, A2, sp) ;\
345 RESTORE_REG(a3, A3, sp) ;\
346 RESTORE_REG(t0, T0, sp) ;\
347 RESTORE_REG(t1, T1, sp) ;\
348 RESTORE_REG(t2, T2, sp) ;\
349 RESTORE_REG(t3, T3, sp) ;\
350 RESTORE_REG(ta0, TA0, sp) ;\
351 RESTORE_REG(ta1, TA1, sp) ;\
352 RESTORE_REG(ta2, TA2, sp) ;\
353 RESTORE_REG(ta3, TA3, sp) ;\
354 RESTORE_REG(t8, T8, sp) ;\
355 RESTORE_REG(t9, T9, sp) ;\
356 RESTORE_REG(s0, S0, sp) ;\
357 RESTORE_REG(s1, S1, sp) ;\
358 RESTORE_REG(s2, S2, sp) ;\
359 RESTORE_REG(s3, S3, sp) ;\
360 RESTORE_REG(s4, S4, sp) ;\
361 RESTORE_REG(s5, S5, sp) ;\
362 RESTORE_REG(s6, S6, sp) ;\
363 RESTORE_REG(s7, S7, sp) ;\
364 RESTORE_REG(s8, S8, sp) ;\
365 RESTORE_REG(gp, GP, sp) ;\
366 RESTORE_REG(ra, RA, sp) ;\
367 PTR_ADDU sp, sp, KERN_EXC_FRAME_SIZE;\
368 mtc0 k0, MIPS_COP_0_STATUS
372 * The kernel exception stack contains 18 saved general registers,
373 * the status register and the multiply lo and high registers.
374 * In addition, we set this up for linkage conventions.
376 #define KERN_REG_SIZE (NUMSAVEREGS * SZREG)
377 #define KERN_EXC_FRAME_SIZE (CALLFRAME_SIZ + KERN_REG_SIZE + 16)
379 NNON_LEAF(MipsKernGenException, KERN_EXC_FRAME_SIZE, ra)
381 PTR_SUBU sp, sp, KERN_EXC_FRAME_SIZE
382 .mask 0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE)
384 * Save CPU state, building 'frame'.
388 * Call the exception handler. a0 points at the saved frame.
390 PTR_LA gp, _C_LABEL(_gp)
391 PTR_LA k0, _C_LABEL(trap)
393 REG_S a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging
396 * Update interrupt and CPU mask in saved status register
397 * Some of interrupts could be disabled by
398 * intr filters if interrupts are enabled later
401 mfc0 a0, MIPS_COP_0_STATUS
402 and a0, a0, (MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
403 RESTORE_REG(a1, SR, sp)
404 and a1, a1, ~(MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
407 RESTORE_CPU # v0 contains the return address.
411 END(MipsKernGenException)
414 #define SAVE_U_PCB_REG(reg, offs, base) \
415 REG_S reg, U_PCB_REGS + (SZREG * offs) (base)
417 #define RESTORE_U_PCB_REG(reg, offs, base) \
418 REG_L reg, U_PCB_REGS + (SZREG * offs) (base)
420 /*----------------------------------------------------------------------------
422 * MipsUserGenException --
424 * Handle an exception from user mode.
432 *----------------------------------------------------------------------------
434 NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
436 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
438 * Save all of the registers except for the kernel temporaries in u.u_pcb.
441 PTR_L k1, PC_CURPCB(k1)
442 SAVE_U_PCB_REG(AT, AST, k1)
444 SAVE_U_PCB_REG(v0, V0, k1)
445 SAVE_U_PCB_REG(v1, V1, k1)
446 SAVE_U_PCB_REG(a0, A0, k1)
448 SAVE_U_PCB_REG(a1, A1, k1)
449 SAVE_U_PCB_REG(a2, A2, k1)
450 SAVE_U_PCB_REG(a3, A3, k1)
451 SAVE_U_PCB_REG(t0, T0, k1)
453 SAVE_U_PCB_REG(t1, T1, k1)
454 SAVE_U_PCB_REG(t2, T2, k1)
455 SAVE_U_PCB_REG(t3, T3, k1)
456 SAVE_U_PCB_REG(ta0, TA0, k1)
457 mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg.
458 SAVE_U_PCB_REG(ta1, TA1, k1)
459 SAVE_U_PCB_REG(ta2, TA2, k1)
460 SAVE_U_PCB_REG(ta3, TA3, k1)
461 SAVE_U_PCB_REG(s0, S0, k1)
462 mfc0 a1, MIPS_COP_0_CAUSE # Second arg is the cause reg.
463 SAVE_U_PCB_REG(s1, S1, k1)
464 SAVE_U_PCB_REG(s2, S2, k1)
465 SAVE_U_PCB_REG(s3, S3, k1)
466 SAVE_U_PCB_REG(s4, S4, k1)
467 MFC0 a2, MIPS_COP_0_BAD_VADDR # Third arg is the fault addr
468 SAVE_U_PCB_REG(s5, S5, k1)
469 SAVE_U_PCB_REG(s6, S6, k1)
470 SAVE_U_PCB_REG(s7, S7, k1)
471 SAVE_U_PCB_REG(t8, T8, k1)
472 MFC0 a3, MIPS_COP_0_EXC_PC # Fourth arg is the pc.
473 SAVE_U_PCB_REG(t9, T9, k1)
474 SAVE_U_PCB_REG(gp, GP, k1)
475 SAVE_U_PCB_REG(sp, SP, k1)
476 SAVE_U_PCB_REG(s8, S8, k1)
477 PTR_SUBU sp, k1, CALLFRAME_SIZ # switch to kernel SP
478 SAVE_U_PCB_REG(ra, RA, k1)
479 SAVE_U_PCB_REG(v0, MULLO, k1)
480 SAVE_U_PCB_REG(v1, MULHI, k1)
481 SAVE_U_PCB_REG(a0, SR, k1)
482 SAVE_U_PCB_REG(a1, CAUSE, k1)
483 SAVE_U_PCB_REG(a2, BADVADDR, k1)
484 SAVE_U_PCB_REG(a3, PC, k1)
485 REG_S a3, CALLFRAME_RA(sp) # for debugging
486 PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
487 # Turn off fpu and enter kernel mode
488 and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_KSU_MASK | MIPS_SR_INT_IE)
489 #if defined(CPU_CNMIPS)
490 and t0, t0, ~(MIPS_SR_COP_2_BIT)
491 or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
492 #elif defined(CPU_RMI) || defined(CPU_NLM)
493 or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT)
495 mtc0 t0, MIPS_COP_0_STATUS
496 PTR_ADDU a0, k1, U_PCB_REGS
500 * Call the exception handler.
502 PTR_LA k0, _C_LABEL(trap)
507 * Restore user registers and return.
508 * First disable interrupts and set exeption level.
515 * The use of k1 for storing the PCB pointer must be done only
516 * after interrupts are disabled. Otherwise it will get overwritten
517 * by the interrupt code.
520 PTR_L k1, PC_CURPCB(k1)
523 * Update interrupt mask in saved status register
524 * Some of interrupts could be enabled by ithread
527 mfc0 a0, MIPS_COP_0_STATUS
528 and a0, a0, MIPS_SR_INT_MASK
529 RESTORE_U_PCB_REG(a1, SR, k1)
530 and a1, a1, ~MIPS_SR_INT_MASK
532 SAVE_U_PCB_REG(a1, SR, k1)
534 RESTORE_U_PCB_REG(t0, MULLO, k1)
535 RESTORE_U_PCB_REG(t1, MULHI, k1)
538 RESTORE_U_PCB_REG(a0, PC, k1)
539 RESTORE_U_PCB_REG(v0, V0, k1)
540 MTC0 a0, MIPS_COP_0_EXC_PC # set return address
541 RESTORE_U_PCB_REG(v1, V1, k1)
542 RESTORE_U_PCB_REG(a0, A0, k1)
543 RESTORE_U_PCB_REG(a1, A1, k1)
544 RESTORE_U_PCB_REG(a2, A2, k1)
545 RESTORE_U_PCB_REG(a3, A3, k1)
546 RESTORE_U_PCB_REG(t0, T0, k1)
547 RESTORE_U_PCB_REG(t1, T1, k1)
548 RESTORE_U_PCB_REG(t2, T2, k1)
549 RESTORE_U_PCB_REG(t3, T3, k1)
550 RESTORE_U_PCB_REG(ta0, TA0, k1)
551 RESTORE_U_PCB_REG(ta1, TA1, k1)
552 RESTORE_U_PCB_REG(ta2, TA2, k1)
553 RESTORE_U_PCB_REG(ta3, TA3, k1)
554 RESTORE_U_PCB_REG(s0, S0, k1)
555 RESTORE_U_PCB_REG(s1, S1, k1)
556 RESTORE_U_PCB_REG(s2, S2, k1)
557 RESTORE_U_PCB_REG(s3, S3, k1)
558 RESTORE_U_PCB_REG(s4, S4, k1)
559 RESTORE_U_PCB_REG(s5, S5, k1)
560 RESTORE_U_PCB_REG(s6, S6, k1)
561 RESTORE_U_PCB_REG(s7, S7, k1)
562 RESTORE_U_PCB_REG(t8, T8, k1)
563 RESTORE_U_PCB_REG(t9, T9, k1)
564 RESTORE_U_PCB_REG(gp, GP, k1)
565 RESTORE_U_PCB_REG(sp, SP, k1)
566 RESTORE_U_PCB_REG(k0, SR, k1)
567 RESTORE_U_PCB_REG(s8, S8, k1)
568 RESTORE_U_PCB_REG(ra, RA, k1)
570 RESTORE_U_PCB_REG(AT, AST, k1)
572 mtc0 k0, MIPS_COP_0_STATUS # still exception level
577 END(MipsUserGenException)
581 NON_LEAF(mips_wait, CALLFRAME_SIZ, ra)
582 PTR_SUBU sp, sp, CALLFRAME_SIZ
583 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
584 REG_S ra, CALLFRAME_RA(sp) # save RA
585 mfc0 t0, MIPS_COP_0_STATUS
586 xori t1, t0, MIPS_SR_INT_IE
587 mtc0 t1, MIPS_COP_0_STATUS
591 REG_L ra, CALLFRAME_RA(sp)
592 mfc0 t0, MIPS_COP_0_STATUS
593 ori t1, t0, MIPS_SR_INT_IE
595 GLOBAL(MipsWaitStart) # this is 16 byte aligned
596 mtc0 t1, MIPS_COP_0_STATUS
600 GLOBAL(MipsWaitEnd) # MipsWaitStart + 16
602 PTR_ADDU sp, sp, CALLFRAME_SIZ
606 /*----------------------------------------------------------------------------
610 * Handle an interrupt from kernel mode.
611 * Interrupts use the standard kernel stack.
612 * switch_exit sets up a kernel stack after exit so interrupts won't fail.
620 *----------------------------------------------------------------------------
623 NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra)
625 PTR_SUBU sp, sp, KERN_EXC_FRAME_SIZE
626 .mask 0x80000000, (CALLFRAME_RA - KERN_EXC_FRAME_SIZE)
629 * Check for getting interrupts just before wait
631 MFC0 k0, MIPS_COP_0_EXC_PC
633 xori k0, 0xf # 16 byte align
634 PTR_LA k1, MipsWaitStart
637 PTR_ADDU k1, 16 # skip over wait
638 MTC0 k1, MIPS_COP_0_EXC_PC
641 * Save CPU state, building 'frame'.
645 * Call the interrupt handler. a0 points at the saved frame.
647 PTR_LA gp, _C_LABEL(_gp)
648 PTR_LA k0, _C_LABEL(cpu_intr)
650 REG_S a3, CALLFRAME_RA + KERN_REG_SIZE(sp) # for debugging
653 * Update interrupt and CPU mask in saved status register
654 * Some of interrupts could be disabled by
655 * intr filters if interrupts are enabled later
658 mfc0 a0, MIPS_COP_0_STATUS
659 and a0, a0, (MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
660 RESTORE_REG(a1, SR, sp)
661 and a1, a1, ~(MIPS_SR_INT_MASK|MIPS_SR_COP_USABILITY)
664 REG_L v0, CALLFRAME_RA + KERN_REG_SIZE(sp)
665 RESTORE_CPU # v0 contains the return address.
671 /*----------------------------------------------------------------------------
675 * Handle an interrupt from user mode.
676 * Note: we save minimal state in the u.u_pcb struct and use the standard
677 * kernel stack since there has to be a u page if we came from user mode.
678 * If there is a pending software interrupt, then save the remaining state
679 * and call softintr(). This is all because if we call switch() inside
680 * interrupt(), not all the user registers have been saved in u.u_pcb.
688 *----------------------------------------------------------------------------
690 NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
692 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
694 * Save the relevant user registers into the u.u_pcb struct.
695 * We don't need to save s0 - s8 because the compiler does it for us.
698 PTR_L k1, PC_CURPCB(k1)
699 SAVE_U_PCB_REG(AT, AST, k1)
701 SAVE_U_PCB_REG(v0, V0, k1)
702 SAVE_U_PCB_REG(v1, V1, k1)
703 SAVE_U_PCB_REG(a0, A0, k1)
704 SAVE_U_PCB_REG(a1, A1, k1)
705 SAVE_U_PCB_REG(a2, A2, k1)
706 SAVE_U_PCB_REG(a3, A3, k1)
707 SAVE_U_PCB_REG(t0, T0, k1)
708 SAVE_U_PCB_REG(t1, T1, k1)
709 SAVE_U_PCB_REG(t2, T2, k1)
710 SAVE_U_PCB_REG(t3, T3, k1)
711 SAVE_U_PCB_REG(ta0, TA0, k1)
712 SAVE_U_PCB_REG(ta1, TA1, k1)
713 SAVE_U_PCB_REG(ta2, TA2, k1)
714 SAVE_U_PCB_REG(ta3, TA3, k1)
715 SAVE_U_PCB_REG(t8, T8, k1)
716 SAVE_U_PCB_REG(t9, T9, k1)
717 SAVE_U_PCB_REG(gp, GP, k1)
718 SAVE_U_PCB_REG(sp, SP, k1)
719 SAVE_U_PCB_REG(ra, RA, k1)
721 * save remaining user state in u.u_pcb.
723 SAVE_U_PCB_REG(s0, S0, k1)
724 SAVE_U_PCB_REG(s1, S1, k1)
725 SAVE_U_PCB_REG(s2, S2, k1)
726 SAVE_U_PCB_REG(s3, S3, k1)
727 SAVE_U_PCB_REG(s4, S4, k1)
728 SAVE_U_PCB_REG(s5, S5, k1)
729 SAVE_U_PCB_REG(s6, S6, k1)
730 SAVE_U_PCB_REG(s7, S7, k1)
731 SAVE_U_PCB_REG(s8, S8, k1)
733 mflo v0 # get lo/hi late to avoid stall
735 mfc0 a0, MIPS_COP_0_STATUS
736 mfc0 a1, MIPS_COP_0_CAUSE
737 MFC0 a3, MIPS_COP_0_EXC_PC
738 SAVE_U_PCB_REG(v0, MULLO, k1)
739 SAVE_U_PCB_REG(v1, MULHI, k1)
740 SAVE_U_PCB_REG(a0, SR, k1)
741 SAVE_U_PCB_REG(a1, CAUSE, k1)
742 SAVE_U_PCB_REG(a3, PC, k1) # PC in a3, note used later!
743 PTR_SUBU sp, k1, CALLFRAME_SIZ # switch to kernel SP
744 PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
746 # Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level.
747 and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS_SR_KSU_MASK)
749 and t0, t0, ~(MIPS_SR_COP_2_BIT)
750 or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
751 #elif defined(CPU_RMI) || defined(CPU_NLM)
752 or t0, t0, (MIPS_SR_KX | MIPS_SR_UX | MIPS_SR_COP_2_BIT)
754 mtc0 t0, MIPS_COP_0_STATUS
756 PTR_ADDU a0, k1, U_PCB_REGS
758 * Call the interrupt handler.
760 PTR_LA k0, _C_LABEL(cpu_intr)
762 REG_S a3, CALLFRAME_RA(sp) # for debugging
765 * Enable interrupts before doing ast().
767 * On SMP kernels the AST processing might trigger IPI to other processors.
768 * If that processor is also doing AST processing with interrupts disabled
769 * then we may deadlock.
771 mfc0 a0, MIPS_COP_0_STATUS
772 or a0, a0, MIPS_SR_INT_IE
773 mtc0 a0, MIPS_COP_0_STATUS
777 * DO_AST enabled interrupts
782 * Restore user registers and return.
787 PTR_L k1, PC_CURPCB(k1)
790 * Update interrupt mask in saved status register
791 * Some of interrupts could be disabled by
794 mfc0 a0, MIPS_COP_0_STATUS
795 and a0, a0, MIPS_SR_INT_MASK
796 RESTORE_U_PCB_REG(a1, SR, k1)
797 and a1, a1, ~MIPS_SR_INT_MASK
799 SAVE_U_PCB_REG(a1, SR, k1)
801 RESTORE_U_PCB_REG(s0, S0, k1)
802 RESTORE_U_PCB_REG(s1, S1, k1)
803 RESTORE_U_PCB_REG(s2, S2, k1)
804 RESTORE_U_PCB_REG(s3, S3, k1)
805 RESTORE_U_PCB_REG(s4, S4, k1)
806 RESTORE_U_PCB_REG(s5, S5, k1)
807 RESTORE_U_PCB_REG(s6, S6, k1)
808 RESTORE_U_PCB_REG(s7, S7, k1)
809 RESTORE_U_PCB_REG(s8, S8, k1)
810 RESTORE_U_PCB_REG(t0, MULLO, k1)
811 RESTORE_U_PCB_REG(t1, MULHI, k1)
812 RESTORE_U_PCB_REG(t2, PC, k1)
815 MTC0 t2, MIPS_COP_0_EXC_PC # set return address
816 RESTORE_U_PCB_REG(v0, V0, k1)
817 RESTORE_U_PCB_REG(v1, V1, k1)
818 RESTORE_U_PCB_REG(a0, A0, k1)
819 RESTORE_U_PCB_REG(a1, A1, k1)
820 RESTORE_U_PCB_REG(a2, A2, k1)
821 RESTORE_U_PCB_REG(a3, A3, k1)
822 RESTORE_U_PCB_REG(t0, T0, k1)
823 RESTORE_U_PCB_REG(t1, T1, k1)
824 RESTORE_U_PCB_REG(t2, T2, k1)
825 RESTORE_U_PCB_REG(t3, T3, k1)
826 RESTORE_U_PCB_REG(ta0, TA0, k1)
827 RESTORE_U_PCB_REG(ta1, TA1, k1)
828 RESTORE_U_PCB_REG(ta2, TA2, k1)
829 RESTORE_U_PCB_REG(ta3, TA3, k1)
830 RESTORE_U_PCB_REG(t8, T8, k1)
831 RESTORE_U_PCB_REG(t9, T9, k1)
832 RESTORE_U_PCB_REG(gp, GP, k1)
833 RESTORE_U_PCB_REG(k0, SR, k1)
834 RESTORE_U_PCB_REG(sp, SP, k1)
835 RESTORE_U_PCB_REG(ra, RA, k1)
837 RESTORE_U_PCB_REG(AT, AST, k1)
839 mtc0 k0, MIPS_COP_0_STATUS # SR with EXL set.
846 NLEAF(MipsTLBInvalidException)
851 MFC0 k0, MIPS_COP_0_BAD_VADDR
852 PTR_LI k1, VM_MAXUSER_ADDRESS
857 /* Kernel address. */
858 lui k1, %hi(kernel_segmap) # k1=hi of segbase
860 PTR_L k1, %lo(kernel_segmap)(k1) # k1=segment tab base
862 1: /* User address. */
864 PTR_L k1, PC_SEGBASE(k1)
866 2: /* Validate page directory pointer. */
870 PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost)
871 beq k1, zero, MipsKernGenException # ==0 -- no seg tab
872 andi k0, k0, PDEPTRMASK #06: k0=seg offset
873 PTR_ADDU k1, k0, k1 # k1=seg entry address
874 PTR_L k1, 0(k1) # k1=seg entry
876 /* Validate page table pointer. */
881 MFC0 k0, MIPS_COP_0_BAD_VADDR
882 PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=pde offset (almost)
883 beq k1, zero, MipsKernGenException # ==0 -- no pde tab
884 andi k0, k0, PDEPTRMASK # k0=pde offset
885 PTR_ADDU k1, k0, k1 # k1=pde entry address
886 PTR_L k1, 0(k1) # k1=pde entry
888 /* Validate pde table pointer. */
892 MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
893 PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN
894 andi k0, k0, PTEMASK # k0=page tab offset
895 PTR_ADDU k1, k1, k0 # k1=pte address
896 PTE_L k0, 0(k1) # k0=this PTE
898 /* Validate page table entry. */
903 /* Check whether this is an even or odd entry. */
909 PTE_L k1, PTESIZE(k1)
911 PTE_MTC0 k0, MIPS_COP_0_TLB_LO0
914 PTE_MTC0 k1, MIPS_COP_0_TLB_LO1
921 PTE_L k0, -PTESIZE(k1)
924 PTE_MTC0 k0, MIPS_COP_0_TLB_LO0
927 PTE_MTC0 k1, MIPS_COP_0_TLB_LO1
933 mfc0 k0, MIPS_COP_0_TLB_INDEX
934 bltz k0, tlb_insert_random
947 * Branch to the comprehensive exception processing.
949 mfc0 k1, MIPS_COP_0_STATUS
950 andi k1, k1, MIPS_SR_KSU_USER
951 bnez k1, _C_LABEL(MipsUserGenException)
955 * Check for kernel stack overflow.
958 PTR_L k0, PC_CURTHREAD(k1)
959 PTR_L k0, TD_KSTACK(k0)
961 bnez k0, _C_LABEL(MipsKernGenException)
965 * Kernel stack overflow.
967 * Move to a valid stack before we call panic. We use the boot stack
972 sll k1, k1, PAGE_SHIFT + 1
974 PTR_LA k0, _C_LABEL(pcpu_space)
975 PTR_ADDU k0, PAGE_SIZE * 2
979 * Stash the original value of 'sp' so we can update trapframe later.
980 * We assume that SAVE_CPU does not trash 'k1'.
985 PTR_SUBU sp, sp, KERN_EXC_FRAME_SIZE
989 REG_S ra, CALLFRAME_RA(sp) /* stop the ddb backtrace right here */
990 REG_S zero, CALLFRAME_SP(sp)
996 * Now restore the value of 'sp' at the time of the tlb exception in
1002 * Squelch any more overflow checks by setting the stack base to 0.
1005 PTR_L k0, PC_CURTHREAD(k1)
1006 PTR_S zero, TD_KSTACK(k0)
1009 PANIC("kernel stack overflow - trapframe at %p")
1012 * This nop is necessary so that the 'ra' remains within the bounds
1013 * of this handler. Otherwise the ddb backtrace code will think that
1014 * the panic() was called from MipsTLBMissException.
1019 END(MipsTLBInvalidException)
1021 /*----------------------------------------------------------------------------
1023 * MipsTLBMissException --
1025 * Handle a TLB miss exception from kernel mode in kernel space.
1026 * The BaddVAddr, Context, and EntryHi registers contain the failed
1035 *----------------------------------------------------------------------------
1037 NLEAF(MipsTLBMissException)
1039 MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address
1040 PTR_LI k1, VM_MAX_KERNEL_ADDRESS # check fault address against
1041 sltu k1, k1, k0 # upper bound of kernel_segmap
1042 bnez k1, MipsKernGenException # out of bound
1043 lui k1, %hi(kernel_segmap) # k1=hi of segbase
1044 PTR_SRL k0, SEGSHIFT - PTRSHIFT # k0=seg offset (almost)
1045 PTR_L k1, %lo(kernel_segmap)(k1) # k1=segment tab base
1046 beq k1, zero, MipsKernGenException # ==0 -- no seg tab
1047 andi k0, k0, PDEPTRMASK #06: k0=seg offset
1048 PTR_ADDU k1, k0, k1 # k1=seg entry address
1049 PTR_L k1, 0(k1) # k1=seg entry
1050 MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
1051 beq k1, zero, MipsKernGenException # ==0 -- no page table
1053 PTR_SRL k0, PDRSHIFT - PTRSHIFT # k0=VPN
1054 andi k0, k0, PDEPTRMASK # k0=pde offset
1055 PTR_ADDU k1, k0, k1 # k1=pde entry address
1056 PTR_L k1, 0(k1) # k1=pde entry
1057 MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
1058 beq k1, zero, MipsKernGenException # ==0 -- no page table
1060 PTR_SRL k0, PAGE_SHIFT - PTESHIFT # k0=VPN
1061 andi k0, k0, PTE2MASK # k0=page tab offset
1062 PTR_ADDU k1, k1, k0 # k1=pte address
1063 PTE_L k0, 0(k1) # k0=lo0 pte
1064 PTE_L k1, PTESIZE(k1) # k1=lo1 pte
1065 CLEAR_PTE_SWBITS(k0)
1066 PTE_MTC0 k0, MIPS_COP_0_TLB_LO0 # lo0 is loaded
1068 CLEAR_PTE_SWBITS(k1)
1069 PTE_MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded
1071 tlbwr # write to tlb
1073 eret # return from exception
1075 END(MipsTLBMissException)
1077 /*----------------------------------------------------------------------------
1081 * Handle a floating point Trap.
1083 * MipsFPTrap(statusReg, causeReg, pc)
1084 * unsigned statusReg;
1085 * unsigned causeReg;
1094 *----------------------------------------------------------------------------
1096 NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra)
1097 PTR_SUBU sp, sp, CALLFRAME_SIZ
1098 mfc0 t0, MIPS_COP_0_STATUS
1099 REG_S ra, CALLFRAME_RA(sp)
1100 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
1102 or t1, t0, MIPS_SR_COP_1_BIT
1103 mtc0 t1, MIPS_COP_0_STATUS
1105 cfc1 t1, MIPS_FPU_CSR # stall til FP done
1106 cfc1 t1, MIPS_FPU_CSR # now get status
1108 sll t2, t1, (31 - 17) # unimplemented operation?
1109 bgez t2, 3f # no, normal trap
1112 * We got an unimplemented operation trap so
1113 * fetch the instruction, compute the next PC and emulate the instruction.
1115 bgez a1, 1f # Check the branch delay bit.
1118 * The instruction is in the branch delay slot so the branch will have to
1119 * be emulated to get the resulting PC.
1121 PTR_S a2, CALLFRAME_SIZ + 8(sp)
1124 PTR_L a0, PC_CURPCB(a0)
1125 PTR_ADDU a0, a0, U_PCB_REGS # first arg is ptr to CPU registers
1126 move a1, a2 # second arg is instruction PC
1127 move a2, t1 # third arg is floating point CSR
1128 PTR_LA t3, _C_LABEL(MipsEmulateBranch) # compute PC after branch
1129 jalr t3 # compute PC after branch
1130 move a3, zero # fourth arg is FALSE
1132 * Now load the floating-point instruction in the branch delay slot
1135 PTR_L a2, CALLFRAME_SIZ + 8(sp) # restore EXC pc
1137 lw a0, 4(a2) # a0 = coproc instruction
1139 * This is not in the branch delay slot so calculate the resulting
1140 * PC (epc + 4) into v0 and continue to MipsEmulateFP().
1143 lw a0, 0(a2) # a0 = coproc instruction
1145 PTR_ADDU v0, a2, 4 # v0 = next pc
1148 PTR_L t2, PC_CURPCB(t2)
1149 SAVE_U_PCB_REG(v0, PC, t2) # save new pc
1151 * Check to see if the instruction to be emulated is a floating-point
1154 srl a3, a0, MIPS_OPCODE_SHIFT
1155 beq a3, MIPS_OPCODE_C1, 4f # this should never fail
1158 * Send a floating point exception signal to the current process.
1162 PTR_L a0, PC_CURTHREAD(a0) # get current thread
1163 cfc1 a2, MIPS_FPU_CSR # code = FP execptions
1164 ctc1 zero, MIPS_FPU_CSR # Clear exceptions
1165 PTR_LA t3, _C_LABEL(trapsignal)
1172 * Finally, we can call MipsEmulateFP() where a0 is the instruction to emulate.
1175 PTR_LA t3, _C_LABEL(MipsEmulateFP)
1180 * Turn off the floating point coprocessor and return.
1183 mfc0 t0, MIPS_COP_0_STATUS
1184 PTR_L ra, CALLFRAME_RA(sp)
1185 and t0, t0, ~MIPS_SR_COP_1_BIT
1186 mtc0 t0, MIPS_COP_0_STATUS
1189 PTR_ADDU sp, sp, CALLFRAME_SIZ
1193 * Interrupt counters for vmstat.
1201 .space INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
1204 .quad INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
1206 .int INTRCNT_COUNT * (MAXCOMLEN + 1) * 2
1209 .align (_MIPS_SZLONG / 8)
1211 .space INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
1214 .quad INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
1216 .int INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
1221 * Vector to real handler in KSEG1.
1224 VECTOR(MipsCache, unknown)
1225 PTR_LA k0, _C_LABEL(MipsCacheException)
1226 li k1, MIPS_KSEG0_PHYS_MASK
1228 PTR_LI k1, MIPS_KSEG1_START
1232 VECTOR_END(MipsCache)
1238 * Panic on cache errors. A lot more could be done to recover
1239 * from some types of errors but it is tricky.
1241 NESTED_NOPROFILE(MipsCacheException, KERN_EXC_FRAME_SIZE, ra)
1243 .mask 0x80000000, -4
1244 PTR_LA k0, _C_LABEL(panic) # return to panic
1245 PTR_LA a0, 9f # panicstr
1246 MFC0 a1, MIPS_COP_0_ERROR_PC
1247 mfc0 a2, MIPS_COP_0_CACHE_ERR # 3rd arg cache error
1249 MTC0 k0, MIPS_COP_0_ERROR_PC # set return address
1251 mfc0 k0, MIPS_COP_0_STATUS # restore status
1252 li k1, MIPS_SR_DIAG_PE # ignore further errors
1254 mtc0 k0, MIPS_COP_0_STATUS # restore status
1259 MSG("cache error @ EPC 0x%x CachErr 0x%x");
1261 END(MipsCacheException)