1 /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department, The Mach Operating System project at
11 * Carnegie-Mellon University and Ralph Campbell.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
38 * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp
39 * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include "opt_cputype.h"
49 #include <sys/param.h>
51 #include <sys/systm.h>
56 #include <sys/kernel.h>
57 #include <sys/linker.h>
58 #include <sys/malloc.h>
60 #include <sys/msgbuf.h>
61 #include <sys/reboot.h>
62 #include <sys/sched.h>
63 #include <sys/sysctl.h>
64 #include <sys/sysproto.h>
65 #include <sys/vmmeter.h>
68 #include <vm/vm_kern.h>
69 #include <vm/vm_object.h>
70 #include <vm/vm_page.h>
72 #include <vm/vm_map.h>
73 #include <vm/vm_pager.h>
74 #include <vm/vm_extern.h>
75 #include <sys/socket.h>
78 #include <sys/interrupt.h>
80 #include <sys/syslog.h>
81 #include <machine/asm.h>
82 #include <machine/bootinfo.h>
83 #include <machine/cache.h>
84 #include <machine/clock.h>
85 #include <machine/cpu.h>
86 #include <machine/cpuregs.h>
87 #include <machine/elf.h>
88 #include <machine/hwfunc.h>
89 #include <machine/intr_machdep.h>
90 #include <machine/md_var.h>
91 #include <machine/tlb.h>
97 #include <sys/random.h>
100 #define BOOTINFO_DEBUG 0
102 char machine[] = "mips";
103 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class");
105 static char cpu_model[30];
106 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model");
111 int cpu_clock = MIPS_DEFAULT_HZ;
112 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
113 &cpu_clock, 0, "CPU instruction clock rate");
114 int clocks_running = 0;
119 * Each entry in the pcpu_space[] array is laid out in the following manner:
120 * struct pcpu for cpu 'n' pcpu_space[n]
121 * boot stack for cpu 'n' pcpu_space[n] + PAGE_SIZE * 2 - CALLFRAME_SIZ
123 * Note that the boot stack grows downwards and we assume that we never
124 * use enough stack space to trample over the 'struct pcpu' that is at
125 * the beginning of the array.
127 * The array is aligned on a (PAGE_SIZE * 2) boundary so that the 'struct pcpu'
128 * is always in the even page frame of the wired TLB entry on SMP kernels.
130 * The array is in the .data section so that the stack does not get zeroed out
131 * when the .bss section is zeroed.
133 char pcpu_space[MAXCPU][PAGE_SIZE * 2] \
134 __aligned(PAGE_SIZE * 2) __section(".data");
136 struct pcpu *pcpup = (struct pcpu *)pcpu_space;
138 vm_offset_t phys_avail[PHYS_AVAIL_ENTRIES + 2];
139 vm_offset_t physmem_desc[PHYS_AVAIL_ENTRIES + 2];
140 vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
143 struct platform platform;
146 static void cpu_startup(void *);
147 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
149 struct kva_md_info kmi;
151 int cpucfg; /* Value of processor config register */
152 int num_tlbentries = 64; /* Size of the CPU tlb */
155 extern char MipsException[], MipsExceptionEnd[];
157 /* TLB miss handler address and end */
158 extern char MipsTLBMiss[], MipsTLBMissEnd[];
160 /* Cache error handler */
161 extern char MipsCache[], MipsCacheEnd[];
163 extern char edata[], end[];
165 extern vm_offset_t ksym_start, ksym_end;
169 struct bootinfo bootinfo;
171 * First kseg0 address available for use. By default it's equal to &end.
172 * But in some cases there might be additional data placed right after
173 * _end by loader or ELF trampoline.
175 vm_offset_t kernel_kseg0_end = (vm_offset_t)&end;
178 cpu_startup(void *dummy)
181 if (boothowto & RB_VERBOSE)
184 printf("real memory = %lu (%luK bytes)\n", ptoa(realmem),
185 ptoa(realmem) / 1024);
188 * Display any holes after the first chunk of extended memory.
193 printf("Physical memory chunk(s):\n");
194 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
195 uintptr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
197 printf("0x%08llx - 0x%08llx, %llu bytes (%llu pages)\n",
198 (unsigned long long)phys_avail[indx],
199 (unsigned long long)phys_avail[indx + 1] - 1,
200 (unsigned long long)size1,
201 (unsigned long long)size1 / PAGE_SIZE);
205 vm_ksubmap_init(&kmi);
207 printf("avail memory = %lu (%luMB)\n", ptoa(cnt.v_free_count),
208 ptoa(cnt.v_free_count) / 1048576);
209 cpu_init_interrupts();
212 * Set up buffers, so they can be used to read disk labels.
215 vm_pager_bufferinit();
219 * Shutdown the CPU as much as possible
229 * Flush the D-cache for non-DMA I/O so that the I-cache can
230 * be made coherent later.
233 cpu_flush_dcache(void *ptr, size_t len)
238 /* Get current clock frequency for the given cpu id. */
240 cpu_est_clockrate(int cpu_id, uint64_t *rate)
247 * Shutdown the CPU as much as possible
256 SYSCTL_STRUCT(_machdep, OID_AUTO, bootinfo, CTLFLAG_RD, &bootinfo,
257 bootinfo, "Bootinfo struct: kernel filename, BIOS harddisk geometry, etc");
260 * Initialize per cpu data structures, include curthread.
265 /* Initialize pcpu info of cpu-zero */
266 pcpu_init(PCPU_ADDR(0), 0, sizeof(struct pcpu));
267 PCPU_SET(curthread, &thread0);
271 * Initialize mips and configure to run kernel
274 mips_proc0_init(void)
277 if (platform_processor_id() != 0)
278 panic("BSP must be processor number 0");
280 proc_linkup0(&proc0, &thread0);
282 KASSERT((kstack0 & PAGE_MASK) == 0,
283 ("kstack0 is not aligned on a page boundary: 0x%0lx",
285 thread0.td_kstack = kstack0;
286 thread0.td_kstack_pages = KSTACK_PAGES;
288 * Do not use cpu_thread_alloc to initialize these fields
289 * thread0 is the only thread that has kstack located in KSEG0
290 * while cpu_thread_alloc handles kstack allocated in KSEG2.
292 thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
293 thread0.td_kstack_pages * PAGE_SIZE) - 1;
294 thread0.td_frame = &thread0.td_pcb->pcb_regs;
296 /* Steal memory for the dynamic per-cpu area. */
297 dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0);
299 PCPU_SET(curpcb, thread0.td_pcb);
301 * There is no need to initialize md_upte array for thread0 as it's
302 * located in .bss section and should be explicitly zeroed during
303 * kernel initialization.
310 platform_initclocks();
313 struct msgbuf *msgbufp=0;
316 * Initialize the hardware exception vectors, and the jump table used to
317 * call locore cache and TLB management functions, based on the kind
318 * of CPU the kernel is running on.
321 mips_vector_init(void)
324 * Copy down exception vector code.
326 if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
327 panic("startup: UTLB code too large");
329 if (MipsCacheEnd - MipsCache > 0x80)
330 panic("startup: Cache error code too large");
332 bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
333 MipsTLBMissEnd - MipsTLBMiss);
335 #if defined(CPU_CNMIPS) || defined(CPU_RMI)
336 /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
337 bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC,
338 MipsTLBMissEnd - MipsTLBMiss);
341 bcopy(MipsException, (void *)MIPS3_GEN_EXC_VEC,
342 MipsExceptionEnd - MipsException);
344 bcopy(MipsCache, (void *)MIPS3_CACHE_ERR_EXC_VEC,
345 MipsCacheEnd - MipsCache);
348 * Clear out the I and D caches.
350 mips_icache_sync_all();
351 mips_dcache_wbinv_all();
354 * Mask all interrupts. Each interrupt will be enabled
355 * when handler is installed for it
359 /* Clear BEV in SR so we start handling our own exceptions */
360 mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
364 * Fix kernel_kseg0_end address in case trampoline placed debug sympols
368 mips_postboot_fixup(void)
371 Elf_Size *trampoline_data = (Elf_Size*)kernel_kseg0_end;
372 Elf_Size symtabsize = 0;
374 if (trampoline_data[0] == SYMTAB_MAGIC) {
375 symtabsize = trampoline_data[1];
376 kernel_kseg0_end += 2 * sizeof(Elf_Size);
377 /* start of .symtab */
378 ksym_start = kernel_kseg0_end;
379 kernel_kseg0_end += symtabsize;
381 ksym_end = kernel_kseg0_end;
387 * Many SoCs have a means to reset the core itself. Others do not, or
388 * the method is unknown to us. For those cases, we jump to the mips
389 * reset vector and hope for the best. This works well in practice.
394 ((void(*)(void))(intptr_t)MIPS_VEC_RESET)();
399 mips_pcpu_tlb_init(struct pcpu *pcpu)
405 * Map the pcpu structure at the virtual address 'pcpup'.
406 * We use a wired tlb index to do this one-time mapping.
409 pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE;
410 tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
411 TLBLO_PA_TO_PFN(pa) | pte,
412 TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
417 * Initialise a struct pcpu.
420 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
423 pcpu->pc_next_asid = 1;
424 pcpu->pc_asid_generation = 1;
426 if ((vm_offset_t)pcpup >= VM_MIN_KERNEL_ADDRESS)
427 mips_pcpu_tlb_init(pcpu);
432 fill_dbregs(struct thread *td, struct dbreg *dbregs)
435 /* No debug registers on mips */
440 set_dbregs(struct thread *td, struct dbreg *dbregs)
443 /* No debug registers on mips */
454 if (td->td_md.md_spinlock_count == 0) {
455 intr = intr_disable();
456 td->td_md.md_spinlock_count = 1;
457 td->td_md.md_saved_intr = intr;
459 td->td_md.md_spinlock_count++;
471 intr = td->td_md.md_saved_intr;
472 td->td_md.md_spinlock_count--;
473 if (td->td_md.md_spinlock_count == 0)
478 * call platform specific code to halt (until next interrupt) for the idle loop
483 if (mips_rd_status() & MIPS_SR_INT_IE)
484 __asm __volatile ("wait");
486 panic("ints disabled in idleproc!");
490 cpu_idle_wakeup(int cpu)
497 is_cacheable_mem(vm_offset_t addr)
501 for (i = 0; physmem_desc[i + 1] != 0; i += 2) {
502 if (addr >= physmem_desc[i] && addr < physmem_desc[i + 1])