2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/param.h>
32 #include <sys/kernel.h>
33 #include <sys/systm.h>
38 #include <vm/vm_page.h>
40 #include <machine/pte.h>
41 #include <machine/tlb.h>
49 } entry[MIPS_MAX_TLB_ENTRIES];
52 static struct tlb_state tlb_state[MAXCPU];
56 * PageMask must increment in steps of 2 bits.
58 COMPILE_TIME_ASSERT(POPCNT(TLBMASK_MASK) % 2 == 0);
64 __asm __volatile ("tlbp" : : : "memory");
71 __asm __volatile ("tlbr" : : : "memory");
76 tlb_write_indexed(void)
78 __asm __volatile ("tlbwi" : : : "memory");
83 tlb_write_random(void)
85 __asm __volatile ("tlbwr" : : : "memory");
89 static void tlb_invalidate_one(unsigned);
92 tlb_insert_wired(unsigned i, vm_offset_t va, pt_entry_t pte0, pt_entry_t pte1)
100 asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
104 mips_wr_entryhi(TLBHI_ENTRY(va, 0));
105 mips_wr_entrylo0(pte0);
106 mips_wr_entrylo1(pte1);
109 mips_wr_entryhi(asid);
114 tlb_invalidate_address(struct pmap *pmap, vm_offset_t va)
123 asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
126 mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
130 tlb_invalidate_one(i);
132 mips_wr_entryhi(asid);
137 tlb_invalidate_all(void)
144 asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
146 for (i = mips_rd_wired(); i < num_tlbentries; i++)
147 tlb_invalidate_one(i);
149 mips_wr_entryhi(asid);
154 tlb_invalidate_all_user(struct pmap *pmap)
161 asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
163 for (i = mips_rd_wired(); i < num_tlbentries; i++) {
169 uasid = mips_rd_entryhi() & TLBHI_ASID_MASK;
172 * Invalidate all non-kernel entries.
178 * Invalidate this pmap's entries.
180 if (uasid != pmap_asid(pmap))
183 tlb_invalidate_one(i);
186 mips_wr_entryhi(asid);
190 /* XXX Only if DDB? */
196 cpu = PCPU_GET(cpuid);
198 tlb_state[cpu].wired = mips_rd_wired();
199 for (i = 0; i < num_tlbentries; i++) {
203 tlb_state[cpu].entry[i].entryhi = mips_rd_entryhi();
204 tlb_state[cpu].entry[i].entrylo0 = mips_rd_entrylo0();
205 tlb_state[cpu].entry[i].entrylo1 = mips_rd_entrylo1();
210 tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte)
217 pte &= ~TLBLO_SWBITS_MASK;
220 asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
223 mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
229 if ((va & PAGE_SIZE) == 0) {
230 mips_wr_entrylo0(pte);
232 mips_wr_entrylo1(pte);
237 mips_wr_entryhi(asid);
242 tlb_invalidate_one(unsigned i)
244 /* XXX an invalid ASID? */
245 mips_wr_entryhi(TLBHI_ENTRY(MIPS_KSEG0_START + (2 * i * PAGE_SIZE), 0));
256 DB_SHOW_COMMAND(tlb, ddb_dump_tlb)
258 register_t ehi, elo0, elo1;
263 * The worst conversion from hex to decimal ever.
266 cpu = ((addr >> 4) % 16) * 10 + (addr % 16);
268 cpu = PCPU_GET(cpuid);
270 if (cpu < 0 || cpu >= mp_ncpus) {
271 db_printf("Invalid CPU %u\n", cpu);
275 if (cpu == PCPU_GET(cpuid))
278 db_printf("Beginning TLB dump for CPU %u...\n", cpu);
279 for (i = 0; i < num_tlbentries; i++) {
280 if (i == tlb_state[cpu].wired) {
282 db_printf("^^^ WIRED ENTRIES ^^^\n");
284 db_printf("(No wired entries.)\n");
288 ehi = tlb_state[cpu].entry[i].entryhi;
289 elo0 = tlb_state[cpu].entry[i].entrylo0;
290 elo1 = tlb_state[cpu].entry[i].entrylo1;
292 if (elo0 == 0 && elo1 == 0)
295 db_printf("#%u\t=> %jx\n", i, (intmax_t)ehi);
296 db_printf(" Lo0\t%jx\t(%#jx)\n", (intmax_t)elo0, (intmax_t)TLBLO_PTE_TO_PA(elo0));
297 db_printf(" Lo1\t%jx\t(%#jx)\n", (intmax_t)elo1, (intmax_t)TLBLO_PTE_TO_PA(elo1));
299 db_printf("Finished.\n");