2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __NLM_BOARD_H__
33 #define __NLM_BOARD_H__
35 #define XLP_NAE_NBLOCKS 5
36 #define XLP_NAE_NPORTS 4
39 * EVP board EEPROM info
41 #define EEPROM_I2CBUS 1
42 #define EEPROM_I2CADDR 0xAE
43 #define EEPROM_SIZE 48
44 #define EEPROM_MACADDR_OFFSET 2
46 /* used if there is no FDT */
47 #define BOARD_CONSOLE_SPEED 115200
48 #define BOARD_CONSOLE_UART 0
51 * EVP board CPLD chip select and daughter card info field
53 #define XLP_EVB_CPLD_CHIPSELECT 2
55 #define DCARD_ILAKEN 0x0
56 #define DCARD_SGMII 0x1
57 #define DCARD_XAUI 0x2
58 #define DCARD_NOT_PRSNT 0x3
60 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
65 struct xlp_port_ivars {
95 int stg2_frout_credit;
98 u_int ieee1588_inc_intg;
99 u_int ieee1588_inc_den;
100 u_int ieee1588_inc_num;
101 uint64_t ieee1588_userval;
102 uint64_t ieee1588_ptpoff;
103 uint64_t ieee1588_tmr1;
104 uint64_t ieee1588_tmr2;
105 uint64_t ieee1588_tmr3;
108 struct xlp_block_ivars {
112 struct xlp_port_ivars port_ivars[XLP_NAE_NPORTS];
115 struct xlp_nae_ivars {
126 u_int prepad_size; /* size in 16 byte units */
128 struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS];
131 struct xlp_board_info {
133 struct xlp_node_info {
134 struct xlp_nae_ivars nae_ivars;
135 } nodes[XLP_MAX_NODES];
138 extern struct xlp_board_info xlp_board_info;
140 /* Network configuration */
141 int nlm_get_vfbid_mapping(int);
142 int nlm_get_poe_distvec(int vec, uint32_t *distvec);
143 void xlpge_get_macaddr(uint8_t *macaddr);
145 int nlm_board_info_setup(void);
148 int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
149 uint8_t *buf,int sz);
150 uint64_t nlm_board_cpld_base(int node, int chipselect);
151 int nlm_board_cpld_majorversion(uint64_t cpldbase);
152 int nlm_board_cpld_minorversion(uint64_t cpldbase);
153 void nlm_board_cpld_reset(uint64_t cpldbase);
154 int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);