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32 #ifndef __XLP_PCIBUS_H__
33 #define __XLP_PCIBUS_H__
35 #define MSI_MIPS_ADDR_BASE 0xfee00000
37 #define MSI_MIPS_ADDR_DEST 0x000ff000
38 #define MSI_MIPS_ADDR_RH 0x00000008
39 #define MSI_MIPS_ADDR_RH_OFF 0x00000000
40 #define MSI_MIPS_ADDR_RH_ON 0x00000008
41 #define MSI_MIPS_ADDR_DM 0x00000004
42 #define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
43 #define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
45 /* Fields in data for Intel MSI messages. */
46 #define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
47 #define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
48 #define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
50 #define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
51 #define MSI_MIPS_DATA_DEASSERT 0x00000000
52 #define MSI_MIPS_DATA_ASSERT 0x00004000
54 #define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
55 #define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
56 #define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
58 #define MSI_MIPS_DATA_INTVEC 0x000000ff
60 /* PCIE Memory and IO regions */
61 #define PCIE_MEM_BASE 0xd0000000ULL
62 #define PCIE_MEM_LIMIT 0xdfffffffULL
63 #define PCIE_IO_BASE 0x14000000ULL
64 #define PCIE_IO_LIMIT 0x15ffffffULL
66 #define PCIE_BRIDGE_CMD 0x1
67 #define PCIE_BRIDGE_MSI_CAP 0x14
68 #define PCIE_BRIDGE_MSI_ADDRL 0x15
69 #define PCIE_BRIDGE_MSI_ADDRH 0x16
70 #define PCIE_BRIDGE_MSI_DATA 0x17
72 /* XLP Global PCIE configuration space registers */
73 #define PCIE_BYTE_SWAP_MEM_BASE 0x247
74 #define PCIE_BYTE_SWAP_MEM_LIM 0x248
75 #define PCIE_BYTE_SWAP_IO_BASE 0x249
76 #define PCIE_BYTE_SWAP_IO_LIM 0x24A
77 #define PCIE_MSI_STATUS 0x25A
78 #define PCIE_MSI_EN 0x25B
79 #define PCIE_INT_EN0 0x261
82 #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
85 #define PCIE_MSI_INT_EN (1 << 9)
87 /* XXXJC: Ax workaround */
88 #define PCIE_LINK0_IRT 78
90 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
92 #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
93 #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
94 #define nlm_get_pcie_base(node, inst) \
95 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
96 #define nlm_get_pcie_regbase(node, inst) \
97 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
100 xlp_pcie_link_irt(int link)
102 if ((link < 0) || (link > 3))
105 return (PCIE_LINK0_IRT + link);
109 * Build Intel MSI message and data values from a source. AMD64 systems
110 * seem to be compatible, so we use the same function for both.
112 #define MIPS_MSI_ADDR(cpu) \
113 (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
114 MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
116 #define MIPS_MSI_DATA(irq) \
117 (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
118 MSI_MIPS_DATA_ASSERT | (irq))
121 #endif /* __XLP_PCIBUS_H__ */