2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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32 #ifndef _NLM_HAL_PIC_H
33 #define _NLM_HAL_PIC_H
35 /* PIC Specific registers */
38 /* PIC control register defines */
39 #define PIC_CTRL_ITV 32 /* interrupt timeout value */
40 #define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */
41 #define PIC_CTRL_ITE 18 /* interrupt timeout enable */
42 #define PIC_CTRL_STE 10 /* system timer interrupt enable */
43 #define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */
44 #define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */
45 #define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */
46 #define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */
47 #define PIC_CTRL_WTE 0 /* watchdog timer enable */
49 /* PIC Status register defines */
50 #define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */
51 #define PIC_ITE_STATUS 32 /* interrupt timeout status */
52 #define PIC_STS_STATUS 4 /* System timer interrupt status */
53 #define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */
54 #define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */
56 /* PIC IPI control register offsets */
57 #define PIC_IPICTRL_NMI 32
58 #define PIC_IPICTRL_RIV 20 /* received interrupt vector */
59 #define PIC_IPICTRL_IDB 16 /* interrupt destination base */
60 #define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */
62 /* PIC IRT register offsets */
63 #define PIC_IRT_ENABLE 31
64 #define PIC_IRT_NMI 29
65 #define PIC_IRT_SCH 28 /* Scheduling scheme */
66 #define PIC_IRT_RVEC 20 /* Interrupt receive vectors */
67 #define PIC_IRT_DT 19 /* Destination type */
68 #define PIC_IRT_DB 16 /* Destination base */
69 #define PIC_IRT_DTE 0 /* Destination thread enables */
71 #define PIC_BYTESWAP 0x02
72 #define PIC_STATUS 0x04
73 #define PIC_INTR_TIMEOUT 0x06
74 #define PIC_ICI0_INTR_TIMEOUT 0x08
75 #define PIC_ICI1_INTR_TIMEOUT 0x0a
76 #define PIC_ICI2_INTR_TIMEOUT 0x0c
77 #define PIC_IPI_CTL 0x0e
78 #define PIC_INT_ACK 0x10
79 #define PIC_INT_PENDING0 0x12
80 #define PIC_INT_PENDING1 0x14
81 #define PIC_INT_PENDING2 0x16
83 #define PIC_WDOG0_MAXVAL 0x18
84 #define PIC_WDOG0_COUNT 0x1a
85 #define PIC_WDOG0_ENABLE0 0x1c
86 #define PIC_WDOG0_ENABLE1 0x1e
87 #define PIC_WDOG0_BEATCMD 0x20
88 #define PIC_WDOG0_BEAT0 0x22
89 #define PIC_WDOG0_BEAT1 0x24
91 #define PIC_WDOG1_MAXVAL 0x26
92 #define PIC_WDOG1_COUNT 0x28
93 #define PIC_WDOG1_ENABLE0 0x2a
94 #define PIC_WDOG1_ENABLE1 0x2c
95 #define PIC_WDOG1_BEATCMD 0x2e
96 #define PIC_WDOG1_BEAT0 0x30
97 #define PIC_WDOG1_BEAT1 0x32
99 #define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
100 #define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
101 #define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
102 #define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
103 #define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
104 #define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
105 #define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
107 #define PIC_TIMER0_MAXVAL 0x34
108 #define PIC_TIMER1_MAXVAL 0x36
109 #define PIC_TIMER2_MAXVAL 0x38
110 #define PIC_TIMER3_MAXVAL 0x3a
111 #define PIC_TIMER4_MAXVAL 0x3c
112 #define PIC_TIMER5_MAXVAL 0x3e
113 #define PIC_TIMER6_MAXVAL 0x40
114 #define PIC_TIMER7_MAXVAL 0x42
115 #define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2))
117 #define PIC_TIMER0_COUNT 0x44
118 #define PIC_TIMER1_COUNT 0x46
119 #define PIC_TIMER2_COUNT 0x48
120 #define PIC_TIMER3_COUNT 0x4a
121 #define PIC_TIMER4_COUNT 0x4c
122 #define PIC_TIMER5_COUNT 0x4e
123 #define PIC_TIMER6_COUNT 0x50
124 #define PIC_TIMER7_COUNT 0x52
125 #define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2))
127 #define PIC_ITE0_N0_N1 0x54
128 #define PIC_ITE1_N0_N1 0x58
129 #define PIC_ITE2_N0_N1 0x5c
130 #define PIC_ITE3_N0_N1 0x60
131 #define PIC_ITE4_N0_N1 0x64
132 #define PIC_ITE5_N0_N1 0x68
133 #define PIC_ITE6_N0_N1 0x6c
134 #define PIC_ITE7_N0_N1 0x70
135 #define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4))
137 #define PIC_ITE0_N2_N3 0x56
138 #define PIC_ITE1_N2_N3 0x5a
139 #define PIC_ITE2_N2_N3 0x5e
140 #define PIC_ITE3_N2_N3 0x62
141 #define PIC_ITE4_N2_N3 0x66
142 #define PIC_ITE5_N2_N3 0x6a
143 #define PIC_ITE6_N2_N3 0x6e
144 #define PIC_ITE7_N2_N3 0x72
145 #define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4))
147 #define PIC_IRT0 0x74
148 #define PIC_IRT(i) (PIC_IRT0 + ((i) * 2))
150 #define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL
155 #define PIC_IRT_WD_0_INDEX 0
156 #define PIC_IRT_WD_1_INDEX 1
157 #define PIC_IRT_WD_NMI_0_INDEX 2
158 #define PIC_IRT_WD_NMI_1_INDEX 3
159 #define PIC_IRT_TIMER_0_INDEX 4
160 #define PIC_IRT_TIMER_1_INDEX 5
161 #define PIC_IRT_TIMER_2_INDEX 6
162 #define PIC_IRT_TIMER_3_INDEX 7
163 #define PIC_IRT_TIMER_4_INDEX 8
164 #define PIC_IRT_TIMER_5_INDEX 9
165 #define PIC_IRT_TIMER_6_INDEX 10
166 #define PIC_IRT_TIMER_7_INDEX 11
167 #define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
168 #define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX)
170 #define PIC_CLOCK_TIMER 7
171 #define PIC_IRQ_BASE 8
173 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
175 #define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE)
176 #define PIC_IRT_LAST_IRQ 63
177 #define XLP_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRT_FIRST_IRQ)
182 #define PIC_IRT_VALID 1
183 #define PIC_LOCAL_SCHEDULING 1
184 #define PIC_GLOBAL_SCHEDULING 0
186 #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r)
187 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
188 #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
189 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
191 /* IRT and h/w interrupt routines */
193 nlm_pic_read_irt(uint64_t base, int irt_index)
195 return nlm_read_pic_reg(base, PIC_IRT(irt_index));
199 nlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi)
206 ipi = ((uint64_t)nmi << 31) | (vec << 20) | (node << 17) |
209 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
211 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
214 static inline uint64_t
215 nlm_pic_read_control(uint64_t base)
217 return nlm_read_pic_reg(base, PIC_CTRL);
221 nlm_pic_write_control(uint64_t base, uint64_t control)
223 nlm_write_pic_reg(base, PIC_CTRL, control);
227 nlm_pic_update_control(uint64_t base, uint64_t control)
231 val = nlm_read_pic_reg(base, PIC_CTRL);
232 nlm_write_pic_reg(base, PIC_CTRL, control | val);
236 nlm_pic_ack(uint64_t base, int irt_num)
238 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
240 /* Ack the Status register for Watchdog & System timers */
242 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
246 nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
250 val = nlm_read_pic_reg(base, PIC_IRT(irt));
254 nlm_write_pic_reg(base, PIC_IRT(irt), val);
258 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
259 int sch, int vec, int dt, int db, int dte)
263 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
264 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
265 ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
268 nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
272 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
273 int sch, int vec, int cpu)
275 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
276 (cpu >> 4), /* thread group */
277 1 << (cpu & 0xf)); /* thread mask */
280 static inline uint64_t
281 nlm_pic_read_timer(uint64_t base, int timer)
283 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
287 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
289 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
293 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
305 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
306 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
307 en, nmi, 0, irq, cpu);
309 /* enable the timer */
310 pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
311 pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
312 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
315 #endif /* __ASSEMBLY__ */
316 #endif /* _NLM_HAL_PIC_H */