2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
32 #include <machine/asm.h>
33 #include <machine/cpu.h>
34 #include <machine/cpuregs.h>
35 #include <mips/nlm/hal/iomap.h>
36 #include <mips/nlm/hal/sys.h>
37 #include <mips/nlm/hal/cpucontrol.h>
39 #define SYS_REG_KSEG1(node, reg) (0xa0000000 + XLP_DEFAULT_IO_BASE + \
40 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + (reg) * 4)
48 VECTOR(XLPResetEntry, unknown)
49 mfc0 t0, MIPS_COP_0_STATUS
56 /* Reset entry for secordary cores */
57 mfc0 t0, MIPS_COP_0_PRID, 1
58 srl t0, t0, 2 /* discard thread id */
59 andi t0, t0, 0x7 /* core id */
62 nor t0, t0, zero /* mask with core id bit clear */
64 /* clear CPU non-coherent bit */
65 li t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE)
69 lw t1, 0(t2) /* read-back ensures operation complete */
78 VECTOR_END(XLPResetEntry)
89 * Enable other threads in the core, called from thread 0
92 LEAF(xlp_enable_threads)
94 * Save and restore callee saved registers of all ABIs
95 * Enabling threads trashes the registers
97 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
99 xori sp, sp, 0x7 /* align 64 bit */
101 mfc0 t1, MIPS_COP_0_STATUS
114 /* Use register number to work in o32 and n32 */
115 li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
118 .word 0x71280019 /* mtcr t0, t1*/
119 mfc0 t0, MIPS_COP_0_PRID, 1
123 dla t1, mpentry /* child thread, go to hardware init */
129 * Parent hardware thread, restore registers, return
133 * A0 Errata - Write MMU_SETUP after changing thread mode register.
137 .word 0x71280019 /* mtcr $8, $9*/
138 .word 0x000000c0 /* ehb */
140 dmfc0 t0, $4, 2 /* SP saved in UserLocal */
142 xori sp, sp, 0x7 /* align 64 bit */
156 mfc0 t1, MIPS_COP_0_STATUS
158 move sp, t0 /* Restore the real SP */
161 END(xlp_enable_threads)