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30 /* MDIO Low level Access routines */
31 /* All Phy's accessed from GMAC0 base */
33 #ifndef _XGMAC_MDIO_H_
34 #define _XGMAC_MDIO_H_
37 xmdio_read(volatile unsigned int *_mmio,
38 uint32_t phy_addr, uint32_t address);
40 xmdio_write(volatile unsigned int *_mmio,
41 uint32_t phy_addr, uint32_t address, uint32_t data);
43 xmdio_address(volatile unsigned int *_mmio,
44 uint32_t phy_addr, uint32_t dev_ad, uint32_t address);
47 xmdio_address(volatile unsigned int *_mmio,
48 uint32_t phy_addr, uint32_t dev_ad, uint32_t address)
50 uint32_t st_field = 0x0;
51 uint32_t op_type = 0x0; /* address operation */
52 uint32_t ta_field = 0x2;/* ta field */
54 _mmio[0x11] = ((st_field & 0x3) << 30) |
55 ((op_type & 0x3) << 28) |
56 ((phy_addr & 0x1F) << 23) |
57 ((dev_ad & 0x1F) << 18) |
58 ((ta_field & 0x3) << 16) |
59 ((address & 0xffff) << 0);
61 _mmio[0x10] = (0x0 << 3) | 0x5;
62 _mmio[0x10] = (0x1 << 3) | 0x5;
63 _mmio[0x10] = (0x0 << 3) | 0x5;
65 /* wait for dev_ad cycle to complete */
66 while (_mmio[0x14] & 0x1) {
71 /* function prototypes */
73 xmdio_read(volatile unsigned int *_mmio,
74 uint32_t phy_addr, uint32_t address)
76 uint32_t st_field = 0x0;
77 uint32_t op_type = 0x3; /* read operation */
78 uint32_t ta_field = 0x2;/* ta field */
81 xmdio_address(_mmio, phy_addr, 5, address);
82 _mmio[0x11] = ((st_field & 0x3) << 30) |
83 ((op_type & 0x3) << 28) |
84 ((phy_addr & 0x1F) << 23) |
86 ((ta_field & 0x3) << 16) |
87 ((data & 0xffff) << 0);
89 _mmio[0x10] = (0x0 << 3) | 0x5;
90 _mmio[0x10] = (0x1 << 3) | 0x5;
91 _mmio[0x10] = (0x0 << 3) | 0x5;
93 /* wait for write cycle to complete */
94 while (_mmio[0x14] & 0x1) {
97 data = _mmio[0x11] & 0xffff;
102 xmdio_write(volatile unsigned int *_mmio,
103 uint32_t phy_addr, uint32_t address, uint32_t data)
105 uint32_t st_field = 0x0;
106 uint32_t op_type = 0x1; /* write operation */
107 uint32_t ta_field = 0x2;/* ta field */
109 xmdio_address(_mmio, phy_addr, 5, address);
110 _mmio[0x11] = ((st_field & 0x3) << 30) |
111 ((op_type & 0x3) << 28) |
112 ((phy_addr & 0x1F) << 23) |
114 ((ta_field & 0x3) << 16) |
115 ((data & 0xffff) << 0);
117 _mmio[0x10] = (0x0 << 3) | 0x5;
118 _mmio[0x10] = (0x1 << 3) | 0x5;
119 _mmio[0x10] = (0x0 << 3) | 0x5;
121 /* wait for write cycle to complete */
122 while (_mmio[0x14] & 0x1) {