1 /*********************************************************************
3 * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
17 * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
29 * *****************************RMI_2**********************************/
33 * This file defines the message ring configuration for XLS two core. It tries to allow
34 * many different point-point communications between the message stations on the message ring
35 * and as result is _not_ the best configuration for performance
37 * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
38 * security engine and the general purpose DMA engines. It provides a high bandwidth,
39 * low latency communication links. On traditional processors, this communication goes through
40 * which inherently does not scale very well with increasing number of cpus.
42 * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
43 * have software configured credits to send messages to any agent. Every receiving agent on the
44 * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
45 * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
46 * across all sending agents should not exceed the bucket size.
48 * Below are the receiving agents and the max number of buckets they can have
58 * CMP : Currently disabled.
60 * The bucket size of a bucket should be aligned to the bucket's starting index in that
61 * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
62 * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
64 * The format of the file is pretty straight forward. Each bucket definition has the size
65 * and the list of sending agents to that bucket with the number of credits to send.
67 * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
69 * Following are the currently supported bucket names
88 * enabled only for xls-b0
98 * enabled only for xls-b0
123 * Following are the currently supported Tx Agent/Station names
138 /*************************************************************/
139 // CPU_0 Message Station
149 "tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */
204 /*************************************************************/
205 // CPU_1 Message Station
236 "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
269 /*************************************************************/
270 // CPU_2 Message Station
301 "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
335 /*************************************************************/
336 // CPU_3 Message Station
366 "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
399 /*************************************************************/
401 // GMAC Message Station
413 bucket "gmac0_tx_0" {
421 bucket "gmac0_tx_1" {
429 bucket "gmac0_tx_2" {
437 bucket "gmac0_tx_3" {
455 bucket "gmac1_tx_0" {
463 bucket "gmac1_tx_1" {
471 bucket "gmac1_tx_2" {
479 bucket "gmac1_tx_3" {
487 /*************************************************************/
488 // Security Message Station
490 bucket "sec_pipe_0" {
498 bucket "sec_rsa_ecc" {
506 bucket "dma_rsvd_0" {
513 bucket "dma_rsvd_1" {
521 bucket "dma_rsvd_2" {
529 bucket "dma_rsvd_3" {
537 /*************************************************************/
538 // Compression Message Station