1 /* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
4 * Copyright (c) 2010 Aleksandr Rybalko.
5 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
6 * Copyright (c) 2007 Oleksandr Tymoshenko.
9 * Redistribution and use in source and binary forms, with or
10 * without modification, are permitted provided that the following
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer in the documentation and/or other materials provided
17 * with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
26 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
28 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
29 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
43 #include <sys/reboot.h>
44 #include <sys/sysctl.h>
45 #include <sys/kernel.h>
46 #include <machine/bus.h>
48 #include <dev/uart/uart.h>
49 #include <dev/uart/uart_cpu.h>
50 #include <dev/uart/uart_bus.h>
52 #include <mips/rt305x/uart_dev_rt305x.h>
53 #include <mips/rt305x/rt305xreg.h>
57 * Low-level UART interface.
59 static int rt305x_uart_probe(struct uart_bas *bas);
60 static void rt305x_uart_init(struct uart_bas *bas, int, int, int, int);
61 static void rt305x_uart_term(struct uart_bas *bas);
62 static void rt305x_uart_putc(struct uart_bas *bas, int);
63 static int rt305x_uart_rxready(struct uart_bas *bas);
64 static int rt305x_uart_getc(struct uart_bas *bas, struct mtx *);
66 static struct uart_ops uart_rt305x_uart_ops = {
67 .probe = rt305x_uart_probe,
68 .init = rt305x_uart_init,
69 .term = rt305x_uart_term,
70 .putc = rt305x_uart_putc,
71 .rxready = rt305x_uart_rxready,
72 .getc = rt305x_uart_getc,
75 static int uart_output = 1;
76 TUNABLE_INT("kern.uart_output", &uart_output);
77 SYSCTL_INT(_kern, OID_AUTO, uart_output, CTLFLAG_RW,
78 &uart_output, 0, "UART output enabled.");
84 rt305x_uart_probe(struct uart_bas *bas)
91 rt305x_uart_init(struct uart_bas *bas, int baudrate, int databits,
92 int stopbits, int parity)
95 /* CLKDIV = 384000000/ 3/ 16/ br */
96 /* for 384MHz CLKDIV = 8000000 / baudrate; */
99 databits = UART_LCR_5B;
102 databits = UART_LCR_6B;
105 databits = UART_LCR_7B;
108 databits = UART_LCR_8B;
115 case UART_PARITY_EVEN: parity = (UART_LCR_PEN|UART_LCR_EVEN); break;
116 case UART_PARITY_NONE: parity = (UART_LCR_PEN); break;
117 case UART_PARITY_ODD: parity = 0; break;
121 uart_setreg(bas, UART_CDDL_REG, 8000000/baudrate);
123 uart_setreg(bas, UART_LCR_REG, databits | (stopbits==1?0:4) | parity);
129 rt305x_uart_term(struct uart_bas *bas)
131 uart_setreg(bas, UART_MCR_REG, 0);
136 rt305x_uart_putc(struct uart_bas *bas, int c)
139 if (!uart_output) return;
141 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
142 uart_setreg(bas, UART_TX_REG, c);
144 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE));
148 rt305x_uart_rxready(struct uart_bas *bas)
151 if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)
161 rt305x_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
167 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) {
173 c = uart_getreg(bas, UART_RX_REG);
181 * High-level UART interface.
183 struct rt305x_uart_softc {
184 struct uart_softc base;
187 static int rt305x_uart_bus_attach(struct uart_softc *);
188 static int rt305x_uart_bus_detach(struct uart_softc *);
189 static int rt305x_uart_bus_flush(struct uart_softc *, int);
190 static int rt305x_uart_bus_getsig(struct uart_softc *);
191 static int rt305x_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
192 static int rt305x_uart_bus_ipend(struct uart_softc *);
193 static int rt305x_uart_bus_param(struct uart_softc *, int, int, int, int);
194 static int rt305x_uart_bus_probe(struct uart_softc *);
195 static int rt305x_uart_bus_receive(struct uart_softc *);
196 static int rt305x_uart_bus_setsig(struct uart_softc *, int);
197 static int rt305x_uart_bus_transmit(struct uart_softc *);
199 static kobj_method_t rt305x_uart_methods[] = {
200 KOBJMETHOD(uart_attach, rt305x_uart_bus_attach),
201 KOBJMETHOD(uart_detach, rt305x_uart_bus_detach),
202 KOBJMETHOD(uart_flush, rt305x_uart_bus_flush),
203 KOBJMETHOD(uart_getsig, rt305x_uart_bus_getsig),
204 KOBJMETHOD(uart_ioctl, rt305x_uart_bus_ioctl),
205 KOBJMETHOD(uart_ipend, rt305x_uart_bus_ipend),
206 KOBJMETHOD(uart_param, rt305x_uart_bus_param),
207 KOBJMETHOD(uart_probe, rt305x_uart_bus_probe),
208 KOBJMETHOD(uart_receive, rt305x_uart_bus_receive),
209 KOBJMETHOD(uart_setsig, rt305x_uart_bus_setsig),
210 KOBJMETHOD(uart_transmit, rt305x_uart_bus_transmit),
214 struct uart_class uart_rt305x_uart_class = {
217 sizeof(struct rt305x_uart_softc),
218 .uc_ops = &uart_rt305x_uart_ops,
219 .uc_range = 1, /* use hinted range */
220 .uc_rclk = SYSTEM_CLOCK
223 #define SIGCHG(c, i, s, d) \
225 i |= (i & s) ? s : s | d; \
227 i = (i & s) ? (i & ~s) | d : i; \
231 * Disable TX interrupt. uart should be locked
234 rt305x_uart_disable_txintr(struct uart_softc *sc)
236 struct uart_bas *bas = &sc->sc_bas;
239 cr = uart_getreg(bas, UART_IER_REG);
240 cr &= ~UART_IER_ETBEI;
241 uart_setreg(bas, UART_IER_REG, cr);
246 * Enable TX interrupt. uart should be locked
249 rt305x_uart_enable_txintr(struct uart_softc *sc)
251 struct uart_bas *bas = &sc->sc_bas;
254 cr = uart_getreg(bas, UART_IER_REG);
255 cr |= UART_IER_ETBEI;
256 uart_setreg(bas, UART_IER_REG, cr);
261 rt305x_uart_bus_attach(struct uart_softc *sc)
263 struct uart_bas *bas;
264 struct uart_devinfo *di;
267 if (sc->sc_sysdev != NULL) {
269 rt305x_uart_init(bas, di->baudrate, di->databits, di->stopbits,
272 rt305x_uart_init(bas, 115200, 8, 1, 0);
275 sc->sc_rxfifosz = 16;
276 sc->sc_txfifosz = 16;
278 (void)rt305x_uart_bus_getsig(sc);
281 uart_setreg(bas, UART_FCR_REG,
282 uart_getreg(bas, UART_FCR_REG) |
283 UART_FCR_FIFOEN | UART_FCR_TXTGR_1 | UART_FCR_RXTGR_1);
285 /* Enable interrupts */
286 uart_setreg(bas, UART_IER_REG,
287 UART_IER_EDSSI | UART_IER_ELSI | UART_IER_ERBFI);
294 rt305x_uart_bus_detach(struct uart_softc *sc)
301 rt305x_uart_bus_flush(struct uart_softc *sc, int what)
303 struct uart_bas *bas = &sc->sc_bas;
304 uint32_t fcr = uart_getreg(bas, UART_FCR_REG);
305 if (what & UART_FLUSH_TRANSMITTER) {
306 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_TXRST);
309 if (what & UART_FLUSH_RECEIVER) {
310 uart_setreg(bas, UART_FCR_REG, fcr|UART_FCR_RXRST);
313 uart_setreg(bas, UART_FCR_REG, fcr);
319 rt305x_uart_bus_getsig(struct uart_softc *sc)
321 uint32_t new, old, sig;
327 uart_lock(sc->sc_hwmtx);
328 bes = uart_getreg(&sc->sc_bas, UART_MSR_REG);
329 uart_unlock(sc->sc_hwmtx);
330 /* XXX: chip can show delta */
331 SIGCHG(bes & UART_MSR_CTS, sig, SER_CTS, SER_DCTS);
332 SIGCHG(bes & UART_MSR_DCD, sig, SER_DCD, SER_DDCD);
333 SIGCHG(bes & UART_MSR_DSR, sig, SER_DSR, SER_DDSR);
334 new = sig & ~SER_MASK_DELTA;
335 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
341 rt305x_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
343 struct uart_bas *bas;
344 int baudrate, divisor, error;
348 uart_lock(sc->sc_hwmtx);
350 case UART_IOCTL_BREAK:
351 /* TODO: Send BREAK */
353 case UART_IOCTL_BAUD:
354 divisor = uart_getreg(bas, UART_CDDL_REG);
355 baudrate = bas->rclk / (divisor * 16);
356 *(int*)data = baudrate;
362 uart_unlock(sc->sc_hwmtx);
367 rt305x_uart_bus_ipend(struct uart_softc *sc)
369 struct uart_bas *bas;
371 uint8_t iir, lsr, msr;
376 uart_lock(sc->sc_hwmtx);
377 iir = uart_getreg(&sc->sc_bas, UART_IIR_REG);
378 lsr = uart_getreg(&sc->sc_bas, UART_LSR_REG);
379 uart_setreg(&sc->sc_bas, UART_LSR_REG, lsr);
380 msr = uart_getreg(&sc->sc_bas, UART_MSR_REG);
381 uart_setreg(&sc->sc_bas, UART_MSR_REG, msr);
382 if (iir & UART_IIR_INTP) {
383 uart_unlock(sc->sc_hwmtx);
388 switch ((iir >> 1) & 0x07) {
389 case UART_IIR_ID_THRE:
390 ipend |= SER_INT_TXIDLE;
392 case UART_IIR_ID_DR2:
393 rt305x_uart_bus_flush(sc, UART_FLUSH_RECEIVER);
396 ipend |= SER_INT_RXREADY;
398 case UART_IIR_ID_MST:
399 case UART_IIR_ID_LINESTATUS:
400 ipend |= SER_INT_SIGCHG;
401 if (lsr & UART_LSR_BI)
403 ipend |= SER_INT_BREAK;
408 if (lsr & UART_LSR_OE)
409 ipend |= SER_INT_OVERRUN;
412 /* XXX: maybe return error here */
416 uart_unlock(sc->sc_hwmtx);
422 rt305x_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
423 int stopbits, int parity)
425 uart_lock(sc->sc_hwmtx);
426 rt305x_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);
427 uart_unlock(sc->sc_hwmtx);
432 rt305x_uart_bus_probe(struct uart_softc *sc)
437 error = rt305x_uart_probe(&sc->sc_bas);
441 snprintf(buf, sizeof(buf), "rt305x_uart");
442 device_set_desc_copy(sc->sc_dev, buf);
448 rt305x_uart_bus_receive(struct uart_softc *sc)
450 struct uart_bas *bas;
455 uart_lock(sc->sc_hwmtx);
456 lsr = uart_getreg(bas, UART_LSR_REG);
457 while ((lsr & UART_LSR_DR)) {
458 if (uart_rx_full(sc)) {
459 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
463 xc = uart_getreg(bas, UART_RX_REG);
464 if (lsr & UART_LSR_FE)
465 xc |= UART_STAT_FRAMERR;
466 if (lsr & UART_LSR_PE)
467 xc |= UART_STAT_PARERR;
468 if (lsr & UART_LSR_OE)
469 xc |= UART_STAT_OVERRUN;
472 lsr = uart_getreg(bas, UART_LSR_REG);
475 uart_unlock(sc->sc_hwmtx);
480 rt305x_uart_bus_setsig(struct uart_softc *sc, int sig)
483 /* TODO: implement (?) */
488 rt305x_uart_bus_transmit(struct uart_softc *sc)
490 struct uart_bas *bas = &sc->sc_bas;
493 if (!uart_output) return (0);
496 uart_lock(sc->sc_hwmtx);
497 while ((uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE) == 0)
499 rt305x_uart_enable_txintr(sc);
500 for (i = 0; i < sc->sc_txdatasz; i++) {
501 uart_setreg(bas, UART_TX_REG, sc->sc_txbuf[i]);
505 uart_unlock(sc->sc_hwmtx);