2 * Copyright (c) 2007 Bruce M. Simpson.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/systm.h>
37 #include <sys/imgact.h>
44 #include <sys/ucontext.h>
47 #include <sys/ptrace.h>
48 #include <sys/reboot.h>
49 #include <sys/signalvar.h>
50 #include <sys/sysent.h>
51 #include <sys/sysproto.h>
53 #include <sys/timetc.h>
56 #include <vm/vm_object.h>
57 #include <vm/vm_page.h>
58 #include <vm/vm_pager.h>
60 #include <machine/cache.h>
61 #include <machine/clock.h>
62 #include <machine/cpu.h>
63 #include <machine/cpuinfo.h>
64 #include <machine/cpufunc.h>
65 #include <machine/cpuregs.h>
66 #include <machine/hwfunc.h>
67 #include <machine/intr_machdep.h>
68 #include <machine/locore.h>
69 #include <machine/md_var.h>
70 #include <machine/pte.h>
71 #include <machine/sigframe.h>
72 #include <machine/trap.h>
73 #include <machine/vmparam.h>
77 #include <machine/smp.h>
81 #include <dev/cfe/cfe_api.h>
88 #error KDB must be enabled in order for DDB to work!
93 extern void cfe_env_init(void);
99 extern char MipsTLBMiss[], MipsTLBMissEnd[];
104 /* Nothing special */
108 sb_intr_init(int cpuid)
113 * Disable all sources to the interrupt mapper and setup the mapping
114 * between an interrupt source and the mips hard interrupt number.
116 for (intsrc = 0; intsrc < NUM_INTSRC; ++intsrc) {
117 intrnum = sb_route_intsrc(intsrc);
118 sb_disable_intsrc(cpuid, intsrc);
119 sb_write_intmap(cpuid, intsrc, intrnum);
122 * Set up the mailbox interrupt mapping.
124 * The mailbox interrupt is "special" in that it is not shared
125 * with any other interrupt source.
127 if (intsrc == INTSRC_MAILBOX3) {
128 intrnum = platform_ipi_intrnum();
129 sb_write_intmap(cpuid, INTSRC_MAILBOX3, intrnum);
130 sb_enable_intsrc(cpuid, INTSRC_MAILBOX3);
139 int i, j, cfe_mem_idx, tmp;
146 TUNABLE_INT_FETCH("boothowto", &boothowto);
148 if (boothowto & RB_VERBOSE)
156 TUNABLE_INT_FETCH("hw.physmem", &tmp);
157 maxmem = (uint64_t)tmp * 1024;
161 * If we used vm_paddr_t consistently in pmap, etc., we could
162 * use 64-bit page numbers on !n64 systems, too, like i386
165 #if !defined(__mips_n64)
166 if (maxmem == 0 || maxmem > 0xffffffff)
172 * Query DRAM memory map from CFE.
176 for (i = 0; i < 10; i += 2) {
178 uint64_t addr, len, type;
180 result = cfe_enummem(cfe_mem_idx++, 0, &addr, &len, &type);
182 phys_avail[i] = phys_avail[i + 1] = 0;
186 KASSERT(type == CFE_MI_AVAILABLE,
187 ("CFE DRAM region is not available?"));
190 printf("cfe_enummem: 0x%016jx/%ju.\n", addr, len);
193 if (addr >= maxmem) {
194 printf("Ignoring %ju bytes of memory at 0x%jx "
195 "that is above maxmem %dMB\n",
197 (int)(maxmem / (1024 * 1024)));
201 if (addr + len > maxmem) {
202 printf("Ignoring %ju bytes of memory "
203 "that is above maxmem %dMB\n",
204 (addr + len) - maxmem,
205 (int)(maxmem / (1024 * 1024)));
210 phys_avail[i] = addr;
211 if (i == 0 && addr == 0) {
213 * If this is the first physical memory segment probed
214 * from CFE, omit the region at the start of physical
215 * memory where the kernel has been loaded.
217 phys_avail[i] += MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
219 phys_avail[i + 1] = addr + len;
223 realmem = btoc(physmem);
226 for (j = 0; j < i; j++)
227 dump_avail[j] = phys_avail[j];
232 init_param2(physmem);
236 * Sibyte has a L1 data cache coherent with DMA. This includes
237 * on-chip network interfaces as well as PCI/HyperTransport bus
240 cpuinfo.cache_coherent_dma = TRUE;
244 * The kernel is running in 32-bit mode but the CFE is running in
245 * 64-bit mode. So the SR_KX bit in the status register is turned
246 * on by the CFE every time we call into it - for e.g. CFE_CONSOLE.
248 * This means that if get a TLB miss for any address above 0xc0000000
249 * and the SR_KX bit is set then we will end up in the XTLB exception
252 * For now work around this by copying the TLB exception handling
253 * code to the XTLB exception vector.
256 bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC,
257 MipsTLBMissEnd - MipsTLBMiss);
259 mips_icache_sync_all();
260 mips_dcache_wbinv_all();
269 if (boothowto & RB_KDB)
270 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
282 platform_identify(void)
293 * XXX flush data caches
299 platform_trap_enter(void)
305 platform_trap_exit(void)
311 kseg0_map_coherent(void)
314 const int CFG_K0_COHERENT = 5;
316 config = mips_rd_config();
317 config &= ~MIPS3_CONFIG_K0_MASK;
318 config |= CFG_K0_COHERENT;
319 mips_wr_config(config);
324 platform_ipi_send(int cpuid)
326 KASSERT(cpuid == 0 || cpuid == 1,
327 ("platform_ipi_send: invalid cpuid %d", cpuid));
329 sb_set_mailbox(cpuid, 1ULL);
333 platform_ipi_clear(void)
337 cpuid = PCPU_GET(cpuid);
338 sb_clear_mailbox(cpuid, 1ULL);
342 platform_ipi_intrnum(void)
349 platform_smp_topo(void)
352 return (smp_topo_none());
356 platform_init_ap(int cpuid)
358 int ipi_int_mask, clock_int_mask;
360 KASSERT(cpuid == 1, ("AP has an invalid cpu id %d", cpuid));
363 * Make sure that kseg0 is mapped cacheable-coherent
365 kseg0_map_coherent();
370 * Unmask the clock and ipi interrupts.
372 clock_int_mask = hard_int_mask(5);
373 ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
374 set_intr_mask(ipi_int_mask | clock_int_mask);
378 platform_start_ap(int cpuid)
383 if ((error = cfe_cpu_start(cpuid, mpentry, 0, 0, 0))) {
384 printf("cfe_cpu_start error: %d\n", error);
396 sb_get_timecount(struct timecounter *tc)
399 return ((u_int)sb_zbbus_cycle_count());
403 sb_timecounter_init(void)
405 static struct timecounter sb_timecounter = {
410 "sibyte_zbbus_counter",
415 * The ZBbus cycle counter runs at half the cpu frequency.
417 sb_timecounter.tc_frequency = sb_cpu_speed() / 2;
418 platform_timecounter = &sb_timecounter;
422 platform_start(__register_t a0, __register_t a1, __register_t a2,
426 * Make sure that kseg0 is mapped cacheable-coherent
428 kseg0_map_coherent();
430 /* clear the BSS and SBSS segments */
431 memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata);
432 mips_postboot_fixup();
435 sb_timecounter_init();
437 /* Initialize pcpu stuff */
442 * Initialize CFE firmware trampolines before
443 * we initialize the low-level console.
445 * CFE passes the following values in registers:
446 * a0: firmware handle
447 * a2: firmware entry point
448 * a3: entry point seal
450 if (a3 == CFE_EPTSEAL)
457 mips_timer_init_params(sb_cpu_speed(), 0);