2 * Copyright (c) 2009 Neelkanth Natu
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/systm.h>
33 #include <sys/module.h>
35 #include <sys/cpuset.h>
37 #include <machine/resource.h>
38 #include <machine/hwfunc.h>
43 * We compile a 32-bit kernel to run on the SB-1 processor which is a 64-bit
44 * processor. It has some registers that must be accessed using 64-bit load
45 * and store instructions.
47 * We use the mips_ld() and mips_sd() functions to do this for us.
49 #define sb_store64(addr, val) mips3_sd((uint64_t *)(uintptr_t)(addr), (val))
50 #define sb_load64(addr) mips3_ld((uint64_t *)(uintptr_t)(addr))
53 * System Control and Debug (SCD) unit on the Sibyte ZBbus.
57 * Extract the value starting at bit position 'b' for 'n' bits from 'x'.
59 #define GET_VAL_64(x, b, n) (((x) >> (b)) & ((1ULL << (n)) - 1))
61 #define SYSREV_ADDR MIPS_PHYS_TO_KSEG1(0x10020000)
62 #define SYSREV_NUM_PROCESSORS(x) GET_VAL_64((x), 24, 4)
64 #define SYSCFG_ADDR MIPS_PHYS_TO_KSEG1(0x10020008)
65 #define SYSCFG_PLLDIV(x) GET_VAL_64((x), 7, 5)
67 #define ZBBUS_CYCLE_COUNT_ADDR MIPS_PHYS_TO_KSEG1(0x10030000)
69 #define INTSRC_MASK_ADDR(cpu) \
70 (MIPS_PHYS_TO_KSEG1(0x10020028) | ((cpu) << 13))
72 #define INTSRC_MAP_ADDR(cpu, intsrc) \
73 (MIPS_PHYS_TO_KSEG1(0x10020200) | ((cpu) << 13)) + (intsrc * 8)
75 #define MAILBOX_SET_ADDR(cpu) \
76 (MIPS_PHYS_TO_KSEG1(0x100200C8) | ((cpu) << 13))
78 #define MAILBOX_CLEAR_ADDR(cpu) \
79 (MIPS_PHYS_TO_KSEG1(0x100200D0) | ((cpu) << 13))
85 return (sb_load64(SYSCFG_ADDR));
89 sb_write_syscfg(uint64_t val)
92 sb_store64(SYSCFG_ADDR, val);
96 sb_zbbus_cycle_count(void)
99 return (sb_load64(ZBBUS_CYCLE_COUNT_ADDR));
106 const uint64_t MHZ = 1000000;
108 plldiv = SYSCFG_PLLDIV(sb_read_syscfg());
110 printf("PLL_DIV is 0 - assuming 6 (300MHz).\n");
114 return (plldiv * 50 * MHZ);
118 sb_system_reset(void)
122 const uint64_t SYSTEM_RESET = 1ULL << 60;
123 const uint64_t EXT_RESET = 1ULL << 59;
124 const uint64_t SOFT_RESET = 1ULL << 58;
126 syscfg = sb_read_syscfg();
127 syscfg &= ~SOFT_RESET;
128 syscfg |= SYSTEM_RESET | EXT_RESET;
129 sb_write_syscfg(syscfg);
133 sb_disable_intsrc(int cpu, int src)
138 regaddr = INTSRC_MASK_ADDR(cpu);
140 val = sb_load64(regaddr);
142 sb_store64(regaddr, val);
146 sb_enable_intsrc(int cpu, int src)
151 regaddr = INTSRC_MASK_ADDR(cpu);
153 val = sb_load64(regaddr);
154 val &= ~(1ULL << src);
155 sb_store64(regaddr, val);
159 sb_write_intsrc_mask(int cpu, uint64_t val)
163 regaddr = INTSRC_MASK_ADDR(cpu);
164 sb_store64(regaddr, val);
168 sb_read_intsrc_mask(int cpu)
173 regaddr = INTSRC_MASK_ADDR(cpu);
174 val = sb_load64(regaddr);
180 sb_write_intmap(int cpu, int intsrc, int intrnum)
184 regaddr = INTSRC_MAP_ADDR(cpu, intsrc);
185 sb_store64(regaddr, intrnum);
189 sb_read_intmap(int cpu, int intsrc)
193 regaddr = INTSRC_MAP_ADDR(cpu, intsrc);
194 return (sb_load64(regaddr) & 0x7);
198 sb_route_intsrc(int intsrc)
202 KASSERT(intsrc >= 0 && intsrc < NUM_INTSRC,
203 ("Invalid interrupt source number (%d)", intsrc));
206 * Interrupt 5 is used by sources internal to the CPU (e.g. timer).
207 * Use a deterministic mapping for the remaining sources.
210 KASSERT(platform_ipi_intrnum() == 4,
211 ("Unexpected interrupt number used for IPI"));
212 intrnum = intsrc % 4;
214 intrnum = intsrc % 5;
225 return (sb_load64(SYSREV_ADDR));
229 sb_set_mailbox(int cpu, uint64_t val)
233 regaddr = MAILBOX_SET_ADDR(cpu);
234 sb_store64(regaddr, val);
238 sb_clear_mailbox(int cpu, uint64_t val)
242 regaddr = MAILBOX_CLEAR_ADDR(cpu);
243 sb_store64(regaddr, val);
247 platform_cpu_mask(cpuset_t *mask)
252 s = SYSREV_NUM_PROCESSORS(sb_read_sysrev());
253 for (i = 0; i < s; i++)
258 #define SCD_PHYSADDR 0x10000000
259 #define SCD_SIZE 0x00060000
262 scd_probe(device_t dev)
265 device_set_desc(dev, "Broadcom/Sibyte System Control and Debug");
270 scd_attach(device_t dev)
273 struct resource *res;
276 device_printf(dev, "attached.\n");
279 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, SCD_PHYSADDR,
280 SCD_PHYSADDR + SCD_SIZE - 1, SCD_SIZE, 0);
282 panic("Cannot allocate resource for system control and debug.");
287 static device_method_t scd_methods[] ={
288 /* Device interface */
289 DEVMETHOD(device_probe, scd_probe),
290 DEVMETHOD(device_attach, scd_attach),
291 DEVMETHOD(device_detach, bus_generic_detach),
292 DEVMETHOD(device_shutdown, bus_generic_shutdown),
293 DEVMETHOD(device_suspend, bus_generic_suspend),
294 DEVMETHOD(device_resume, bus_generic_resume),
299 static driver_t scd_driver = {
304 static devclass_t scd_devclass;
306 DRIVER_MODULE(scd, zbbus, scd_driver, scd_devclass, 0, 0);