2 * Copyright (c) 2013 George V. Neville-Neil
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * The following set of constants are from Document SFF-8472
31 * "Diagnostic Monitoring Interface for Optical Transceivers" revision
32 * 11.3 published by the SFF Committee on June 11, 2013
34 * The SFF standard defines two ranges of addresses, each 255 bytes
35 * long for the storage of data and diagnostics on cables, such as
36 * SFP+ optics and TwinAx cables. The ranges are defined in the
39 * Base Address 0xa0 (Identification Data)
40 * 0-95 Serial ID Defined by SFP MSA
41 * 96-127 Vendor Specific Data
44 * Base Address 0xa2 (Diagnostic Data)
45 * 0-55 Alarm and Warning Thresholds
47 * 96-119 Real Time Diagnostic Interface
48 * 120-127 Vendor Specific
49 * 128-247 User Writable EEPROM
50 * 248-255 Vendor Specific
52 * Note that not all addresses are supported. Where support is
53 * optional this is noted and instructions for checking for the
54 * support are supplied.
56 * All these values are read across an I2C (i squared C) bus. Any
57 * device wishing to read these addresses must first have support for
58 * i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such
63 /* Table 3.1 Two-wire interface ID: Data Fields */
65 #define SFF_8472_BASE 0xa0 /* Base address for all our queries. */
66 #define SFF_8472_ID 0 /* Transceiver Type (Table 3.2) */
67 #define SFF_8472_EXT_ID 1 /* Extended transceiver type (Table 3.3) */
68 #define SFF_8472_CONNECTOR 2 /* Connector type (Table 3.4) */
69 #define SFF_8472_TRANS_START 3 /* Elec or Optical Compatibility
71 #define SFF_8472_TRANS_END 10
72 #define SFF_8472_ENCODING 11 /* Encoding Code for high speed
73 * serial encoding algorithm (see
75 #define SFF_8472_BITRATE 12 /* Nominal signaling rate, units
76 * of 100MBd. (see details for
77 * rates > 25.0Gb/s) */
78 #define SFF_8472_RATEID 13 /* Type of rate select
79 * functionality (see Table
81 #define SFF_8472_LEN_SMF_KM 14 /* Link length supported for single
82 * mode fiber, units of km */
83 #define SFF_8472_LEN_SMF 15 /* Link length supported for single
84 * mode fiber, units of 100 m */
85 #define SFF_8472_LEN_50UM 16 /* Link length supported for 50 um
86 * OM2 fiber, units of 10 m */
87 #define SFF_8472_LEN_625UM 17 /* Link length supported for 62.5
88 * um OM1 fiber, units of 10 m */
89 #define SFF_8472_LEN_OM4 18 /* Link length supported for 50um
90 * OM4 fiber, units of 10m.
91 * Alternatively copper or direct
92 * attach cable, units of m */
93 #define SFF_8472_LEN_OM3 19 /* Link length supported for 50 um OM3 fiber, units of 10 m */
94 #define SFF_8472_VENDOR_START 20 /* Vendor name [Address A0h, Bytes
96 #define SFF_8472_VENDOR_END 35
97 #define SFF_8472_TRANS 36 /* Transceiver Code for electronic
98 * or optical compatibility (see
100 #define SFF_8472_VENDOR_OUI_START 37 /* Vendor OUI SFP vendor IEEE
102 #define SFF_8472_VENDOR_OUI_END 39
103 #define SFF_8472_PN_START 40 /* Vendor PN */
104 #define SFF_8472_PN_END 55
105 #define SFF_8472_REV_START 56 /* Vendor Revision */
106 #define SFF_8472_REV_END 59
107 #define SFF_8472_WAVELEN_START 60 /* Wavelength Laser wavelength
108 * (Passive/Active Cable
109 * Specification Compliance) */
110 #define SFF_8472_WAVELEN_END 61
111 #define SFF_8472_CC_BASE 63 /* CC_BASE Check code for Base ID
112 * Fields (addresses 0 to 62) */
115 * Extension Fields (optional) check the options before reading other
118 #define SFF_8472_OPTIONS_MSB 64 /* Options Indicates which optional
119 * transceiver signals are
121 #define SFF_8472_OPTIONS_LSB 65 /* (see Table 3.7) */
122 #define SFF_8472_BR_MAX 66 /* BR max Upper bit rate margin,
123 * units of % (see details for
124 * rates > 25.0Gb/s) */
125 #define SFF_8472_BR_MIN 67 /* Lower bit rate margin, units of
126 * % (see details for rates >
128 #define SFF_8472_SN_START 68 /* Vendor SN [Address A0h, Bytes 68-83] */
129 #define SFF_8472_SN_END 83
130 #define SFF_8472_DATE_START 84 /* Date code Vendor’s manufacturing
131 * date code (see Table 3.8) */
132 #define SFF_8472_DATE_END 91
133 #define SFF_8472_DIAG_TYPE 92 /* Diagnostic Monitoring Type
134 * Indicates which type of
135 * diagnostic monitoring is
136 * implemented (if any) in the
137 * transceiver (see Table 3.9)
139 #define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */
140 #define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */
141 #define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */
142 #define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */
143 #define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required.
144 * See SFF-8472 doc. */
146 #define SFF_8472_ENHANCED 93 /* Enhanced Options Indicates which
147 * optional enhanced features are
148 * implemented (if any) in the
149 * transceiver (see Table 3.10) */
150 #define SFF_8472_COMPLIANCE 94 /* SFF-8472 Compliance Indicates
151 * which revision of SFF-8472 the
152 * transceiver complies with. (see
154 #define SFF_8472_CC_EXT 95 /* Check code for the Extended ID
155 * Fields (addresses 64 to 94)
158 #define SFF_8472_VENDOR_RSRVD_START 96
159 #define SFF_8472_VENDOR_RSRVD_END 127
161 #define SFF_8472_RESERVED_START 128
162 #define SFF_8472_RESERVED_END 255
165 * Diagnostics are available at the two wire address 0xa2. All
166 * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to
167 * see which, if any are supported.
170 #define SFF_8472_DIAG 0xa2 /* Base address for diagnostics. */
173 * Table 3.15 Alarm and Warning Thresholds All values are 2 bytes
174 * and MUST be read in a single read operation starting at the MSB
177 #define SFF_8472_TEMP_HIGH_ALM 0 /* Temp High Alarm */
178 #define SFF_8472_TEMP_LOW_ALM 2 /* Temp Low Alarm */
179 #define SFF_8472_TEMP_HIGH_WARN 4 /* Temp High Warning */
180 #define SFF_8472_TEMP_LOW_WARN 6 /* Temp Low Warning */
181 #define SFF_8472_VOLTAGE_HIGH_ALM 8 /* Voltage High Alarm */
182 #define SFF_8472_VOLTAGE_LOW_ALM 10 /* Voltage Low Alarm */
183 #define SFF_8472_VOLTAGE_HIGH_WARN 12 /* Voltage High Warning */
184 #define SFF_8472_VOLTAGE_LOW_WARN 14 /* Voltage Low Warning */
185 #define SFF_8472_BIAS_HIGH_ALM 16 /* Bias High Alarm */
186 #define SFF_8472_BIAS_LOW_ALM 18 /* Bias Low Alarm */
187 #define SFF_8472_BIAS_HIGH_WARN 20 /* Bias High Warning */
188 #define SFF_8472_BIAS_LOW_WARN 22 /* Bias Low Warning */
189 #define SFF_8472_TX_POWER_HIGH_ALM 24 /* TX Power High Alarm */
190 #define SFF_8472_TX_POWER_LOW_ALM 26 /* TX Power Low Alarm */
191 #define SFF_8472_TX_POWER_HIGH_WARN 28 /* TX Power High Warning */
192 #define SFF_8472_TX_POWER_LOW_WARN 30 /* TX Power Low Warning */
193 #define SFF_8472_RX_POWER_HIGH_ALM 32 /* RX Power High Alarm */
194 #define SFF_8472_RX_POWER_LOW_ALM 34 /* RX Power Low Alarm */
195 #define SFF_8472_RX_POWER_HIGH_WARN 36 /* RX Power High Warning */
196 #define SFF_8472_RX_POWER_LOW_WARN 38 /* RX Power Low Warning */
198 #define SFF_8472_RX_POWER4 56 /* Rx_PWR(4) Single precision
199 * floating point calibration data
200 * - Rx optical power. Bit 7 of
201 * byte 56 is MSB. Bit 0 of byte
202 * 59 is LSB. Rx_PWR(4) should be
203 * set to zero for “internally
204 * calibrated” devices. */
205 #define SFF_8472_RX_POWER3 60 /* Rx_PWR(3) Single precision
206 * floating point calibration data
207 * - Rx optical power. Bit 7 of
208 * byte 60 is MSB. Bit 0 of byte 63
209 * is LSB. Rx_PWR(3) should be set
210 * to zero for “internally
211 * calibrated” devices.*/
212 #define SFF_8472_RX_POWER2 64 /* Rx_PWR(2) Single precision
213 * floating point calibration data,
214 * Rx optical power. Bit 7 of byte
215 * 64 is MSB, bit 0 of byte 67 is
216 * LSB. Rx_PWR(2) should be set to
217 * zero for “internally calibrated”
219 #define SFF_8472_RX_POWER1 68 /* Rx_PWR(1) Single precision
220 * floating point calibration data,
221 * Rx optical power. Bit 7 of byte
222 * 68 is MSB, bit 0 of byte 71 is
223 * LSB. Rx_PWR(1) should be set to
224 * 1 for “internally calibrated”
226 #define SFF_8472_RX_POWER0 72 /* Rx_PWR(0) Single precision
227 * floating point calibration data,
228 * Rx optical power. Bit 7 of byte
229 * 72 is MSB, bit 0 of byte 75 is
230 * LSB. Rx_PWR(0) should be set to
231 * zero for “internally calibrated”
233 #define SFF_8472_TX_I_SLOPE 76 /* Tx_I(Slope) Fixed decimal
234 * (unsigned) calibration data,
235 * laser bias current. Bit 7 of
236 * byte 76 is MSB, bit 0 of byte 77
237 * is LSB. Tx_I(Slope) should be
238 * set to 1 for “internally
239 * calibrated” devices. */
240 #define SFF_8472_TX_I_OFFSET 78 /* Tx_I(Offset) Fixed decimal
241 * (signed two’s complement)
242 * calibration data, laser bias
243 * current. Bit 7 of byte 78 is
244 * MSB, bit 0 of byte 79 is
245 * LSB. Tx_I(Offset) should be set
246 * to zero for “internally
247 * calibrated” devices. */
248 #define SFF_8472_TX_POWER_SLOPE 80 /* Tx_PWR(Slope) Fixed decimal
249 * (unsigned) calibration data,
250 * transmitter coupled output
251 * power. Bit 7 of byte 80 is MSB,
252 * bit 0 of byte 81 is LSB.
253 * Tx_PWR(Slope) should be set to 1
254 * for “internally calibrated”
256 #define SFF_8472_TX_POWER_OFFSET 82 /* Tx_PWR(Offset) Fixed decimal
257 * (signed two’s complement)
258 * calibration data, transmitter
259 * coupled output power. Bit 7 of
260 * byte 82 is MSB, bit 0 of byte 83
261 * is LSB. Tx_PWR(Offset) should be
262 * set to zero for “internally
263 * calibrated” devices. */
264 #define SFF_8472_T_SLOPE 84 /* T (Slope) Fixed decimal
265 * (unsigned) calibration data,
266 * internal module temperature. Bit
267 * 7 of byte 84 is MSB, bit 0 of
268 * byte 85 is LSB. T(Slope) should
269 * be set to 1 for “internally
270 * calibrated” devices. */
271 #define SFF_8472_T_OFFSET 86 /* T (Offset) Fixed decimal (signed
272 * two’s complement) calibration
273 * data, internal module
274 * temperature. Bit 7 of byte 86 is
275 * MSB, bit 0 of byte 87 is LSB.
276 * T(Offset) should be set to zero
277 * for “internally calibrated”
279 #define SFF_8472_V_SLOPE 88 /* V (Slope) Fixed decimal
280 * (unsigned) calibration data,
281 * internal module supply
282 * voltage. Bit 7 of byte 88 is
283 * MSB, bit 0 of byte 89 is
284 * LSB. V(Slope) should be set to 1
285 * for “internally calibrated”
287 #define SFF_8472_V_OFFSET 90 /* V (Offset) Fixed decimal (signed
288 * two’s complement) calibration
289 * data, internal module supply
290 * voltage. Bit 7 of byte 90 is
291 * MSB. Bit 0 of byte 91 is
292 * LSB. V(Offset) should be set to
293 * zero for “internally calibrated”
295 #define SFF_8472_CHECKSUM 95 /* Checksum Byte 95 contains the
296 * low order 8 bits of the sum of
298 /* Internal measurements. */
300 #define SFF_8472_TEMP 96 /* Internally measured module temperature. */
301 #define SFF_8472_VCC 98 /* Internally measured supply
302 * voltage in transceiver.
304 #define SFF_8472_TX_BIAS 100 /* Internally measured TX Bias Current. */
305 #define SFF_8472_TX_POWER 102 /* Measured TX output power. */
306 #define SFF_8472_RX_POWER 104 /* Measured RX input power. */
308 #define SFF_8472_STATUS 110 /* See below */
310 /* Status Bits Described */
313 * TX Disable State Digital state of the TX Disable Input Pin. Updated
314 * within 100ms of change on pin.
316 #define SFF_8472_STATUS_TX_DISABLE (1 << 7)
319 * Select Read/write bit that allows software disable of
320 * laser. Writing ‘1’ disables laser. See Table 3.11 for
321 * enable/disable timing requirements. This bit is “OR”d with the hard
322 * TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default
323 * enabled unless pulled low by hardware. If Soft TX Disable is not
324 * implemented, the transceiver ignores the value of this bit. Default
325 * power up value is zero/low.
327 #define SFF_8472_STATUS_SOFT_TX_DISABLE (1 << 6)
330 * RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or
331 * RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h
332 * Byte 118, Bit 3 for Soft RS(1) Select control information.
334 #define SFF_8472_RS_STATE (1 << 5)
337 * Rate_Select State [aka. “RS(0)”] Digital state of the SFP
338 * Rate_Select Input Pin. Updated within 100ms of change on pin. Note:
339 * This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431.
341 #define SFF_8472_STATUS_SELECT_STATE (1 << 4)
344 * Read/write bit that allows software rate select control. Writing
345 * ‘1’ selects full bandwidth operation. This bit is “OR’d with the
346 * hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for
347 * timing requirements. Default at power up is logic zero/low. If Soft
348 * Rate Select is not implemented, the transceiver ignores the value
349 * of this bit. Note: Specific transceiver behaviors of this bit are
350 * identified in Table 3.6a and referenced documents. See Table 3.18a,
351 * byte 118, bit 3 for Soft RS(1) Select.
353 #define SFF_8472_STATUS_SOFT_RATE_SELECT (1 << 3)
356 * TX Fault State Digital state of the TX Fault Output Pin. Updated
357 * within 100ms of change on pin.
359 #define SFF_8472_STATUS_TX_FAULT_STATE (1 << 2)
362 * Digital state of the RX_LOS Output Pin. Updated within 100ms of
365 #define SFF_8472_STATUS_RX_LOS (1 << 1)
368 * Indicates transceiver has achieved power up and data is ready. Bit
369 * remains high until data is ready to be read at which time the
370 * device sets the bit low.
372 #define SFF_8472_STATUS_DATA_READY (1 << 0)
374 /* Table 3.2 Identifier values */
375 #define SFF_8472_ID_UNKNOWN 0x0 /* Unknown or unspecified */
376 #define SFF_8472_ID_GBIC 0x1 /* GBIC */
377 #define SFF_8472_ID_SFF 0x2 /* Module soldered to motherboard (ex: SFF)*/
378 #define SFF_8472_ID_SFP 0x3 /* SFP or SFP “Plus” */
379 #define SFF_8472_ID_XBI 0x4 /* Reserved for “300 pin XBI” devices */
380 #define SFF_8472_ID_XENPAK 0x5 /* Reserved for “Xenpak” devices */
381 #define SFF_8472_ID_XFP 0x6 /* Reserved for “XFP” devices */
382 #define SFF_8472_ID_XFF 0x7 /* Reserved for “XFF” devices */
383 #define SFF_8472_ID_XFPE 0x8 /* Reserved for “XFP-E” devices */
384 #define SFF_8472_ID_XPAK 0x9 /* Reserved for “XPak” devices */
385 #define SFF_8472_ID_X2 0xA /* Reserved for “X2” devices */
386 #define SFF_8472_ID_DWDM_SFP 0xB /* Reserved for “DWDM-SFP” devices */
387 #define SFF_8472_ID_QSFP 0xC /* Reserved for “QSFP” devices */
388 #define SFF_8472_ID_LAST SFF_8472_ID_QSFP
390 static char *sff_8472_id[SFF_8472_ID_LAST + 1] = {"Unknown",
404 /* Table 3.13 and 3.14 Temperature Conversion Values */
405 #define SFF_8472_TEMP_SIGN (1 << 15)
406 #define SFF_8472_TEMP_SHIFT 8
407 #define SFF_8472_TEMP_MSK 0xEF00
408 #define SFF_8472_TEMP_FRAC 0x00FF
410 /* Internal Callibration Conversion factors */
413 * Represented as a 16 bit unsigned integer with the voltage defined
414 * as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt,
415 * yielding a total range of 0 to +6.55 Volts.
417 #define SFF_8472_VCC_FACTOR 10000.0
420 * Represented as a 16 bit unsigned integer with the current defined
421 * as the full 16 bit value (0 – 65535) with LSB equal to 2 uA,
422 * yielding a total range of 0 to 131 mA.
425 #define SFF_8472_BIAS_FACTOR 2000.0
428 * Represented as a 16 bit unsigned integer with the power defined as
429 * the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW,
430 * yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm).
433 #define SFF_8472_POWER_FACTOR 10000.0