2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/pci.h>
38 #include <linux/errno.h>
40 #include <linux/mlx4/cmd.h>
41 #include <linux/semaphore.h>
42 #include <rdma/ib_smi.h>
49 #define CMD_POLL_TOKEN 0xffff
50 #define INBOX_MASK 0xffffffffffffff00ULL
52 #define CMD_CHAN_VER 1
53 #define CMD_CHAN_IF_REV 1
56 /* command completed successfully: */
58 /* Internal error (such as a bus error) occurred while processing command: */
59 CMD_STAT_INTERNAL_ERR = 0x01,
60 /* Operation/command not supported or opcode modifier not supported: */
61 CMD_STAT_BAD_OP = 0x02,
62 /* Parameter not supported or parameter out of range: */
63 CMD_STAT_BAD_PARAM = 0x03,
64 /* System not enabled or bad system state: */
65 CMD_STAT_BAD_SYS_STATE = 0x04,
66 /* Attempt to access reserved or unallocaterd resource: */
67 CMD_STAT_BAD_RESOURCE = 0x05,
68 /* Requested resource is currently executing a command, or is otherwise busy: */
69 CMD_STAT_RESOURCE_BUSY = 0x06,
70 /* Required capability exceeds device limits: */
71 CMD_STAT_EXCEED_LIM = 0x08,
72 /* Resource is not in the appropriate state or ownership: */
73 CMD_STAT_BAD_RES_STATE = 0x09,
74 /* Index out of range: */
75 CMD_STAT_BAD_INDEX = 0x0a,
76 /* FW image corrupted: */
77 CMD_STAT_BAD_NVMEM = 0x0b,
78 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
79 CMD_STAT_ICM_ERROR = 0x0c,
80 /* Attempt to modify a QP/EE which is not in the presumed state: */
81 CMD_STAT_BAD_QP_STATE = 0x10,
82 /* Bad segment parameters (Address/Size): */
83 CMD_STAT_BAD_SEG_PARAM = 0x20,
84 /* Memory Region has Memory Windows bound to: */
85 CMD_STAT_REG_BOUND = 0x21,
86 /* HCA local attached memory not present: */
87 CMD_STAT_LAM_NOT_PRE = 0x22,
88 /* Bad management packet (silently discarded): */
89 CMD_STAT_BAD_PKT = 0x30,
90 /* More outstanding CQEs in CQ than new CQ size: */
91 CMD_STAT_BAD_SIZE = 0x40,
92 /* Multi Function device support required: */
93 CMD_STAT_MULTI_FUNC_REQ = 0x50,
97 HCR_IN_PARAM_OFFSET = 0x00,
98 HCR_IN_MODIFIER_OFFSET = 0x08,
99 HCR_OUT_PARAM_OFFSET = 0x0c,
100 HCR_TOKEN_OFFSET = 0x14,
101 HCR_STATUS_OFFSET = 0x18,
103 HCR_OPMOD_SHIFT = 12,
110 GO_BIT_TIMEOUT_MSECS = 10000
113 struct mlx4_cmd_context {
114 struct completion done;
122 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
123 struct mlx4_vhcr_cmd *in_vhcr);
125 static int mlx4_status_to_errno(u8 status)
127 static const int trans_table[] = {
128 [CMD_STAT_INTERNAL_ERR] = -EIO,
129 [CMD_STAT_BAD_OP] = -EPERM,
130 [CMD_STAT_BAD_PARAM] = -EINVAL,
131 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
132 [CMD_STAT_BAD_RESOURCE] = -EBADF,
133 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
134 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
135 [CMD_STAT_BAD_RES_STATE] = -EBADF,
136 [CMD_STAT_BAD_INDEX] = -EBADF,
137 [CMD_STAT_BAD_NVMEM] = -EFAULT,
138 [CMD_STAT_ICM_ERROR] = -ENFILE,
139 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
140 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
141 [CMD_STAT_REG_BOUND] = -EBUSY,
142 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
143 [CMD_STAT_BAD_PKT] = -EINVAL,
144 [CMD_STAT_BAD_SIZE] = -ENOMEM,
145 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
148 if (status >= ARRAY_SIZE(trans_table) ||
149 (status != CMD_STAT_OK && trans_table[status] == 0))
152 return trans_table[status];
155 static u8 mlx4_errno_to_status(int errno)
159 return CMD_STAT_BAD_OP;
161 return CMD_STAT_BAD_PARAM;
163 return CMD_STAT_BAD_SYS_STATE;
165 return CMD_STAT_RESOURCE_BUSY;
167 return CMD_STAT_EXCEED_LIM;
169 return CMD_STAT_ICM_ERROR;
171 return CMD_STAT_INTERNAL_ERR;
175 static int comm_pending(struct mlx4_dev *dev)
177 struct mlx4_priv *priv = mlx4_priv(dev);
178 u32 status = readl(&priv->mfunc.comm->slave_read);
180 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
183 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
185 struct mlx4_priv *priv = mlx4_priv(dev);
188 priv->cmd.comm_toggle ^= 1;
189 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
190 __raw_writel((__force u32) cpu_to_be32(val),
191 &priv->mfunc.comm->slave_write);
195 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
196 unsigned long timeout)
198 struct mlx4_priv *priv = mlx4_priv(dev);
201 int ret_from_pending = 0;
203 /* First, verify that the master reports correct status */
204 if (comm_pending(dev)) {
205 mlx4_warn(dev, "Communication channel is not idle."
206 "my toggle is %d (cmd:0x%x)\n",
207 priv->cmd.comm_toggle, cmd);
212 down(&priv->cmd.poll_sem);
213 mlx4_comm_cmd_post(dev, cmd, param);
215 end = msecs_to_jiffies(timeout) + jiffies;
216 while (comm_pending(dev) && time_before(jiffies, end))
218 ret_from_pending = comm_pending(dev);
219 if (ret_from_pending) {
220 /* check if the slave is trying to boot in the middle of
221 * FLR process. The only non-zero result in the RESET command
222 * is MLX4_DELAY_RESET_SLAVE*/
223 if ((MLX4_COMM_CMD_RESET == cmd)) {
224 mlx4_warn(dev, "Got slave FLRed from Communication"
225 " channel (ret:0x%x)\n", ret_from_pending);
226 err = MLX4_DELAY_RESET_SLAVE;
228 mlx4_warn(dev, "Communication channel timed out\n");
233 up(&priv->cmd.poll_sem);
237 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
238 u16 param, unsigned long timeout)
240 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
241 struct mlx4_cmd_context *context;
245 down(&cmd->event_sem);
247 spin_lock(&cmd->context_lock);
248 BUG_ON(cmd->free_head < 0);
249 context = &cmd->context[cmd->free_head];
250 context->token += cmd->token_mask + 1;
251 cmd->free_head = context->next;
252 spin_unlock(&cmd->context_lock);
254 init_completion(&context->done);
256 mlx4_comm_cmd_post(dev, op, param);
258 if (!wait_for_completion_timeout(&context->done,
259 msecs_to_jiffies(timeout))) {
260 mlx4_warn(dev, "communication channel command 0x%x timed out\n", op);
265 err = context->result;
266 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
267 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
268 op, context->fw_status);
273 /* wait for comm channel ready
274 * this is necessary for prevention the race
275 * when switching between event to polling mode
277 end = msecs_to_jiffies(timeout) + jiffies;
278 while (comm_pending(dev) && time_before(jiffies, end))
281 spin_lock(&cmd->context_lock);
282 context->next = cmd->free_head;
283 cmd->free_head = context - cmd->context;
284 spin_unlock(&cmd->context_lock);
290 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
291 unsigned long timeout)
293 if (mlx4_priv(dev)->cmd.use_events)
294 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
295 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
298 static int cmd_pending(struct mlx4_dev *dev)
302 if (pci_channel_offline(dev->pdev))
305 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
307 return (status & swab32(1 << HCR_GO_BIT)) ||
308 (mlx4_priv(dev)->cmd.toggle ==
309 !!(status & swab32(1 << HCR_T_BIT)));
312 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
313 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
316 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
317 u32 __iomem *hcr = cmd->hcr;
321 mutex_lock(&cmd->hcr_mutex);
323 if (pci_channel_offline(dev->pdev)) {
325 * Device is going through error recovery
326 * and cannot accept commands.
334 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
336 while (cmd_pending(dev)) {
337 if (pci_channel_offline(dev->pdev)) {
339 * Device is going through error recovery
340 * and cannot accept commands.
346 if (time_after_eq(jiffies, end)) {
347 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
354 * We use writel (instead of something like memcpy_toio)
355 * because writes of less than 32 bits to the HCR don't work
356 * (and some architectures such as ia64 implement memcpy_toio
357 * in terms of writeb).
359 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
360 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
361 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
362 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
363 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
364 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
366 /* __raw_writel may not order writes. */
369 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
370 (cmd->toggle << HCR_T_BIT) |
371 (event ? (1 << HCR_E_BIT) : 0) |
372 (op_modifier << HCR_OPMOD_SHIFT) |
376 * Make sure that our HCR writes don't get mixed in with
377 * writes from another CPU starting a FW command.
381 cmd->toggle = cmd->toggle ^ 1;
386 mutex_unlock(&cmd->hcr_mutex);
390 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
391 int out_is_imm, u32 in_modifier, u8 op_modifier,
392 u16 op, unsigned long timeout)
394 struct mlx4_priv *priv = mlx4_priv(dev);
395 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
398 mutex_lock(&priv->cmd.slave_cmd_mutex);
400 vhcr->in_param = cpu_to_be64(in_param);
401 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
402 vhcr->in_modifier = cpu_to_be32(in_modifier);
403 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
404 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
406 vhcr->flags = !!(priv->cmd.use_events) << 6;
408 if (mlx4_is_master(dev)) {
409 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
414 be64_to_cpu(vhcr->out_param);
416 mlx4_err(dev, "response expected while"
417 "output mailbox is NULL for "
418 "command 0x%x\n", op);
419 vhcr->status = CMD_STAT_BAD_PARAM;
422 ret = mlx4_status_to_errno(vhcr->status);
425 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
426 MLX4_COMM_TIME + timeout);
431 be64_to_cpu(vhcr->out_param);
433 mlx4_err(dev, "response expected while"
434 "output mailbox is NULL for "
435 "command 0x%x\n", op);
436 vhcr->status = CMD_STAT_BAD_PARAM;
439 ret = mlx4_status_to_errno(vhcr->status);
441 mlx4_err(dev, "failed execution of VHCR_POST command"
442 "opcode 0x%x\n", op);
445 mutex_unlock(&priv->cmd.slave_cmd_mutex);
449 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
450 int out_is_imm, u32 in_modifier, u8 op_modifier,
451 u16 op, unsigned long timeout)
453 struct mlx4_priv *priv = mlx4_priv(dev);
454 void __iomem *hcr = priv->cmd.hcr;
459 down(&priv->cmd.poll_sem);
461 if (pci_channel_offline(dev->pdev)) {
463 * Device is going through error recovery
464 * and cannot accept commands.
470 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
471 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
475 end = msecs_to_jiffies(timeout) + jiffies;
476 while (cmd_pending(dev) && time_before(jiffies, end)) {
477 if (pci_channel_offline(dev->pdev)) {
479 * Device is going through error recovery
480 * and cannot accept commands.
489 if (cmd_pending(dev)) {
490 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n", op);
497 (u64) be32_to_cpu((__force __be32)
498 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
499 (u64) be32_to_cpu((__force __be32)
500 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
501 stat = be32_to_cpu((__force __be32)
502 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
503 err = mlx4_status_to_errno(stat);
505 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
509 up(&priv->cmd.poll_sem);
513 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
515 struct mlx4_priv *priv = mlx4_priv(dev);
516 struct mlx4_cmd_context *context =
517 &priv->cmd.context[token & priv->cmd.token_mask];
519 /* previously timed out command completing at long last */
520 if (token != context->token)
523 context->fw_status = status;
524 context->result = mlx4_status_to_errno(status);
525 context->out_param = out_param;
527 complete(&context->done);
530 static int get_status(struct mlx4_dev *dev, u32 *status, int *go_bit,
533 if (pci_channel_offline(dev->pdev))
536 *status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
537 *t_bit = !!(*status & swab32(1 << HCR_T_BIT));
538 *go_bit = !!(*status & swab32(1 << HCR_GO_BIT));
543 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
544 int out_is_imm, u32 in_modifier, u8 op_modifier,
545 u16 op, unsigned long timeout)
547 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
548 struct mlx4_cmd_context *context;
550 int go_bit = 0, t_bit = 0, stat_err;
553 down(&cmd->event_sem);
555 spin_lock(&cmd->context_lock);
556 BUG_ON(cmd->free_head < 0);
557 context = &cmd->context[cmd->free_head];
558 context->token += cmd->token_mask + 1;
559 cmd->free_head = context->next;
560 spin_unlock(&cmd->context_lock);
562 init_completion(&context->done);
564 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
565 in_modifier, op_modifier, op, context->token, 1);
567 mlx4_warn(dev, "command 0x%x could not be posted (%d)\n",
572 if (!wait_for_completion_timeout(&context->done,
573 msecs_to_jiffies(timeout))) {
574 stat_err = get_status(dev, &status, &go_bit, &t_bit);
575 mlx4_warn(dev, "command 0x%x timed out: "
576 "get_status err=%d, status=0x%x, go_bit=%d, "
577 "t_bit=%d, toggle=0x%x\n", op, stat_err, status,
578 go_bit, t_bit, mlx4_priv(dev)->cmd.toggle);
583 err = context->result;
585 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
586 op, context->fw_status);
591 *out_param = context->out_param;
594 spin_lock(&cmd->context_lock);
595 context->next = cmd->free_head;
596 cmd->free_head = context - cmd->context;
597 spin_unlock(&cmd->context_lock);
603 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
604 int out_is_imm, u32 in_modifier, u8 op_modifier,
605 u16 op, unsigned long timeout, int native)
607 if (pci_channel_offline(dev->pdev))
610 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
611 if (mlx4_priv(dev)->cmd.use_events)
612 return mlx4_cmd_wait(dev, in_param, out_param,
613 out_is_imm, in_modifier,
614 op_modifier, op, timeout);
616 return mlx4_cmd_poll(dev, in_param, out_param,
617 out_is_imm, in_modifier,
618 op_modifier, op, timeout);
620 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
621 in_modifier, op_modifier, op, timeout);
623 EXPORT_SYMBOL_GPL(__mlx4_cmd);
626 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
628 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
629 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
632 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
633 int slave, u64 slave_addr,
634 int size, int is_read)
639 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
640 (slave & ~0x7f) | (size & 0xff)) {
641 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
642 "master_addr:0x%llx slave_id:%d size:%d\n",
643 slave_addr, master_addr, slave, size);
648 in_param = (u64) slave | slave_addr;
649 out_param = (u64) dev->caps.function | master_addr;
651 in_param = (u64) dev->caps.function | master_addr;
652 out_param = (u64) slave | slave_addr;
655 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
657 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
660 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
661 struct mlx4_cmd_mailbox *inbox,
662 struct mlx4_cmd_mailbox *outbox)
664 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
665 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
672 in_mad->attr_mod = cpu_to_be32(index / 32);
674 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
675 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
680 for (i = 0; i < 32; ++i)
681 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
686 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
687 struct mlx4_cmd_mailbox *inbox,
688 struct mlx4_cmd_mailbox *outbox)
693 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
694 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
701 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
702 #define PORT_STATE_OFFSET 32
704 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
706 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
707 return IB_PORT_ACTIVE;
712 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
713 struct mlx4_vhcr *vhcr,
714 struct mlx4_cmd_mailbox *inbox,
715 struct mlx4_cmd_mailbox *outbox,
716 struct mlx4_cmd_info *cmd)
718 struct ib_smp *smp = inbox->buf;
724 struct mlx4_priv *priv = mlx4_priv(dev);
725 struct ib_smp *outsmp = outbox->buf;
726 __be16 *outtab = (__be16 *)(outsmp->data);
727 __be32 slave_cap_mask;
728 __be64 slave_node_guid;
729 port = vhcr->in_modifier;
731 if (smp->base_version == 1 &&
732 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
733 smp->class_version == 1) {
734 if (smp->method == IB_MGMT_METHOD_GET) {
735 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
736 index = be32_to_cpu(smp->attr_mod);
737 if (port < 1 || port > dev->caps.num_ports)
739 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
742 /* need to get the full pkey table because the paravirtualized
743 * pkeys may be scattered among several pkey blocks.
745 err = get_full_pkey_table(dev, port, table, inbox, outbox);
747 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
748 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
749 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
755 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
756 /*get the slave specific caps:*/
758 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
759 vhcr->in_modifier, vhcr->op_modifier,
760 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
761 /* modify the response for slaves */
762 if (!err && slave != mlx4_master_func_num(dev)) {
763 u8 *state = outsmp->data + PORT_STATE_OFFSET;
765 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
766 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
767 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
771 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
772 /* compute slave's gid block */
773 smp->attr_mod = cpu_to_be32(slave / 8);
775 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
776 vhcr->in_modifier, vhcr->op_modifier,
777 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
779 /* if needed, move slave gid to index 0 */
782 outsmp->data + (slave % 8) * 8, 8);
783 /* delete all other gids */
784 memset(outsmp->data + 8, 0, 56);
788 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
789 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
790 vhcr->in_modifier, vhcr->op_modifier,
791 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
793 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
794 memcpy(outsmp->data + 12, &slave_node_guid, 8);
800 if (slave != mlx4_master_func_num(dev) &&
801 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
802 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
803 smp->method == IB_MGMT_METHOD_SET))) {
804 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
805 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
806 slave, smp->method, smp->mgmt_class,
807 be16_to_cpu(smp->attr_id));
811 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
812 vhcr->in_modifier, vhcr->op_modifier,
813 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
816 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
817 struct mlx4_vhcr *vhcr,
818 struct mlx4_cmd_mailbox *inbox,
819 struct mlx4_cmd_mailbox *outbox,
820 struct mlx4_cmd_info *cmd)
826 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
827 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
828 if (cmd->encode_slave_id) {
829 in_param &= 0xffffffffffffff00ll;
833 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
834 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
835 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
838 vhcr->out_param = out_param;
843 static struct mlx4_cmd_info cmd_info[] = {
845 .opcode = MLX4_CMD_QUERY_FW,
849 .encode_slave_id = false,
851 .wrapper = mlx4_QUERY_FW_wrapper
854 .opcode = MLX4_CMD_QUERY_HCA,
858 .encode_slave_id = false,
863 .opcode = MLX4_CMD_QUERY_DEV_CAP,
867 .encode_slave_id = false,
869 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
872 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
876 .encode_slave_id = false,
878 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
881 .opcode = MLX4_CMD_QUERY_ADAPTER,
885 .encode_slave_id = false,
890 .opcode = MLX4_CMD_INIT_PORT,
894 .encode_slave_id = false,
896 .wrapper = mlx4_INIT_PORT_wrapper
899 .opcode = MLX4_CMD_CLOSE_PORT,
903 .encode_slave_id = false,
905 .wrapper = mlx4_CLOSE_PORT_wrapper
908 .opcode = MLX4_CMD_QUERY_PORT,
912 .encode_slave_id = false,
914 .wrapper = mlx4_QUERY_PORT_wrapper
917 .opcode = MLX4_CMD_SET_PORT,
921 .encode_slave_id = false,
923 .wrapper = mlx4_SET_PORT_wrapper
926 .opcode = MLX4_CMD_MAP_EQ,
930 .encode_slave_id = false,
932 .wrapper = mlx4_MAP_EQ_wrapper
935 .opcode = MLX4_CMD_SW2HW_EQ,
939 .encode_slave_id = true,
941 .wrapper = mlx4_SW2HW_EQ_wrapper
944 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
948 .encode_slave_id = false,
953 .opcode = MLX4_CMD_NOP,
957 .encode_slave_id = false,
962 .opcode = MLX4_CMD_ALLOC_RES,
966 .encode_slave_id = false,
968 .wrapper = mlx4_ALLOC_RES_wrapper
971 .opcode = MLX4_CMD_FREE_RES,
975 .encode_slave_id = false,
977 .wrapper = mlx4_FREE_RES_wrapper
980 .opcode = MLX4_CMD_SW2HW_MPT,
984 .encode_slave_id = true,
986 .wrapper = mlx4_SW2HW_MPT_wrapper
989 .opcode = MLX4_CMD_QUERY_MPT,
993 .encode_slave_id = false,
995 .wrapper = mlx4_QUERY_MPT_wrapper
998 .opcode = MLX4_CMD_HW2SW_MPT,
1000 .has_outbox = false,
1001 .out_is_imm = false,
1002 .encode_slave_id = false,
1004 .wrapper = mlx4_HW2SW_MPT_wrapper
1007 .opcode = MLX4_CMD_READ_MTT,
1010 .out_is_imm = false,
1011 .encode_slave_id = false,
1016 .opcode = MLX4_CMD_WRITE_MTT,
1018 .has_outbox = false,
1019 .out_is_imm = false,
1020 .encode_slave_id = false,
1022 .wrapper = mlx4_WRITE_MTT_wrapper
1025 .opcode = MLX4_CMD_SYNC_TPT,
1027 .has_outbox = false,
1028 .out_is_imm = false,
1029 .encode_slave_id = false,
1034 .opcode = MLX4_CMD_HW2SW_EQ,
1037 .out_is_imm = false,
1038 .encode_slave_id = true,
1040 .wrapper = mlx4_HW2SW_EQ_wrapper
1043 .opcode = MLX4_CMD_QUERY_EQ,
1046 .out_is_imm = false,
1047 .encode_slave_id = true,
1049 .wrapper = mlx4_QUERY_EQ_wrapper
1052 .opcode = MLX4_CMD_SW2HW_CQ,
1054 .has_outbox = false,
1055 .out_is_imm = false,
1056 .encode_slave_id = true,
1058 .wrapper = mlx4_SW2HW_CQ_wrapper
1061 .opcode = MLX4_CMD_HW2SW_CQ,
1063 .has_outbox = false,
1064 .out_is_imm = false,
1065 .encode_slave_id = false,
1067 .wrapper = mlx4_HW2SW_CQ_wrapper
1070 .opcode = MLX4_CMD_QUERY_CQ,
1073 .out_is_imm = false,
1074 .encode_slave_id = false,
1076 .wrapper = mlx4_QUERY_CQ_wrapper
1079 .opcode = MLX4_CMD_MODIFY_CQ,
1081 .has_outbox = false,
1083 .encode_slave_id = false,
1085 .wrapper = mlx4_MODIFY_CQ_wrapper
1088 .opcode = MLX4_CMD_SW2HW_SRQ,
1090 .has_outbox = false,
1091 .out_is_imm = false,
1092 .encode_slave_id = true,
1094 .wrapper = mlx4_SW2HW_SRQ_wrapper
1097 .opcode = MLX4_CMD_HW2SW_SRQ,
1099 .has_outbox = false,
1100 .out_is_imm = false,
1101 .encode_slave_id = false,
1103 .wrapper = mlx4_HW2SW_SRQ_wrapper
1106 .opcode = MLX4_CMD_QUERY_SRQ,
1109 .out_is_imm = false,
1110 .encode_slave_id = false,
1112 .wrapper = mlx4_QUERY_SRQ_wrapper
1115 .opcode = MLX4_CMD_ARM_SRQ,
1117 .has_outbox = false,
1118 .out_is_imm = false,
1119 .encode_slave_id = false,
1121 .wrapper = mlx4_ARM_SRQ_wrapper
1124 .opcode = MLX4_CMD_RST2INIT_QP,
1126 .has_outbox = false,
1127 .out_is_imm = false,
1128 .encode_slave_id = true,
1130 .wrapper = mlx4_RST2INIT_QP_wrapper
1133 .opcode = MLX4_CMD_INIT2INIT_QP,
1135 .has_outbox = false,
1136 .out_is_imm = false,
1137 .encode_slave_id = false,
1139 .wrapper = mlx4_INIT2INIT_QP_wrapper
1142 .opcode = MLX4_CMD_INIT2RTR_QP,
1144 .has_outbox = false,
1145 .out_is_imm = false,
1146 .encode_slave_id = false,
1148 .wrapper = mlx4_INIT2RTR_QP_wrapper
1151 .opcode = MLX4_CMD_RTR2RTS_QP,
1153 .has_outbox = false,
1154 .out_is_imm = false,
1155 .encode_slave_id = false,
1157 .wrapper = mlx4_RTR2RTS_QP_wrapper
1160 .opcode = MLX4_CMD_RTS2RTS_QP,
1162 .has_outbox = false,
1163 .out_is_imm = false,
1164 .encode_slave_id = false,
1166 .wrapper = mlx4_RTS2RTS_QP_wrapper
1169 .opcode = MLX4_CMD_SQERR2RTS_QP,
1171 .has_outbox = false,
1172 .out_is_imm = false,
1173 .encode_slave_id = false,
1175 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1178 .opcode = MLX4_CMD_2ERR_QP,
1180 .has_outbox = false,
1181 .out_is_imm = false,
1182 .encode_slave_id = false,
1184 .wrapper = mlx4_GEN_QP_wrapper
1187 .opcode = MLX4_CMD_RTS2SQD_QP,
1189 .has_outbox = false,
1190 .out_is_imm = false,
1191 .encode_slave_id = false,
1193 .wrapper = mlx4_GEN_QP_wrapper
1196 .opcode = MLX4_CMD_SQD2SQD_QP,
1198 .has_outbox = false,
1199 .out_is_imm = false,
1200 .encode_slave_id = false,
1202 .wrapper = mlx4_SQD2SQD_QP_wrapper
1205 .opcode = MLX4_CMD_SQD2RTS_QP,
1207 .has_outbox = false,
1208 .out_is_imm = false,
1209 .encode_slave_id = false,
1211 .wrapper = mlx4_SQD2RTS_QP_wrapper
1214 .opcode = MLX4_CMD_2RST_QP,
1216 .has_outbox = false,
1217 .out_is_imm = false,
1218 .encode_slave_id = false,
1220 .wrapper = mlx4_2RST_QP_wrapper
1223 .opcode = MLX4_CMD_QUERY_QP,
1226 .out_is_imm = false,
1227 .encode_slave_id = false,
1229 .wrapper = mlx4_GEN_QP_wrapper
1232 .opcode = MLX4_CMD_SUSPEND_QP,
1234 .has_outbox = false,
1235 .out_is_imm = false,
1236 .encode_slave_id = false,
1238 .wrapper = mlx4_GEN_QP_wrapper
1241 .opcode = MLX4_CMD_UNSUSPEND_QP,
1243 .has_outbox = false,
1244 .out_is_imm = false,
1245 .encode_slave_id = false,
1247 .wrapper = mlx4_GEN_QP_wrapper
1250 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1252 .has_outbox = false,
1253 .out_is_imm = false,
1254 .encode_slave_id = false,
1255 .verify = NULL, /* XXX verify: only demux can do this */
1259 .opcode = MLX4_CMD_MAD_IFC,
1262 .out_is_imm = false,
1263 .encode_slave_id = false,
1265 .wrapper = mlx4_MAD_IFC_wrapper
1268 .opcode = MLX4_CMD_QUERY_IF_STAT,
1271 .out_is_imm = false,
1272 .encode_slave_id = false,
1274 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1276 /* Native multicast commands are not available for guests */
1278 .opcode = MLX4_CMD_QP_ATTACH,
1280 .has_outbox = false,
1281 .out_is_imm = false,
1282 .encode_slave_id = false,
1284 .wrapper = mlx4_QP_ATTACH_wrapper
1287 .opcode = MLX4_CMD_PROMISC,
1289 .has_outbox = false,
1290 .out_is_imm = false,
1291 .encode_slave_id = false,
1293 .wrapper = mlx4_PROMISC_wrapper
1295 /* Ethernet specific commands */
1297 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1299 .has_outbox = false,
1300 .out_is_imm = false,
1301 .encode_slave_id = false,
1303 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1306 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1308 .has_outbox = false,
1309 .out_is_imm = false,
1310 .encode_slave_id = false,
1312 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1315 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1318 .out_is_imm = false,
1319 .encode_slave_id = false,
1321 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1324 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1326 .has_outbox = false,
1327 .out_is_imm = false,
1328 .encode_slave_id = false,
1332 /* flow steering commands */
1334 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1336 .has_outbox = false,
1338 .encode_slave_id = false,
1340 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1343 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1345 .has_outbox = false,
1346 .out_is_imm = false,
1347 .encode_slave_id = false,
1349 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1353 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1354 struct mlx4_vhcr_cmd *in_vhcr)
1356 struct mlx4_priv *priv = mlx4_priv(dev);
1357 struct mlx4_cmd_info *cmd = NULL;
1358 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1359 struct mlx4_vhcr *vhcr;
1360 struct mlx4_cmd_mailbox *inbox = NULL;
1361 struct mlx4_cmd_mailbox *outbox = NULL;
1368 /* Create sw representation of Virtual HCR */
1369 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1373 /* DMA in the vHCR */
1375 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1376 priv->mfunc.master.slave_state[slave].vhcr_dma,
1377 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1378 MLX4_ACCESS_MEM_ALIGN), 1);
1380 mlx4_err(dev, "%s:Failed reading vhcr"
1381 "ret: 0x%x\n", __func__, ret);
1387 /* Fill SW VHCR fields */
1388 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1389 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1390 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1391 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1392 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1393 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1394 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1396 /* Lookup command */
1397 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1398 if (vhcr->op == cmd_info[i].opcode) {
1404 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1406 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1411 if (cmd->has_inbox) {
1412 vhcr->in_param &= INBOX_MASK;
1413 inbox = mlx4_alloc_cmd_mailbox(dev);
1414 if (IS_ERR(inbox)) {
1415 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1420 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1422 MLX4_MAILBOX_SIZE, 1)) {
1423 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1424 __func__, cmd->opcode);
1425 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1430 /* Apply permission and bound checks if applicable */
1431 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1432 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1433 "checks for resource_id:%d\n", vhcr->op, slave,
1435 vhcr_cmd->status = CMD_STAT_BAD_OP;
1439 /* Allocate outbox */
1440 if (cmd->has_outbox) {
1441 outbox = mlx4_alloc_cmd_mailbox(dev);
1442 if (IS_ERR(outbox)) {
1443 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1449 /* Execute the command! */
1451 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1453 if (cmd->out_is_imm)
1454 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1456 in_param = cmd->has_inbox ? (u64) inbox->dma :
1458 out_param = cmd->has_outbox ? (u64) outbox->dma :
1460 err = __mlx4_cmd(dev, in_param, &out_param,
1461 cmd->out_is_imm, vhcr->in_modifier,
1462 vhcr->op_modifier, vhcr->op,
1463 MLX4_CMD_TIME_CLASS_A,
1466 if (cmd->out_is_imm) {
1467 vhcr->out_param = out_param;
1468 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1473 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1474 " error:%d, status %d\n",
1475 vhcr->op, slave, vhcr->errno, err);
1476 vhcr_cmd->status = mlx4_errno_to_status(err);
1481 /* Write outbox if command completed successfully */
1482 if (cmd->has_outbox && !vhcr_cmd->status) {
1483 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1485 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1487 /* If we failed to write back the outbox after the
1488 *command was successfully executed, we must fail this
1489 * slave, as it is now in undefined state */
1490 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1496 /* DMA back vhcr result */
1498 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1499 priv->mfunc.master.slave_state[slave].vhcr_dma,
1500 ALIGN(sizeof(struct mlx4_vhcr),
1501 MLX4_ACCESS_MEM_ALIGN),
1504 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1506 else if (vhcr->e_bit &&
1507 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1508 mlx4_warn(dev, "Failed to generate command completion "
1509 "eqe for slave %d\n", slave);
1514 mlx4_free_cmd_mailbox(dev, inbox);
1515 mlx4_free_cmd_mailbox(dev, outbox);
1519 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1522 struct mlx4_vport_state *vp_admin;
1523 struct mlx4_vport_oper_state *vp_oper;
1525 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1526 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1527 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1528 vp_oper->state = *vp_admin;
1529 if (MLX4_VGT != vp_admin->default_vlan) {
1530 err = mlx4_register_vlan(&priv->dev, port,
1531 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1533 vp_oper->vlan_idx = NO_INDX;
1534 mlx4_warn((&priv->dev),
1535 "No vlan resorces slave %d, port %d\n",
1539 mlx4_dbg((&(priv->dev)), "alloc vlan %d idx %d slave %d port %d\n",
1540 (int)(vp_oper->state.default_vlan),
1541 vp_oper->vlan_idx, slave, port);
1543 if (vp_admin->spoofchk) {
1544 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1547 if (0 > vp_oper->mac_idx) {
1548 err = vp_oper->mac_idx;
1549 vp_oper->mac_idx = NO_INDX;
1550 mlx4_warn((&priv->dev),
1551 "No mac resorces slave %d, port %d\n",
1555 mlx4_dbg((&(priv->dev)), "alloc mac %llx idx %d slave %d port %d\n",
1556 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1562 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1565 struct mlx4_vport_oper_state *vp_oper;
1567 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1568 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1569 if (NO_INDX != vp_oper->vlan_idx) {
1570 __mlx4_unregister_vlan(&priv->dev,
1571 port, vp_oper->state.default_vlan);
1572 vp_oper->vlan_idx = NO_INDX;
1574 if (NO_INDX != vp_oper->mac_idx) {
1575 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
1576 vp_oper->mac_idx = NO_INDX;
1582 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1583 u16 param, u8 toggle)
1585 struct mlx4_priv *priv = mlx4_priv(dev);
1586 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1588 u8 is_going_down = 0;
1590 unsigned long flags;
1592 slave_state[slave].comm_toggle ^= 1;
1593 reply = (u32) slave_state[slave].comm_toggle << 31;
1594 if (toggle != slave_state[slave].comm_toggle) {
1595 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1596 "STATE COMPROMISIED ***\n", toggle, slave);
1599 if (cmd == MLX4_COMM_CMD_RESET) {
1600 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1601 slave_state[slave].active = false;
1602 mlx4_master_deactivate_admin_state(priv, slave);
1603 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1604 slave_state[slave].event_eq[i].eqn = -1;
1605 slave_state[slave].event_eq[i].token = 0;
1607 /*check if we are in the middle of FLR process,
1608 if so return "retry" status to the slave*/
1609 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1610 goto inform_slave_state;
1612 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1614 /* write the version in the event field */
1615 reply |= mlx4_comm_get_version();
1619 /*command from slave in the middle of FLR*/
1620 if (cmd != MLX4_COMM_CMD_RESET &&
1621 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1622 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1623 "in the middle of FLR\n", slave, cmd);
1628 case MLX4_COMM_CMD_VHCR0:
1629 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1631 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1632 priv->mfunc.master.slave_state[slave].cookie = 0;
1633 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1635 case MLX4_COMM_CMD_VHCR1:
1636 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1638 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1640 case MLX4_COMM_CMD_VHCR2:
1641 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1643 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1645 case MLX4_COMM_CMD_VHCR_EN:
1646 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1648 slave_state[slave].vhcr_dma |= param;
1649 if (mlx4_master_activate_admin_state(priv, slave))
1651 slave_state[slave].active = true;
1652 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1654 case MLX4_COMM_CMD_VHCR_POST:
1655 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1656 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1659 mutex_lock(&priv->cmd.slave_cmd_mutex);
1660 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1661 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1662 " resetting slave.\n", slave);
1663 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1666 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1669 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1672 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1673 if (!slave_state[slave].is_slave_going_down)
1674 slave_state[slave].last_cmd = cmd;
1677 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1678 if (is_going_down) {
1679 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1680 " executing from slave:%d\n",
1684 __raw_writel((__force u32) cpu_to_be32(reply),
1685 &priv->mfunc.comm[slave].slave_read);
1691 /* cleanup any slave resources */
1692 mlx4_delete_all_resources_for_slave(dev, slave);
1693 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1694 if (!slave_state[slave].is_slave_going_down)
1695 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1696 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1697 /*with slave in the middle of flr, no need to clean resources again.*/
1699 memset(&slave_state[slave].event_eq, 0,
1700 sizeof(struct mlx4_slave_event_eq_info));
1701 __raw_writel((__force u32) cpu_to_be32(reply),
1702 &priv->mfunc.comm[slave].slave_read);
1706 /* master command processing */
1707 void mlx4_master_comm_channel(struct work_struct *work)
1709 struct mlx4_mfunc_master_ctx *master =
1711 struct mlx4_mfunc_master_ctx,
1713 struct mlx4_mfunc *mfunc =
1714 container_of(master, struct mlx4_mfunc, master);
1715 struct mlx4_priv *priv =
1716 container_of(mfunc, struct mlx4_priv, mfunc);
1717 struct mlx4_dev *dev = &priv->dev;
1727 bit_vec = master->comm_arm_bit_vector;
1728 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1729 vec = be32_to_cpu(bit_vec[i]);
1730 for (j = 0; j < 32; j++) {
1731 if (!(vec & (1 << j)))
1734 slave = (i * 32) + j;
1735 comm_cmd = swab32(readl(
1736 &mfunc->comm[slave].slave_write));
1737 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1739 toggle = comm_cmd >> 31;
1740 if (toggle != slt) {
1741 if (master->slave_state[slave].comm_toggle
1743 mlx4_info(dev, "slave %d out of sync."
1744 " read toggle %d, state toggle %d. "
1745 "Resynching.\n", slave, slt,
1746 master->slave_state[slave].comm_toggle);
1747 master->slave_state[slave].comm_toggle =
1750 mlx4_master_do_cmd(dev, slave,
1751 comm_cmd >> 16 & 0xff,
1752 comm_cmd & 0xffff, toggle);
1758 if (reported && reported != served)
1759 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1760 " but %d were served\n",
1763 if (mlx4_ARM_COMM_CHANNEL(dev))
1764 mlx4_warn(dev, "Failed to arm comm channel events\n");
1767 static int sync_toggles(struct mlx4_dev *dev)
1769 struct mlx4_priv *priv = mlx4_priv(dev);
1774 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1775 end = jiffies + msecs_to_jiffies(5000);
1777 while (time_before(jiffies, end)) {
1778 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1779 if (rd_toggle == wr_toggle) {
1780 priv->cmd.comm_toggle = rd_toggle;
1788 * we could reach here if for example the previous VM using this
1789 * function misbehaved and left the channel with unsynced state. We
1790 * should fix this here and give this VM a chance to use a properly
1793 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1794 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1795 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1796 priv->cmd.comm_toggle = 0;
1801 int mlx4_multi_func_init(struct mlx4_dev *dev)
1803 struct mlx4_priv *priv = mlx4_priv(dev);
1804 struct mlx4_slave_state *s_state;
1805 int i, j, err, port;
1807 if (mlx4_is_master(dev))
1809 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1810 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1813 ioremap(pci_resource_start(dev->pdev, 2) +
1814 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1815 if (!priv->mfunc.comm) {
1816 mlx4_err(dev, "Couldn't map communication vector.\n");
1820 if (mlx4_is_master(dev)) {
1821 priv->mfunc.master.slave_state =
1822 kzalloc(dev->num_slaves *
1823 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1824 if (!priv->mfunc.master.slave_state)
1827 priv->mfunc.master.vf_admin =
1828 kzalloc(dev->num_slaves *
1829 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1830 if (!priv->mfunc.master.vf_admin)
1831 goto err_comm_admin;
1833 priv->mfunc.master.vf_oper =
1834 kzalloc(dev->num_slaves *
1835 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1836 if (!priv->mfunc.master.vf_oper)
1839 for (i = 0; i < dev->num_slaves; ++i) {
1840 s_state = &priv->mfunc.master.slave_state[i];
1841 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1842 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1843 s_state->event_eq[j].eqn = -1;
1844 __raw_writel((__force u32) 0,
1845 &priv->mfunc.comm[i].slave_write);
1846 __raw_writel((__force u32) 0,
1847 &priv->mfunc.comm[i].slave_read);
1849 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1850 s_state->vlan_filter[port] =
1851 kzalloc(sizeof(struct mlx4_vlan_fltr),
1853 if (!s_state->vlan_filter[port]) {
1855 kfree(s_state->vlan_filter[port]);
1858 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1859 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
1860 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
1861 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1862 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
1864 spin_lock_init(&s_state->lock);
1867 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1868 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1869 INIT_WORK(&priv->mfunc.master.comm_work,
1870 mlx4_master_comm_channel);
1871 INIT_WORK(&priv->mfunc.master.slave_event_work,
1872 mlx4_gen_slave_eqe);
1873 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1874 mlx4_master_handle_slave_flr);
1875 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1876 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1877 priv->mfunc.master.comm_wq =
1878 create_singlethread_workqueue("mlx4_comm");
1879 if (!priv->mfunc.master.comm_wq)
1882 if (mlx4_init_resource_tracker(dev))
1885 err = mlx4_ARM_COMM_CHANNEL(dev);
1887 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1893 err = sync_toggles(dev);
1895 mlx4_err(dev, "Couldn't sync toggles\n");
1902 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1904 flush_workqueue(priv->mfunc.master.comm_wq);
1905 destroy_workqueue(priv->mfunc.master.comm_wq);
1908 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1909 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1911 kfree(priv->mfunc.master.vf_oper);
1913 kfree(priv->mfunc.master.vf_admin);
1915 kfree(priv->mfunc.master.slave_state);
1917 iounmap(priv->mfunc.comm);
1919 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1921 priv->mfunc.vhcr_dma);
1922 priv->mfunc.vhcr = NULL;
1926 int mlx4_cmd_init(struct mlx4_dev *dev)
1928 struct mlx4_priv *priv = mlx4_priv(dev);
1930 mutex_init(&priv->cmd.hcr_mutex);
1931 mutex_init(&priv->cmd.slave_cmd_mutex);
1932 sema_init(&priv->cmd.poll_sem, 1);
1933 priv->cmd.use_events = 0;
1934 priv->cmd.toggle = 1;
1936 priv->cmd.hcr = NULL;
1937 priv->mfunc.vhcr = NULL;
1939 if (!mlx4_is_slave(dev)) {
1940 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1941 MLX4_HCR_BASE, MLX4_HCR_SIZE);
1942 if (!priv->cmd.hcr) {
1943 mlx4_err(dev, "Couldn't map command register.\n");
1948 if (mlx4_is_mfunc(dev)) {
1949 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1950 &priv->mfunc.vhcr_dma,
1952 if (!priv->mfunc.vhcr) {
1953 mlx4_err(dev, "Couldn't allocate VHCR.\n");
1958 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1960 MLX4_MAILBOX_SIZE, 0);
1961 if (!priv->cmd.pool)
1967 if (mlx4_is_mfunc(dev))
1968 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1969 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1970 priv->mfunc.vhcr = NULL;
1973 if (!mlx4_is_slave(dev))
1974 iounmap(priv->cmd.hcr);
1978 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1980 struct mlx4_priv *priv = mlx4_priv(dev);
1983 if (mlx4_is_master(dev)) {
1984 flush_workqueue(priv->mfunc.master.comm_wq);
1985 destroy_workqueue(priv->mfunc.master.comm_wq);
1986 for (i = 0; i < dev->num_slaves; i++) {
1987 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1988 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1990 kfree(priv->mfunc.master.slave_state);
1991 kfree(priv->mfunc.master.vf_admin);
1992 kfree(priv->mfunc.master.vf_oper);
1995 iounmap(priv->mfunc.comm);
1998 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2000 struct mlx4_priv *priv = mlx4_priv(dev);
2002 pci_pool_destroy(priv->cmd.pool);
2004 if (!mlx4_is_slave(dev))
2005 iounmap(priv->cmd.hcr);
2006 if (mlx4_is_mfunc(dev))
2007 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2008 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2009 priv->mfunc.vhcr = NULL;
2013 * Switch to using events to issue FW commands (can only be called
2014 * after event queue for command events has been initialized).
2016 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2018 struct mlx4_priv *priv = mlx4_priv(dev);
2022 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2023 sizeof (struct mlx4_cmd_context),
2025 if (!priv->cmd.context)
2028 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2029 priv->cmd.context[i].token = i;
2030 priv->cmd.context[i].next = i + 1;
2033 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2034 priv->cmd.free_head = 0;
2036 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2037 spin_lock_init(&priv->cmd.context_lock);
2039 for (priv->cmd.token_mask = 1;
2040 priv->cmd.token_mask < priv->cmd.max_cmds;
2041 priv->cmd.token_mask <<= 1)
2043 --priv->cmd.token_mask;
2045 down(&priv->cmd.poll_sem);
2046 priv->cmd.use_events = 1;
2052 * Switch back to polling (used when shutting down the device)
2054 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2056 struct mlx4_priv *priv = mlx4_priv(dev);
2059 priv->cmd.use_events = 0;
2061 for (i = 0; i < priv->cmd.max_cmds; ++i)
2062 down(&priv->cmd.event_sem);
2064 kfree(priv->cmd.context);
2066 up(&priv->cmd.poll_sem);
2069 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2071 struct mlx4_cmd_mailbox *mailbox;
2073 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2075 return ERR_PTR(-ENOMEM);
2077 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2079 if (!mailbox->buf) {
2081 return ERR_PTR(-ENOMEM);
2086 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2088 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2089 struct mlx4_cmd_mailbox *mailbox)
2094 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2097 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2099 u32 mlx4_comm_get_version(void)
2101 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2104 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u8 *mac)
2106 struct mlx4_priv *priv = mlx4_priv(dev);
2107 struct mlx4_vport_state *s_info;
2109 if (!mlx4_is_master(dev))
2110 return -EPROTONOSUPPORT;
2112 if ((vf <= 0) || (vf > dev->num_vfs)) {
2113 mlx4_err(dev, "Bad vf number:%d (max vf activated: %d)\n", vf, dev->num_vfs);
2117 s_info = &priv->mfunc.master.vf_admin[vf].vport[port];
2118 s_info->mac = mlx4_mac_to_u64(mac);
2119 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2120 vf, port, s_info->mac);
2123 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2125 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2127 struct mlx4_priv *priv = mlx4_priv(dev);
2128 struct mlx4_vport_state *s_info;
2130 if ((!mlx4_is_master(dev)) ||
2131 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_ESWITCH_SUPPORT))
2132 return -EPROTONOSUPPORT;
2134 if ((vf <= 0) || (vf > dev->num_vfs) || (vlan > 4095) || (qos > 7))
2137 s_info = &priv->mfunc.master.vf_admin[vf].vport[port];
2138 if ((0 == vlan) && (0 == qos))
2139 s_info->default_vlan = MLX4_VGT;
2141 s_info->default_vlan = vlan;
2142 s_info->default_qos = qos;
2145 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2147 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2149 struct mlx4_priv *priv = mlx4_priv(dev);
2150 struct mlx4_vport_state *s_info;
2152 if ((!mlx4_is_master(dev)) ||
2153 !(dev->caps.flags & MLX4_DEV_CAP_FLAG_ESWITCH_SUPPORT))
2154 return -EPROTONOSUPPORT;
2156 if ((vf <= 0) || (vf > dev->num_vfs))
2159 s_info = &priv->mfunc.master.vf_admin[vf].vport[port];
2160 s_info->spoofchk = setting;
2164 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);