sys/ofed/drivers/net/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/kmod.h>
  37 /*
  38  * kmod.h must be included before module.h since it includes (indirectly) sys/module.h
  39  * To use the FBSD macro sys/module.h should define MODULE_VERSION before linux/module does.
  40 */
  41 #include <linux/module.h>
  42 #include <linux/errno.h>
  43 #include <linux/pci.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/slab.h>
  46 #include <linux/io-mapping.h>
  47 #include <linux/delay.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/string.h>
  50 #include <linux/fs.h>
  51
  52 #include <linux/mlx4/device.h>
  53 #include <linux/mlx4/doorbell.h>
  54
  55 #include "mlx4.h"
  56 #include "fw.h"
  57 #include "icm.h"
  58 #include "mlx4_stats.h"
  59
  60 MODULE_AUTHOR("Roland Dreier");
  61 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  62 MODULE_LICENSE("Dual BSD/GPL");
  63
  64 struct workqueue_struct *mlx4_wq;
  65
  66 #ifdef CONFIG_MLX4_DEBUG
  67
  68 int mlx4_debug_level = 0;
  69 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  70 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  71
  72 #endif /* CONFIG_MLX4_DEBUG */
  73
  74 #ifdef CONFIG_PCI_MSI
  75
  76 static int msi_x = 1;
  77 module_param(msi_x, int, 0444);
  78 MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x (non-SRIOV only)");
  79
  80 #else /* CONFIG_PCI_MSI */
  81
  82 #define msi_x (0)
  83
  84 #endif /* CONFIG_PCI_MSI */
  85
  86 static int enable_sys_tune = 0;
  87 module_param(enable_sys_tune, int, 0444);
  88 MODULE_PARM_DESC(enable_sys_tune, "Tune the cpu's for better performance (default 0)");
  89
  90 int mlx4_blck_lb = 1;
  91 module_param_named(block_loopback, mlx4_blck_lb, int, 0644);
  92 MODULE_PARM_DESC(block_loopback, "Block multicast loopback packets if > 0 "
  93                                  "(default: 1)");
  94 enum {
  95         DEFAULT_DOMAIN  = 0,
  96         BDF_STR_SIZE    = 8, /* bb:dd.f- */
  97         DBDF_STR_SIZE   = 13 /* mmmm:bb:dd.f- */
  98 };
  99
 100 enum {
 101         NUM_VFS,
 102         PROBE_VF,
 103         PORT_TYPE_ARRAY
 104 };
 105
 106 enum {
 107         VALID_DATA,
 108         INVALID_DATA,
 109         INVALID_STR
 110 };
 111
 112 struct param_data {
 113         int                             id;
 114         struct mlx4_dbdf2val_lst        dbdf2val;
 115 };
 116
 117 static struct param_data num_vfs = {
 118         .id             = NUM_VFS,
 119         .dbdf2val = {
 120                 .name           = "num_vfs param",
 121                 .num_vals       = 1,
 122                 .def_val        = {0},
 123                 .range          = {0, MLX4_MAX_NUM_VF}
 124         }
 125 };
 126 module_param_string(num_vfs, num_vfs.dbdf2val.str,
 127                     sizeof(num_vfs.dbdf2val.str), 0444);
 128 MODULE_PARM_DESC(num_vfs,
 129                  "Either single value (e.g. '5') to define uniform num_vfs value for all devices functions\n"
 130                  "\t\tor a string to map device function numbers to their num_vfs values (e.g. '0000:04:00.0-5,002b:1c:0b.a-15').\n"
 131                  "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for num_vfs value (e.g. 15).");
 132
 133 static struct param_data probe_vf = {
 134         .id             = PROBE_VF,
 135         .dbdf2val = {
 136                 .name           = "probe_vf param",
 137                 .num_vals       = 1,
 138                 .def_val        = {0},
 139                 .range          = {0, MLX4_MAX_NUM_VF}
 140         }
 141 };
 142 module_param_string(probe_vf, probe_vf.dbdf2val.str,
 143                     sizeof(probe_vf.dbdf2val.str), 0444);
 144 MODULE_PARM_DESC(probe_vf,
 145                  "Either single value (e.g. '3') to define uniform number of VFs to probe by the pf driver for all devices functions\n"
 146                  "\t\tor a string to map device function numbers to their probe_vf values (e.g. '0000:04:00.0-3,002b:1c:0b.a-13').\n"
 147                  "\t\tHexadecimal digits for the device function (e.g. 002b:1c:0b.a) and decimal for probe_vf value (e.g. 13).");
 148
 149 int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
 150
 151 module_param_named(log_num_mgm_entry_size,
 152                         mlx4_log_num_mgm_entry_size, int, 0444);
 153 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
 154                                          " of qp per mcg, for example:"
 155                                          " 10 gives 248.range: 7 <="
 156                                          " log_num_mgm_entry_size <= 12."
 157                                          " To activate device managed"
 158                                          " flow steering when available, set to -1");
 159
 160 static int high_rate_steer;
 161 module_param(high_rate_steer, int, 0444);
 162 MODULE_PARM_DESC(high_rate_steer, "Enable steering mode for higher packet rate"
 163                                   " (default off)");
 164
 165 static int fast_drop;
 166 module_param_named(fast_drop, fast_drop, int, 0444);
 167 MODULE_PARM_DESC(fast_drop,
 168                  "Enable fast packet drop when no recieve WQEs are posted");
 169
 170 int mlx4_enable_64b_cqe_eqe = 1;
 171 module_param_named(enable_64b_cqe_eqe, mlx4_enable_64b_cqe_eqe, int, 0644);
 172 MODULE_PARM_DESC(enable_64b_cqe_eqe,
 173                  "Enable 64 byte CQEs/EQEs when the the FW supports this if non-zero (default: 1)");
 174
 175 #define HCA_GLOBAL_CAP_MASK            0
 176
 177 #define PF_CONTEXT_BEHAVIOUR_MASK       MLX4_FUNC_CAP_64B_EQE_CQE
 178
 179 static char mlx4_version[] __devinitdata =
 180         DRV_NAME ": Mellanox ConnectX core driver v"
 181         DRV_VERSION " (" DRV_RELDATE ")\n";
 182
 183 static int log_num_mac = 7;
 184 module_param_named(log_num_mac, log_num_mac, int, 0444);
 185 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 186
 187 static int log_num_vlan;
 188 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 189 MODULE_PARM_DESC(log_num_vlan,
 190         "(Obsolete) Log2 max number of VLANs per ETH port (0-7)");
 191 /* Log2 max number of VLANs per ETH port (0-7) */
 192 #define MLX4_LOG_NUM_VLANS 7
 193
 194 int log_mtts_per_seg = ilog2(1);
 195 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 196 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
 197                  "(0-7) (default: 0)");
 198
 199 static struct param_data port_type_array = {
 200         .id             = PORT_TYPE_ARRAY,
 201         .dbdf2val = {
 202                 .name           = "port_type_array param",
 203                 .num_vals       = 2,
 204                 .def_val        = {MLX4_PORT_TYPE_ETH, MLX4_PORT_TYPE_ETH},
 205                 .range          = {MLX4_PORT_TYPE_IB, MLX4_PORT_TYPE_NA}
 206         }
 207 };
 208 module_param_string(port_type_array, port_type_array.dbdf2val.str,
 209                     sizeof(port_type_array.dbdf2val.str), 0444);
 210 MODULE_PARM_DESC(port_type_array,
 211                  "Either pair of values (e.g. '1,2') to define uniform port1/port2 types configuration for all devices functions\n"
 212                  "\t\tor a string to map device function numbers to their pair of port types values (e.g. '0000:04:00.0-1;2,002b:1c:0b.a-1;1').\n"
 213                  "\t\tValid port types: 1-ib, 2-eth, 3-auto, 4-N/A\n"
 214                  "\t\tIn case that only one port is available use the N/A port type for port2 (e.g '1,4').");
 215
 216
 217 struct mlx4_port_config {
 218         struct list_head list;
 219         enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
 220         struct pci_dev *pdev;
 221 };
 222
 223 #define MLX4_LOG_NUM_MTT 20
 224 /* We limit to 30 as of a bit map issue which uses int and not uint.
 225      see mlx4_buddy_init -> bitmap_zero which gets int.
 226 */
 227 #define MLX4_MAX_LOG_NUM_MTT 30
 228 static struct mlx4_profile mod_param_profile = {
 229         .num_qp         = 19,
 230         .num_srq        = 16,
 231         .rdmarc_per_qp  = 4,
 232         .num_cq         = 16,
 233         .num_mcg        = 13,
 234         .num_mpt        = 19,
 235         .num_mtt_segs   = 0, /* max(20, 2*MTTs for host memory)) */
 236 };
 237
 238 module_param_named(log_num_qp, mod_param_profile.num_qp, int, 0444);
 239 MODULE_PARM_DESC(log_num_qp, "log maximum number of QPs per HCA (default: 19)");
 240
 241 module_param_named(log_num_srq, mod_param_profile.num_srq, int, 0444);
 242 MODULE_PARM_DESC(log_num_srq, "log maximum number of SRQs per HCA "
 243                  "(default: 16)");
 244
 245 module_param_named(log_rdmarc_per_qp, mod_param_profile.rdmarc_per_qp, int,
 246                    0444);
 247 MODULE_PARM_DESC(log_rdmarc_per_qp, "log number of RDMARC buffers per QP "
 248                  "(default: 4)");
 249
 250 module_param_named(log_num_cq, mod_param_profile.num_cq, int, 0444);
 251 MODULE_PARM_DESC(log_num_cq, "log maximum number of CQs per HCA (default: 16)");
 252
 253 module_param_named(log_num_mcg, mod_param_profile.num_mcg, int, 0444);
 254 MODULE_PARM_DESC(log_num_mcg, "log maximum number of multicast groups per HCA "
 255                  "(default: 13)");
 256
 257 module_param_named(log_num_mpt, mod_param_profile.num_mpt, int, 0444);
 258 MODULE_PARM_DESC(log_num_mpt,
 259                  "log maximum number of memory protection table entries per "
 260                  "HCA (default: 19)");
 261
 262 module_param_named(log_num_mtt, mod_param_profile.num_mtt_segs, int, 0444);
 263 MODULE_PARM_DESC(log_num_mtt,
 264                  "log maximum number of memory translation table segments per "
 265                  "HCA (default: max(20, 2*MTTs for register all of the host memory limited to 30))");
 266
 267 enum {
 268         MLX4_IF_STATE_BASIC,
 269         MLX4_IF_STATE_EXTENDED
 270 };
 271
 272 static inline u64 dbdf_to_u64(int domain, int bus, int dev, int fn)
 273 {
 274         return (domain << 20) | (bus << 12) | (dev << 4) | fn;
 275 }
 276
 277 static inline void pr_bdf_err(const char *dbdf, const char *pname)
 278 {
 279         pr_warn("mlx4_core: '%s' is not valid bdf in '%s'\n", dbdf, pname);
 280 }
 281
 282 static inline void pr_val_err(const char *dbdf, const char *pname,
 283                               const char *val)
 284 {
 285         pr_warn("mlx4_core: value '%s' of bdf '%s' in '%s' is not valid\n"
 286                 , val, dbdf, pname);
 287 }
 288
 289 static inline void pr_out_of_range_bdf(const char *dbdf, int val,
 290                                        struct mlx4_dbdf2val_lst *dbdf2val)
 291 {
 292         pr_warn("mlx4_core: value %d in bdf '%s' of '%s' is out of its valid range (%d,%d)\n"
 293                 , val, dbdf, dbdf2val->name , dbdf2val->range.min,
 294                 dbdf2val->range.max);
 295 }
 296
 297 static inline void pr_out_of_range(struct mlx4_dbdf2val_lst *dbdf2val)
 298 {
 299         pr_warn("mlx4_core: value of '%s' is out of its valid range (%d,%d)\n"
 300                 , dbdf2val->name , dbdf2val->range.min, dbdf2val->range.max);
 301 }
 302
 303 static inline int is_in_range(int val, struct mlx4_range *r)
 304 {
 305         return (val >= r->min && val <= r->max);
 306 }
 307
 308 static int update_defaults(struct param_data *pdata)
 309 {
 310         long int val[MLX4_MAX_BDF_VALS];
 311         int ret;
 312         char *t, *p = pdata->dbdf2val.str;
 313         char sval[32];
 314         int val_len;
 315
 316         if (!strlen(p) || strchr(p, ':') || strchr(p, '.') || strchr(p, ';'))
 317                 return INVALID_STR;
 318
 319         switch (pdata->id) {
 320         case PORT_TYPE_ARRAY:
 321                 t = strchr(p, ',');
 322                 if (!t || t == p || (t - p) > sizeof(sval))
 323                         return INVALID_STR;
 324
 325                 val_len = t - p;
 326                 strncpy(sval, p, val_len);
 327                 sval[val_len] = 0;
 328
 329                 ret = kstrtol(sval, 0, &val[0]);
 330                 if (ret == -EINVAL)
 331                         return INVALID_STR;
 332                 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) {
 333                         pr_out_of_range(&pdata->dbdf2val);
 334                         return INVALID_DATA;
 335                 }
 336
 337                 ret = kstrtol(t + 1, 0, &val[1]);
 338                 if (ret == -EINVAL)
 339                         return INVALID_STR;
 340                 if (ret || !is_in_range(val[1], &pdata->dbdf2val.range)) {
 341                         pr_out_of_range(&pdata->dbdf2val);
 342                         return INVALID_DATA;
 343                 }
 344
 345                 pdata->dbdf2val.tbl[0].val[0] = val[0];
 346                 pdata->dbdf2val.tbl[0].val[1] = val[1];
 347                 break;
 348
 349         case NUM_VFS:
 350         case PROBE_VF:
 351                 ret = kstrtol(p, 0, &val[0]);
 352                 if (ret == -EINVAL)
 353                         return INVALID_STR;
 354                 if (ret || !is_in_range(val[0], &pdata->dbdf2val.range)) {
 355                         pr_out_of_range(&pdata->dbdf2val);
 356                         return INVALID_DATA;
 357                 }
 358                 pdata->dbdf2val.tbl[0].val[0] = val[0];
 359                 break;
 360         }
 361         pdata->dbdf2val.tbl[1].dbdf = MLX4_ENDOF_TBL;
 362
 363         return VALID_DATA;
 364 }
 365
 366 int mlx4_fill_dbdf2val_tbl(struct mlx4_dbdf2val_lst *dbdf2val_lst)
 367 {
 368         int domain, bus, dev, fn;
 369         u64 dbdf;
 370         char *p, *t, *v;
 371         char tmp[32];
 372         char sbdf[32];
 373         char sep = ',';
 374         int j, k, str_size, i = 1;
 375         int prfx_size;
 376
 377         p = dbdf2val_lst->str;
 378
 379         for (j = 0; j < dbdf2val_lst->num_vals; j++)
 380                 dbdf2val_lst->tbl[0].val[j] = dbdf2val_lst->def_val[j];
 381         dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL;
 382
 383         str_size = strlen(dbdf2val_lst->str);
 384
 385         if (str_size == 0)
 386                 return 0;
 387
 388         while (strlen(p)) {
 389                 prfx_size = BDF_STR_SIZE;
 390                 sbdf[prfx_size] = 0;
 391                 strncpy(sbdf, p, prfx_size);
 392                 domain = DEFAULT_DOMAIN;
 393                 if (sscanf(sbdf, "%02x:%02x.%x-", &bus, &dev, &fn) != 3) {
 394                         prfx_size = DBDF_STR_SIZE;
 395                         sbdf[prfx_size] = 0;
 396                         strncpy(sbdf, p, prfx_size);
 397                         if (sscanf(sbdf, "%04x:%02x:%02x.%x-", &domain, &bus,
 398                                    &dev, &fn) != 4) {
 399                                 pr_bdf_err(sbdf, dbdf2val_lst->name);
 400                                 goto err;
 401                         }
 402                         sprintf(tmp, "%04x:%02x:%02x.%x-", domain, bus, dev,
 403                                 fn);
 404                 } else {
 405                         sprintf(tmp, "%02x:%02x.%x-", bus, dev, fn);
 406                 }
 407
 408                 if (strnicmp(sbdf, tmp, sizeof(tmp))) {
 409                         pr_bdf_err(sbdf, dbdf2val_lst->name);
 410                         goto err;
 411                 }
 412
 413                 dbdf = dbdf_to_u64(domain, bus, dev, fn);
 414
 415                 for (j = 1; j < i; j++)
 416                         if (dbdf2val_lst->tbl[j].dbdf == dbdf) {
 417                                 pr_warn("mlx4_core: in '%s', %s appears multiple times\n"
 418                                         , dbdf2val_lst->name, sbdf);
 419                                 goto err;
 420                         }
 421
 422                 if (i >= MLX4_DEVS_TBL_SIZE) {
 423                         pr_warn("mlx4_core: Too many devices in '%s'\n"
 424                                 , dbdf2val_lst->name);
 425                         goto err;
 426                 }
 427
 428                 p += prfx_size;
 429                 t = strchr(p, sep);
 430                 t = t ? t : p + strlen(p);
 431                 if (p >= t) {
 432                         pr_val_err(sbdf, dbdf2val_lst->name, "");
 433                         goto err;
 434                 }
 435
 436                 for (k = 0; k < dbdf2val_lst->num_vals; k++) {
 437                         char sval[32];
 438                         long int val;
 439                         int ret, val_len;
 440                         char vsep = ';';
 441
 442                         v = (k == dbdf2val_lst->num_vals - 1) ? t : strchr(p, vsep);
 443                         if (!v || v > t || v == p || (v - p) > sizeof(sval)) {
 444                                 pr_val_err(sbdf, dbdf2val_lst->name, p);
 445                                 goto err;
 446                         }
 447                         val_len = v - p;
 448                         strncpy(sval, p, val_len);
 449                         sval[val_len] = 0;
 450
 451                         ret = kstrtol(sval, 0, &val);
 452                         if (ret) {
 453                                 if (strchr(p, vsep))
 454                                         pr_warn("mlx4_core: too many vals in bdf '%s' of '%s'\n"
 455                                                 , sbdf, dbdf2val_lst->name);
 456                                 else
 457                                         pr_val_err(sbdf, dbdf2val_lst->name,
 458                                                    sval);
 459                                 goto err;
 460                         }
 461                         if (!is_in_range(val, &dbdf2val_lst->range)) {
 462                                 pr_out_of_range_bdf(sbdf, val, dbdf2val_lst);
 463                                 goto err;
 464                         }
 465
 466                         dbdf2val_lst->tbl[i].val[k] = val;
 467                         p = v;
 468                         if (p[0] == vsep)
 469                                 p++;
 470                 }
 471
 472                 dbdf2val_lst->tbl[i].dbdf = dbdf;
 473                 if (strlen(p)) {
 474                         if (p[0] != sep) {
 475                                 pr_warn("mlx4_core: expect separator '%c' before '%s' in '%s'\n"
 476                                         , sep, p, dbdf2val_lst->name);
 477                                 goto err;
 478                         }
 479                         p++;
 480                 }
 481                 i++;
 482                 if (i < MLX4_DEVS_TBL_SIZE)
 483                         dbdf2val_lst->tbl[i].dbdf = MLX4_ENDOF_TBL;
 484         }
 485
 486         return 0;
 487
 488 err:
 489         dbdf2val_lst->tbl[1].dbdf = MLX4_ENDOF_TBL;
 490         pr_warn("mlx4_core: The value of '%s' is incorrect. The value is discarded!\n"
 491                 , dbdf2val_lst->name);
 492
 493         return -EINVAL;
 494 }
 495 EXPORT_SYMBOL(mlx4_fill_dbdf2val_tbl);
 496
 497 int mlx4_get_val(struct mlx4_dbdf2val *tbl, struct pci_dev *pdev, int idx,
 498                  int *val)
 499 {
 500         u64 dbdf;
 501         int i = 1;
 502
 503         *val = tbl[0].val[idx];
 504         if (!pdev)
 505                 return -EINVAL;
 506
 507         dbdf = dbdf_to_u64(pci_get_domain(pdev->dev.bsddev), pci_get_bus(pdev->dev.bsddev),
 508                            PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 509
 510         while ((i < MLX4_DEVS_TBL_SIZE) && (tbl[i].dbdf != MLX4_ENDOF_TBL)) {
 511                 if (tbl[i].dbdf == dbdf) {
 512                         *val = tbl[i].val[idx];
 513                         return 0;
 514                 }
 515                 i++;
 516         }
 517
 518         return 0;
 519 }
 520 EXPORT_SYMBOL(mlx4_get_val);
 521
 522 static void process_mod_param_profile(struct mlx4_profile *profile)
 523 {
 524         vm_size_t hwphyssz;
 525         hwphyssz = 0;
 526         TUNABLE_ULONG_FETCH("hw.realmem", (u_long *) &hwphyssz);
 527
 528         profile->num_qp        = 1 << mod_param_profile.num_qp;
 529         profile->num_srq       = 1 << mod_param_profile.num_srq;
 530         profile->rdmarc_per_qp = 1 << mod_param_profile.rdmarc_per_qp;
 531         profile->num_cq        = 1 << mod_param_profile.num_cq;
 532         profile->num_mcg       = 1 << mod_param_profile.num_mcg;
 533         profile->num_mpt       = 1 << mod_param_profile.num_mpt;
 534         /*
 535          * We want to scale the number of MTTs with the size of the
 536          * system memory, since it makes sense to register a lot of
 537          * memory on a system with a lot of memory.  As a heuristic,
 538          * make sure we have enough MTTs to register twice the system
 539          * memory (with PAGE_SIZE entries).
 540          *
 541          * This number has to be a power of two and fit into 32 bits
 542          * due to device limitations. We cap this at 2^30 as of bit map
 543          * limitation to work with int instead of uint (mlx4_buddy_init -> bitmap_zero)
 544          * That limits us to 4TB of memory registration per HCA with
 545          * 4KB pages, which is probably OK for the next few months.
 546          */
 547         if (mod_param_profile.num_mtt_segs)
 548                 profile->num_mtt_segs = 1 << mod_param_profile.num_mtt_segs;
 549         else {
 550                 profile->num_mtt_segs =
 551                         roundup_pow_of_two(max_t(unsigned,
 552                                                 1 << (MLX4_LOG_NUM_MTT - log_mtts_per_seg),
 553                                                 min(1UL <<
 554                                                 (MLX4_MAX_LOG_NUM_MTT -
 555                                                 log_mtts_per_seg),
 556                                                 (hwphyssz << 1)
 557                                                 >> log_mtts_per_seg)));
 558                 /* set the actual value, so it will be reflected to the user
 559                    using the sysfs */
 560                 mod_param_profile.num_mtt_segs = ilog2(profile->num_mtt_segs);
 561         }
 562 }
 563
 564 int mlx4_check_port_params(struct mlx4_dev *dev,
 565                            enum mlx4_port_type *port_type)
 566 {
 567         int i;
 568
 569         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 570                 if (port_type[i] != port_type[i + 1]) {
 571                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 572                                 mlx4_err(dev, "Only same port types supported "
 573                                          "on this HCA, aborting.\n");
 574                                 return -EINVAL;
 575                         }
 576                 }
 577         }
 578
 579         for (i = 0; i < dev->caps.num_ports; i++) {
 580                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 581                         mlx4_err(dev, "Requested port type for port %d is not "
 582                                       "supported on this HCA\n", i + 1);
 583                         return -EINVAL;
 584                 }
 585         }
 586         return 0;
 587 }
 588
 589 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 590 {
 591         int i;
 592
 593         for (i = 1; i <= dev->caps.num_ports; ++i)
 594                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 595 }
 596
 597 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 598 {
 599         int err;
 600         int i;
 601
 602         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 603         if (err) {
 604                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 605                 return err;
 606         }
 607
 608         if (dev_cap->min_page_sz > PAGE_SIZE) {
 609                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 610                          "kernel PAGE_SIZE of %d, aborting.\n",
 611                          dev_cap->min_page_sz, PAGE_SIZE);
 612                 return -ENODEV;
 613         }
 614         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 615                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 616                          "aborting.\n",
 617                          dev_cap->num_ports, MLX4_MAX_PORTS);
 618                 return -ENODEV;
 619         }
 620
 621         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 622                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 623                          "PCI resource 2 size of 0x%llx, aborting.\n",
 624                          dev_cap->uar_size,
 625                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 626                 return -ENODEV;
 627         }
 628
 629         dev->caps.num_ports          = dev_cap->num_ports;
 630         dev->phys_caps.num_phys_eqs  = MLX4_MAX_EQ_NUM;
 631         for (i = 1; i <= dev->caps.num_ports; ++i) {
 632                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 633                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 634                 dev->phys_caps.gid_phys_table_len[i]  = dev_cap->max_gids[i];
 635                 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
 636                 /* set gid and pkey table operating lengths by default
 637                  * to non-sriov values */
 638                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 639                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 640                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 641                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 642                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 643                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 644                 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
 645                 dev->caps.default_sense[i] = dev_cap->default_sense[i];
 646                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 647                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 648                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 649                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 650         }
 651
 652         dev->caps.uar_page_size      = PAGE_SIZE;
 653         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 654         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 655         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 656         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 657         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 658         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 659         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 660         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 661         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 662         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 663         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 664         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 665         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 666         /*
 667          * Subtract 1 from the limit because we need to allocate a
 668          * spare CQE to enable resizing the CQ
 669          */
 670         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 671         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 672         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 673         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 674         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 675
 676         /* The first 128 UARs are used for EQ doorbells */
 677         dev->caps.reserved_uars      = max_t(int, 128, dev_cap->reserved_uars);
 678         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 679         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 680                                         dev_cap->reserved_xrcds : 0;
 681         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 682                                         dev_cap->max_xrcds : 0;
 683         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 684
 685         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 686         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 687         dev->caps.flags              = dev_cap->flags;
 688         dev->caps.flags2             = dev_cap->flags2;
 689         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 690         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 691         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 692         dev->caps.cq_timestamp       = dev_cap->timestamp_support;
 693         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 694         dev->caps.max_rss_tbl_sz     = dev_cap->max_rss_tbl_sz;
 695
 696         /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
 697         if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
 698                 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 699         /* Don't do sense port on multifunction devices (for now at least) */
 700         if (mlx4_is_mfunc(dev))
 701                 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
 702
 703         dev->caps.log_num_macs  = log_num_mac;
 704         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 705
 706         dev->caps.fast_drop     = fast_drop ?
 707                                   !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FAST_DROP) :
 708                                   0;
 709
 710         for (i = 1; i <= dev->caps.num_ports; ++i) {
 711                 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
 712                 if (dev->caps.supported_type[i]) {
 713                         /* if only ETH is supported - assign ETH */
 714                         if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
 715                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 716                         /* if only IB is supported, assign IB */
 717                         else if (dev->caps.supported_type[i] ==
 718                                  MLX4_PORT_TYPE_IB)
 719                                 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 720                         else {
 721                                 /*
 722                                  * if IB and ETH are supported, we set the port
 723                                  * type according to user selection of port type;
 724                                  * if there is no user selection, take the FW hint
 725                                  */
 726                                 int pta;
 727                                 mlx4_get_val(port_type_array.dbdf2val.tbl,
 728                                              pci_physfn(dev->pdev), i - 1,
 729                                              &pta);
 730                                 if (pta == MLX4_PORT_TYPE_NONE) {
 731                                         dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
 732                                                 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
 733                                 } else if (pta == MLX4_PORT_TYPE_NA) {
 734                                         mlx4_err(dev, "Port %d is valid port. "
 735                                                  "It is not allowed to configure its type to N/A(%d)\n",
 736                                                  i, MLX4_PORT_TYPE_NA);
 737                                         return -EINVAL;
 738                                 } else {
 739                                         dev->caps.port_type[i] = pta;
 740                                 }
 741                         }
 742                 }
 743                 /*
 744                  * Link sensing is allowed on the port if 3 conditions are true:
 745                  * 1. Both protocols are supported on the port.
 746                  * 2. Different types are supported on the port
 747                  * 3. FW declared that it supports link sensing
 748                  */
 749                 mlx4_priv(dev)->sense.sense_allowed[i] =
 750                         ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
 751                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
 752                          (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
 753
 754                 /* Disablling auto sense for default Eth ports support */
 755                 mlx4_priv(dev)->sense.sense_allowed[i] = 0;
 756
 757                 /*
 758                  * If "default_sense" bit is set, we move the port to "AUTO" mode
 759                  * and perform sense_port FW command to try and set the correct
 760                  * port type from beginning
 761                  */
 762                 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
 763                         enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
 764                         dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
 765                         mlx4_SENSE_PORT(dev, i, &sensed_port);
 766                         if (sensed_port != MLX4_PORT_TYPE_NONE)
 767                                 dev->caps.port_type[i] = sensed_port;
 768                 } else {
 769                         dev->caps.possible_type[i] = dev->caps.port_type[i];
 770                 }
 771
 772                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 773                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 774                         mlx4_warn(dev, "Requested number of MACs is too much "
 775                                   "for port %d, reducing to %d.\n",
 776                                   i, 1 << dev->caps.log_num_macs);
 777                 }
 778                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 779                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 780                         mlx4_warn(dev, "Requested number of VLANs is too much "
 781                                   "for port %d, reducing to %d.\n",
 782                                   i, 1 << dev->caps.log_num_vlans);
 783                 }
 784         }
 785
 786         dev->caps.max_basic_counters = dev_cap->max_basic_counters;
 787         dev->caps.max_extended_counters = dev_cap->max_extended_counters;
 788         /* support extended counters if available */
 789         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS_EXT)
 790                 dev->caps.max_counters = dev->caps.max_extended_counters;
 791         else
 792                 dev->caps.max_counters = dev->caps.max_basic_counters;
 793
 794         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 795         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 796                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 797                 (1 << dev->caps.log_num_macs) *
 798                 (1 << dev->caps.log_num_vlans) *
 799                 dev->caps.num_ports;
 800         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 801
 802         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 803                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 804                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 805                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 806
 807         dev->caps.sync_qp = dev_cap->sync_qp;
 808         if (dev->pdev->device == 0x1003)
 809                 dev->caps.cq_flags |= MLX4_DEV_CAP_CQ_FLAG_IO;
 810
 811         dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
 812
 813         if (!mlx4_enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
 814                 if (dev_cap->flags &
 815                     (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
 816                         mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
 817                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
 818                         dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
 819                 }
 820         }
 821
 822         if ((dev->caps.flags &
 823             (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
 824             mlx4_is_master(dev))
 825                 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
 826
 827         if (!mlx4_is_slave(dev)) {
 828                 for (i = 0; i < dev->caps.num_ports; ++i)
 829                         dev->caps.def_counter_index[i] = i << 1;
 830         }
 831
 832         return 0;
 833 }
 834 /*The function checks if there are live vf, return the num of them*/
 835 static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
 836 {
 837         struct mlx4_priv *priv = mlx4_priv(dev);
 838         struct mlx4_slave_state *s_state;
 839         int i;
 840         int ret = 0;
 841
 842         for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
 843                 s_state = &priv->mfunc.master.slave_state[i];
 844                 if (s_state->active && s_state->last_cmd !=
 845                     MLX4_COMM_CMD_RESET) {
 846                         mlx4_warn(dev, "%s: slave: %d is still active\n",
 847                                   __func__, i);
 848                         ret++;
 849                 }
 850         }
 851         return ret;
 852 }
 853
 854 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
 855 {
 856         u32 qk = MLX4_RESERVED_QKEY_BASE;
 857
 858         if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
 859             qpn < dev->phys_caps.base_proxy_sqpn)
 860                 return -EINVAL;
 861
 862         if (qpn >= dev->phys_caps.base_tunnel_sqpn)
 863                 /* tunnel qp */
 864                 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
 865         else
 866                 qk += qpn - dev->phys_caps.base_proxy_sqpn;
 867         *qkey = qk;
 868         return 0;
 869 }
 870 EXPORT_SYMBOL(mlx4_get_parav_qkey);
 871
 872 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
 873 {
 874         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 875
 876         if (!mlx4_is_master(dev))
 877                 return;
 878
 879         priv->virt2phys_pkey[slave][port - 1][i] = val;
 880 }
 881 EXPORT_SYMBOL(mlx4_sync_pkey_table);
 882
 883 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
 884 {
 885         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 886
 887         if (!mlx4_is_master(dev))
 888                 return;
 889
 890         priv->slave_node_guids[slave] = guid;
 891 }
 892 EXPORT_SYMBOL(mlx4_put_slave_node_guid);
 893
 894 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
 895 {
 896         struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
 897
 898         if (!mlx4_is_master(dev))
 899                 return 0;
 900
 901         return priv->slave_node_guids[slave];
 902 }
 903 EXPORT_SYMBOL(mlx4_get_slave_node_guid);
 904
 905 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
 906 {
 907         struct mlx4_priv *priv = mlx4_priv(dev);
 908         struct mlx4_slave_state *s_slave;
 909
 910         if (!mlx4_is_master(dev))
 911                 return 0;
 912
 913         s_slave = &priv->mfunc.master.slave_state[slave];
 914         return !!s_slave->active;
 915 }
 916 EXPORT_SYMBOL(mlx4_is_slave_active);
 917
 918 static void slave_adjust_steering_mode(struct mlx4_dev *dev,
 919                                        struct mlx4_dev_cap *dev_cap,
 920                                        struct mlx4_init_hca_param *hca_param)
 921 {
 922         dev->caps.steering_mode = hca_param->steering_mode;
 923         if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED)
 924                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
 925         else
 926                 dev->caps.num_qp_per_mgm =
 927                         4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
 928
 929         mlx4_dbg(dev, "Steering mode is: %s\n",
 930                  mlx4_steering_mode_str(dev->caps.steering_mode));
 931 }
 932
 933 static int mlx4_slave_cap(struct mlx4_dev *dev)
 934 {
 935         int                        err;
 936         u32                        page_size;
 937         struct mlx4_dev_cap        dev_cap;
 938         struct mlx4_func_cap       func_cap;
 939         struct mlx4_init_hca_param hca_param;
 940         int                        i;
 941
 942         memset(&hca_param, 0, sizeof(hca_param));
 943         err = mlx4_QUERY_HCA(dev, &hca_param);
 944         if (err) {
 945                 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
 946                 return err;
 947         }
 948
 949         /*fail if the hca has an unknown capability */
 950         if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
 951             HCA_GLOBAL_CAP_MASK) {
 952                 mlx4_err(dev, "Unknown hca global capabilities\n");
 953                 return -ENOSYS;
 954         }
 955
 956         mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
 957
 958         dev->caps.hca_core_clock = hca_param.hca_core_clock;
 959
 960         memset(&dev_cap, 0, sizeof(dev_cap));
 961         dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
 962         err = mlx4_dev_cap(dev, &dev_cap);
 963         if (err) {
 964                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 965                 return err;
 966         }
 967
 968         err = mlx4_QUERY_FW(dev);
 969         if (err)
 970                 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
 971
 972         if (!hca_param.mw_enable) {
 973                 dev->caps.flags      &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
 974                 dev->caps.bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
 975         }
 976
 977         page_size = ~dev->caps.page_size_cap + 1;
 978         mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
 979         if (page_size > PAGE_SIZE) {
 980                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 981                          "kernel PAGE_SIZE of %d, aborting.\n",
 982                          page_size, PAGE_SIZE);
 983                 return -ENODEV;
 984         }
 985
 986         /* slave gets uar page size from QUERY_HCA fw command */
 987         dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
 988
 989         /* TODO: relax this assumption */
 990         if (dev->caps.uar_page_size != PAGE_SIZE) {
 991                 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %d\n",
 992                          dev->caps.uar_page_size, PAGE_SIZE);
 993                 return -ENODEV;
 994         }
 995
 996         memset(&func_cap, 0, sizeof(func_cap));
 997         err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
 998         if (err) {
 999                 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
1000                           err);
1001                 return err;
1002         }
1003
1004         if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
1005             PF_CONTEXT_BEHAVIOUR_MASK) {
1006                 mlx4_err(dev, "Unknown pf context behaviour\n");
1007                 return -ENOSYS;
1008         }
1009
1010         dev->caps.num_ports             = func_cap.num_ports;
1011         dev->quotas.qp                  = func_cap.qp_quota;
1012         dev->quotas.srq                 = func_cap.srq_quota;
1013         dev->quotas.cq                  = func_cap.cq_quota;
1014         dev->quotas.mpt                 = func_cap.mpt_quota;
1015         dev->quotas.mtt                 = func_cap.mtt_quota;
1016         dev->caps.num_qps               = 1 << hca_param.log_num_qps;
1017         dev->caps.num_srqs              = 1 << hca_param.log_num_srqs;
1018         dev->caps.num_cqs               = 1 << hca_param.log_num_cqs;
1019         dev->caps.num_mpts              = 1 << hca_param.log_mpt_sz;
1020         dev->caps.num_eqs               = func_cap.max_eq;
1021         dev->caps.reserved_eqs          = func_cap.reserved_eq;
1022         dev->caps.num_pds               = MLX4_NUM_PDS;
1023         dev->caps.num_mgms              = 0;
1024         dev->caps.num_amgms             = 0;
1025
1026         if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1027                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
1028                          "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
1029                 return -ENODEV;
1030         }
1031
1032         dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1033         dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1034         dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1035         dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
1036
1037         if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
1038             !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
1039                 err = -ENOMEM;
1040                 goto err_mem;
1041         }
1042
1043         for (i = 1; i <= dev->caps.num_ports; ++i) {
1044                 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
1045                 if (err) {
1046                         mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
1047                                  " port %d, aborting (%d).\n", i, err);
1048                         goto err_mem;
1049                 }
1050                 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
1051                 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
1052                 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
1053                 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
1054                 dev->caps.def_counter_index[i - 1] = func_cap.def_counter_index;
1055
1056                 dev->caps.port_mask[i] = dev->caps.port_type[i];
1057                 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
1058                                                       &dev->caps.gid_table_len[i],
1059                                                       &dev->caps.pkey_table_len[i]);
1060                 if (err)
1061                         goto err_mem;
1062         }
1063
1064         if (dev->caps.uar_page_size * (dev->caps.num_uars -
1065                                        dev->caps.reserved_uars) >
1066                                        pci_resource_len(dev->pdev, 2)) {
1067                 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
1068                          "PCI resource 2 size of 0x%llx, aborting.\n",
1069                          dev->caps.uar_page_size * dev->caps.num_uars,
1070                          (unsigned long long) pci_resource_len(dev->pdev, 2));
1071                 err = -ENOMEM;
1072                 goto err_mem;
1073         }
1074
1075         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
1076                 dev->caps.eqe_size   = 64;
1077                 dev->caps.eqe_factor = 1;
1078         } else {
1079                 dev->caps.eqe_size   = 32;
1080                 dev->caps.eqe_factor = 0;
1081         }
1082
1083         if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
1084                 dev->caps.cqe_size   = 64;
1085                 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1086         } else {
1087                 dev->caps.cqe_size   = 32;
1088         }
1089
1090         dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1091         mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
1092
1093         slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
1094
1095         return 0;
1096
1097 err_mem:
1098         kfree(dev->caps.qp0_tunnel);
1099         kfree(dev->caps.qp0_proxy);
1100         kfree(dev->caps.qp1_tunnel);
1101         kfree(dev->caps.qp1_proxy);
1102         dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
1103                 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
1104
1105         return err;
1106 }
1107
1108 static void mlx4_request_modules(struct mlx4_dev *dev)
1109 {
1110         int port;
1111         int has_ib_port = false;
1112         int has_eth_port = false;
1113 #define EN_DRV_NAME     "mlx4_en"
1114 #define IB_DRV_NAME     "mlx4_ib"
1115
1116         for (port = 1; port <= dev->caps.num_ports; port++) {
1117                 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1118                         has_ib_port = true;
1119                 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1120                         has_eth_port = true;
1121         }
1122
1123         if (has_ib_port)
1124                 request_module_nowait(IB_DRV_NAME);
1125         if (has_eth_port)
1126                 request_module_nowait(EN_DRV_NAME);
1127 }
1128
1129 /*
1130  * Change the port configuration of the device.
1131  * Every user of this function must hold the port mutex.
1132  */
1133 int mlx4_change_port_types(struct mlx4_dev *dev,
1134                            enum mlx4_port_type *port_types)
1135 {
1136         int err = 0;
1137         int change = 0;
1138         int port;
1139
1140         for (port = 0; port <  dev->caps.num_ports; port++) {
1141                 /* Change the port type only if the new type is different
1142                  * from the current, and not set to Auto */
1143                 if (port_types[port] != dev->caps.port_type[port + 1])
1144                         change = 1;
1145         }
1146         if (change) {
1147                 mlx4_unregister_device(dev);
1148                 for (port = 1; port <= dev->caps.num_ports; port++) {
1149                         mlx4_CLOSE_PORT(dev, port);
1150                         dev->caps.port_type[port] = port_types[port - 1];
1151                         err = mlx4_SET_PORT(dev, port, -1);
1152                         if (err) {
1153                                 mlx4_err(dev, "Failed to set port %d, "
1154                                               "aborting\n", port);
1155                                 goto out;
1156                         }
1157                 }
1158                 mlx4_set_port_mask(dev);
1159                 err = mlx4_register_device(dev);
1160                 if (err) {
1161                         mlx4_err(dev, "Failed to register device\n");
1162                         goto out;
1163                 }
1164                 mlx4_request_modules(dev);
1165         }
1166
1167 out:
1168         return err;
1169 }
1170
1171 static ssize_t show_port_type(struct device *dev,
1172                               struct device_attribute *attr,
1173                               char *buf)
1174 {
1175         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1176                                                    port_attr);
1177         struct mlx4_dev *mdev = info->dev;
1178         char type[8];
1179
1180         sprintf(type, "%s",
1181                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1182                 "ib" : "eth");
1183         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1184                 sprintf(buf, "auto (%s)\n", type);
1185         else
1186                 sprintf(buf, "%s\n", type);
1187
1188         return strlen(buf);
1189 }
1190
1191 static ssize_t set_port_type(struct device *dev,
1192                              struct device_attribute *attr,
1193                              const char *buf, size_t count)
1194 {
1195         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1196                                                    port_attr);
1197         struct mlx4_dev *mdev = info->dev;
1198         struct mlx4_priv *priv = mlx4_priv(mdev);
1199         enum mlx4_port_type types[MLX4_MAX_PORTS];
1200         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1201         int i;
1202         int err = 0;
1203
1204         if (!strcmp(buf, "ib\n"))
1205                 info->tmp_type = MLX4_PORT_TYPE_IB;
1206         else if (!strcmp(buf, "eth\n"))
1207                 info->tmp_type = MLX4_PORT_TYPE_ETH;
1208         else if (!strcmp(buf, "auto\n"))
1209                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
1210         else {
1211                 mlx4_err(mdev, "%s is not supported port type\n", buf);
1212                 return -EINVAL;
1213         }
1214
1215         if ((info->tmp_type & mdev->caps.supported_type[info->port]) !=
1216             info->tmp_type) {
1217                 mlx4_err(mdev, "Requested port type for port %d is not supported on this HCA\n",
1218                          info->port);
1219                 return -EINVAL;
1220         }
1221
1222         mlx4_stop_sense(mdev);
1223         mutex_lock(&priv->port_mutex);
1224         /* Possible type is always the one that was delivered */
1225         mdev->caps.possible_type[info->port] = info->tmp_type;
1226
1227         for (i = 0; i < mdev->caps.num_ports; i++) {
1228                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1229                                         mdev->caps.possible_type[i+1];
1230                 if (types[i] == MLX4_PORT_TYPE_AUTO)
1231                         types[i] = mdev->caps.port_type[i+1];
1232         }
1233
1234         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1235             !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1236                 for (i = 1; i <= mdev->caps.num_ports; i++) {
1237                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1238                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1239                                 err = -EINVAL;
1240                         }
1241                 }
1242         }
1243         if (err) {
1244                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
1245                                "Set only 'eth' or 'ib' for both ports "
1246                                "(should be the same)\n");
1247                 goto out;
1248         }
1249
1250         mlx4_do_sense_ports(mdev, new_types, types);
1251
1252         err = mlx4_check_port_params(mdev, new_types);
1253         if (err)
1254                 goto out;
1255
1256         /* We are about to apply the changes after the configuration
1257          * was verified, no need to remember the temporary types
1258          * any more */
1259         for (i = 0; i < mdev->caps.num_ports; i++)
1260                 priv->port[i + 1].tmp_type = 0;
1261
1262         err = mlx4_change_port_types(mdev, new_types);
1263
1264 out:
1265         mlx4_start_sense(mdev);
1266         mutex_unlock(&priv->port_mutex);
1267         return err ? err : count;
1268 }
1269
1270 enum ibta_mtu {
1271         IB_MTU_256  = 1,
1272         IB_MTU_512  = 2,
1273         IB_MTU_1024 = 3,
1274         IB_MTU_2048 = 4,
1275         IB_MTU_4096 = 5
1276 };
1277
1278 static inline int int_to_ibta_mtu(int mtu)
1279 {
1280         switch (mtu) {
1281         case 256:  return IB_MTU_256;
1282         case 512:  return IB_MTU_512;
1283         case 1024: return IB_MTU_1024;
1284         case 2048: return IB_MTU_2048;
1285         case 4096: return IB_MTU_4096;
1286         default: return -1;
1287         }
1288 }
1289
1290 static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1291 {
1292         switch (mtu) {
1293         case IB_MTU_256:  return  256;
1294         case IB_MTU_512:  return  512;
1295         case IB_MTU_1024: return 1024;
1296         case IB_MTU_2048: return 2048;
1297         case IB_MTU_4096: return 4096;
1298         default: return -1;
1299         }
1300 }
1301
1302 static ssize_t show_port_ib_mtu(struct device *dev,
1303                              struct device_attribute *attr,
1304                              char *buf)
1305 {
1306         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1307                                                    port_mtu_attr);
1308         struct mlx4_dev *mdev = info->dev;
1309
1310         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1311                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1312
1313         sprintf(buf, "%d\n",
1314                         ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1315         return strlen(buf);
1316 }
1317
1318 static ssize_t set_port_ib_mtu(struct device *dev,
1319                              struct device_attribute *attr,
1320                              const char *buf, size_t count)
1321 {
1322         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1323                                                    port_mtu_attr);
1324         struct mlx4_dev *mdev = info->dev;
1325         struct mlx4_priv *priv = mlx4_priv(mdev);
1326         int err, port, mtu, ibta_mtu = -1;
1327
1328         if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1329                 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1330                 return -EINVAL;
1331         }
1332
1333         mtu = (int) simple_strtol(buf, NULL, 0);
1334         ibta_mtu = int_to_ibta_mtu(mtu);
1335
1336         if (ibta_mtu < 0) {
1337                 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1338                 return -EINVAL;
1339         }
1340
1341         mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1342
1343         mlx4_stop_sense(mdev);
1344         mutex_lock(&priv->port_mutex);
1345         mlx4_unregister_device(mdev);
1346         for (port = 1; port <= mdev->caps.num_ports; port++) {
1347                 mlx4_CLOSE_PORT(mdev, port);
1348                 err = mlx4_SET_PORT(mdev, port, -1);
1349                 if (err) {
1350                         mlx4_err(mdev, "Failed to set port %d, "
1351                                       "aborting\n", port);
1352                         goto err_set_port;
1353                 }
1354         }
1355         err = mlx4_register_device(mdev);
1356 err_set_port:
1357         mutex_unlock(&priv->port_mutex);
1358         mlx4_start_sense(mdev);
1359         return err ? err : count;
1360 }
1361
1362 static int mlx4_load_fw(struct mlx4_dev *dev)
1363 {
1364         struct mlx4_priv *priv = mlx4_priv(dev);
1365         int err, unmap_flag = 0;
1366
1367         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1368                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
1369         if (!priv->fw.fw_icm) {
1370                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
1371                 return -ENOMEM;
1372         }
1373
1374         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1375         if (err) {
1376                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
1377                 goto err_free;
1378         }
1379
1380         err = mlx4_RUN_FW(dev);
1381         if (err) {
1382                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1383                 goto err_unmap_fa;
1384         }
1385
1386         return 0;
1387
1388 err_unmap_fa:
1389         unmap_flag = mlx4_UNMAP_FA(dev);
1390         if (unmap_flag)
1391                 pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
1392
1393 err_free:
1394         if (!unmap_flag)
1395                 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1396         return err;
1397 }
1398
1399 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1400                                 int cmpt_entry_sz)
1401 {
1402         struct mlx4_priv *priv = mlx4_priv(dev);
1403         int err;
1404         int num_eqs;
1405
1406         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1407                                   cmpt_base +
1408                                   ((u64) (MLX4_CMPT_TYPE_QP *
1409                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1410                                   cmpt_entry_sz, dev->caps.num_qps,
1411                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1412                                   0, 0);
1413         if (err)
1414                 goto err;
1415
1416         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1417                                   cmpt_base +
1418                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
1419                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1420                                   cmpt_entry_sz, dev->caps.num_srqs,
1421                                   dev->caps.reserved_srqs, 0, 0);
1422         if (err)
1423                 goto err_qp;
1424
1425         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1426                                   cmpt_base +
1427                                   ((u64) (MLX4_CMPT_TYPE_CQ *
1428                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1429                                   cmpt_entry_sz, dev->caps.num_cqs,
1430                                   dev->caps.reserved_cqs, 0, 0);
1431         if (err)
1432                 goto err_srq;
1433
1434         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1435                   dev->caps.num_eqs;
1436         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1437                                   cmpt_base +
1438                                   ((u64) (MLX4_CMPT_TYPE_EQ *
1439                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1440                                   cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1441         if (err)
1442                 goto err_cq;
1443
1444         return 0;
1445
1446 err_cq:
1447         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1448
1449 err_srq:
1450         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1451
1452 err_qp:
1453         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1454
1455 err:
1456         return err;
1457 }
1458
1459 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1460                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
1461 {
1462         struct mlx4_priv *priv = mlx4_priv(dev);
1463         u64 aux_pages;
1464         int num_eqs;
1465         int err, unmap_flag = 0;
1466
1467         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1468         if (err) {
1469                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1470                 return err;
1471         }
1472
1473         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1474                  (unsigned long long) icm_size >> 10,
1475                  (unsigned long long) aux_pages << 2);
1476
1477         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1478                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
1479         if (!priv->fw.aux_icm) {
1480                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1481                 return -ENOMEM;
1482         }
1483
1484         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1485         if (err) {
1486                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1487                 goto err_free_aux;
1488         }
1489
1490         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1491         if (err) {
1492                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1493                 goto err_unmap_aux;
1494         }
1495
1496
1497         num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1498                    dev->caps.num_eqs;
1499         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1500                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
1501                                   num_eqs, num_eqs, 0, 0);
1502         if (err) {
1503                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1504                 goto err_unmap_cmpt;
1505         }
1506
1507         /*
1508          * Reserved MTT entries must be aligned up to a cacheline
1509          * boundary, since the FW will write to them, while the driver
1510          * writes to all other MTT entries. (The variable
1511          * dev->caps.mtt_entry_sz below is really the MTT segment
1512          * size, not the raw entry size)
1513          */
1514         dev->caps.reserved_mtts =
1515                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1516                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1517
1518         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1519                                   init_hca->mtt_base,
1520                                   dev->caps.mtt_entry_sz,
1521                                   dev->caps.num_mtts,
1522                                   dev->caps.reserved_mtts, 1, 0);
1523         if (err) {
1524                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1525                 goto err_unmap_eq;
1526         }
1527
1528         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1529                                   init_hca->dmpt_base,
1530                                   dev_cap->dmpt_entry_sz,
1531                                   dev->caps.num_mpts,
1532                                   dev->caps.reserved_mrws, 1, 1);
1533         if (err) {
1534                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1535                 goto err_unmap_mtt;
1536         }
1537
1538         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1539                                   init_hca->qpc_base,
1540                                   dev_cap->qpc_entry_sz,
1541                                   dev->caps.num_qps,
1542                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1543                                   0, 0);
1544         if (err) {
1545                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1546                 goto err_unmap_dmpt;
1547         }
1548
1549         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1550                                   init_hca->auxc_base,
1551                                   dev_cap->aux_entry_sz,
1552                                   dev->caps.num_qps,
1553                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1554                                   0, 0);
1555         if (err) {
1556                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1557                 goto err_unmap_qp;
1558         }
1559
1560         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1561                                   init_hca->altc_base,
1562                                   dev_cap->altc_entry_sz,
1563                                   dev->caps.num_qps,
1564                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1565                                   0, 0);
1566         if (err) {
1567                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1568                 goto err_unmap_auxc;
1569         }
1570
1571         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1572                                   init_hca->rdmarc_base,
1573                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1574                                   dev->caps.num_qps,
1575                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1576                                   0, 0);
1577         if (err) {
1578                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1579                 goto err_unmap_altc;
1580         }
1581
1582         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1583                                   init_hca->cqc_base,
1584                                   dev_cap->cqc_entry_sz,
1585                                   dev->caps.num_cqs,
1586                                   dev->caps.reserved_cqs, 0, 0);
1587         if (err) {
1588                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1589                 goto err_unmap_rdmarc;
1590         }
1591
1592         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1593                                   init_hca->srqc_base,
1594                                   dev_cap->srq_entry_sz,
1595                                   dev->caps.num_srqs,
1596                                   dev->caps.reserved_srqs, 0, 0);
1597         if (err) {
1598                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1599                 goto err_unmap_cq;
1600         }
1601
1602         /*
1603          * For flow steering device managed mode it is required to use
1604          * mlx4_init_icm_table. For B0 steering mode it's not strictly
1605          * required, but for simplicity just map the whole multicast
1606          * group table now.  The table isn't very big and it's a lot
1607          * easier than trying to track ref counts.
1608          */
1609         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1610                                   init_hca->mc_base,
1611                                   mlx4_get_mgm_entry_size(dev),
1612                                   dev->caps.num_mgms + dev->caps.num_amgms,
1613                                   dev->caps.num_mgms + dev->caps.num_amgms,
1614                                   0, 0);
1615         if (err) {
1616                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1617                 goto err_unmap_srq;
1618         }
1619
1620         return 0;
1621
1622 err_unmap_srq:
1623         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1624
1625 err_unmap_cq:
1626         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1627
1628 err_unmap_rdmarc:
1629         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1630
1631 err_unmap_altc:
1632         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1633
1634 err_unmap_auxc:
1635         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1636
1637 err_unmap_qp:
1638         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1639
1640 err_unmap_dmpt:
1641         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1642
1643 err_unmap_mtt:
1644         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1645
1646 err_unmap_eq:
1647         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1648
1649 err_unmap_cmpt:
1650         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1651         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1652         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1653         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1654
1655 err_unmap_aux:
1656         unmap_flag = mlx4_UNMAP_ICM_AUX(dev);
1657         if (unmap_flag)
1658                 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n");
1659
1660 err_free_aux:
1661         if (!unmap_flag)
1662                 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1663
1664         return err;
1665 }
1666
1667 static void mlx4_free_icms(struct mlx4_dev *dev)
1668 {
1669         struct mlx4_priv *priv = mlx4_priv(dev);
1670
1671         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1672         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1673         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1674         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1675         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1676         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1677         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1678         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1679         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1680         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1681         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1682         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1683         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1684         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1685
1686         if (!mlx4_UNMAP_ICM_AUX(dev))
1687                 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1688         else
1689                 pr_warn("mlx4_core: mlx4_UNMAP_ICM_AUX failed.\n");
1690 }
1691
1692 static void mlx4_slave_exit(struct mlx4_dev *dev)
1693 {
1694         struct mlx4_priv *priv = mlx4_priv(dev);
1695
1696         mutex_lock(&priv->cmd.slave_cmd_mutex);
1697         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1698                 mlx4_warn(dev, "Failed to close slave function.\n");
1699         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1700 }
1701
1702 static int map_bf_area(struct mlx4_dev *dev)
1703 {
1704         struct mlx4_priv *priv = mlx4_priv(dev);
1705         resource_size_t bf_start;
1706         resource_size_t bf_len;
1707         int err = 0;
1708
1709         if (!dev->caps.bf_reg_size)
1710                 return -ENXIO;
1711
1712         bf_start = pci_resource_start(dev->pdev, 2) +
1713                         (dev->caps.num_uars << PAGE_SHIFT);
1714         bf_len = pci_resource_len(dev->pdev, 2) -
1715                         (dev->caps.num_uars << PAGE_SHIFT);
1716         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1717         if (!priv->bf_mapping)
1718                 err = -ENOMEM;
1719
1720         return err;
1721 }
1722
1723 static void unmap_bf_area(struct mlx4_dev *dev)
1724 {
1725         if (mlx4_priv(dev)->bf_mapping)
1726                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1727 }
1728
1729 int mlx4_read_clock(struct mlx4_dev *dev)
1730 {
1731         u32 clockhi, clocklo, clockhi1;
1732         cycle_t cycles;
1733         int i;
1734         struct mlx4_priv *priv = mlx4_priv(dev);
1735
1736         if (!priv->clock_mapping)
1737                 return -ENOTSUPP;
1738
1739         for (i = 0; i < 10; i++) {
1740                 clockhi = swab32(readl(priv->clock_mapping));
1741                 clocklo = swab32(readl(priv->clock_mapping + 4));
1742                 clockhi1 = swab32(readl(priv->clock_mapping));
1743                 if (clockhi == clockhi1)
1744                         break;
1745         }
1746
1747         cycles = (u64) clockhi << 32 | (u64) clocklo;
1748
1749         return cycles;
1750 }
1751 EXPORT_SYMBOL_GPL(mlx4_read_clock);
1752
1753
1754 static int map_internal_clock(struct mlx4_dev *dev)
1755 {
1756         struct mlx4_priv *priv = mlx4_priv(dev);
1757
1758         priv->clock_mapping = ioremap(pci_resource_start(dev->pdev,
1759                                 priv->fw.clock_bar) +
1760                                 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1761
1762         if (!priv->clock_mapping)
1763                 return -ENOMEM;
1764
1765         return 0;
1766 }
1767
1768
1769 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1770                                    struct mlx4_clock_params *params)
1771 {
1772         struct mlx4_priv *priv = mlx4_priv(dev);
1773
1774         if (mlx4_is_slave(dev))
1775                 return -ENOTSUPP;
1776         if (!params)
1777                 return -EINVAL;
1778
1779         params->bar = priv->fw.clock_bar;
1780         params->offset = priv->fw.clock_offset;
1781         params->size = MLX4_CLOCK_SIZE;
1782
1783         return 0;
1784 }
1785 EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1786
1787 static void unmap_internal_clock(struct mlx4_dev *dev)
1788 {
1789         struct mlx4_priv *priv = mlx4_priv(dev);
1790
1791         if (priv->clock_mapping)
1792                 iounmap(priv->clock_mapping);
1793 }
1794
1795 static void mlx4_close_hca(struct mlx4_dev *dev)
1796 {
1797         unmap_internal_clock(dev);
1798         unmap_bf_area(dev);
1799         if (mlx4_is_slave(dev)) {
1800                 mlx4_slave_exit(dev);
1801         } else {
1802                 mlx4_CLOSE_HCA(dev, 0);
1803                 mlx4_free_icms(dev);
1804
1805                 if (!mlx4_UNMAP_FA(dev))
1806                          mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1807                 else
1808                         pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
1809         }
1810 }
1811
1812 static int mlx4_init_slave(struct mlx4_dev *dev)
1813 {
1814         struct mlx4_priv *priv = mlx4_priv(dev);
1815         u64 dma = (u64) priv->mfunc.vhcr_dma;
1816         int num_of_reset_retries = NUM_OF_RESET_RETRIES;
1817         int ret_from_reset = 0;
1818         u32 slave_read;
1819         u32 cmd_channel_ver;
1820
1821         mutex_lock(&priv->cmd.slave_cmd_mutex);
1822         priv->cmd.max_cmds = 1;
1823         mlx4_warn(dev, "Sending reset\n");
1824         ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1825                                        MLX4_COMM_TIME);
1826         /* if we are in the middle of flr the slave will try
1827          * NUM_OF_RESET_RETRIES times before leaving.*/
1828         if (ret_from_reset) {
1829                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1830                         msleep(SLEEP_TIME_IN_RESET);
1831                         while (ret_from_reset && num_of_reset_retries) {
1832                                 mlx4_warn(dev, "slave is currently in the"
1833                                           "middle of FLR. retrying..."
1834                                           "(try num:%d)\n",
1835                                           (NUM_OF_RESET_RETRIES -
1836                                            num_of_reset_retries  + 1));
1837                                 ret_from_reset =
1838                                         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
1839                                                       0, MLX4_COMM_TIME);
1840                                 num_of_reset_retries = num_of_reset_retries - 1;
1841                         }
1842                 } else
1843                         goto err;
1844         }
1845
1846         /* check the driver version - the slave I/F revision
1847          * must match the master's */
1848         slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1849         cmd_channel_ver = mlx4_comm_get_version();
1850
1851         if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1852                 MLX4_COMM_GET_IF_REV(slave_read)) {
1853                 mlx4_err(dev, "slave driver version is not supported"
1854                          " by the master\n");
1855                 goto err;
1856         }
1857
1858         mlx4_warn(dev, "Sending vhcr0\n");
1859         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1860                                                     MLX4_COMM_TIME))
1861                 goto err;
1862         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1863                                                     MLX4_COMM_TIME))
1864                 goto err;
1865         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1866                                                     MLX4_COMM_TIME))
1867                 goto err;
1868         if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1869                 goto err;
1870
1871         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1872         return 0;
1873
1874 err:
1875         mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
1876         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1877         return -EIO;
1878 }
1879
1880 static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1881 {
1882         int i;
1883
1884         for (i = 1; i <= dev->caps.num_ports; i++) {
1885                 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1886                         dev->caps.gid_table_len[i] =
1887                                 mlx4_get_slave_num_gids(dev, 0);
1888                 else
1889                         dev->caps.gid_table_len[i] = 1;
1890                 dev->caps.pkey_table_len[i] =
1891                         dev->phys_caps.pkey_phys_table_len[i] - 1;
1892         }
1893 }
1894
1895 static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1896 {
1897         int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1898
1899         for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1900               i++) {
1901                 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1902                         break;
1903         }
1904
1905         return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1906 }
1907
1908 static void choose_steering_mode(struct mlx4_dev *dev,
1909                                  struct mlx4_dev_cap *dev_cap)
1910 {
1911         int nvfs;
1912
1913         mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(dev->pdev), 0, &nvfs);
1914         if (high_rate_steer && !mlx4_is_mfunc(dev)) {
1915                 dev->caps.flags &= ~(MLX4_DEV_CAP_FLAG_VEP_MC_STEER |
1916                                      MLX4_DEV_CAP_FLAG_VEP_UC_STEER);
1917                 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_FS_EN;
1918         }
1919
1920         if (mlx4_log_num_mgm_entry_size == -1 &&
1921             dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
1922             (!mlx4_is_mfunc(dev) ||
1923              (dev_cap->fs_max_num_qp_per_entry >= (nvfs + 1))) &&
1924             choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1925                 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1926                 dev->oper_log_mgm_entry_size =
1927                         choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
1928                 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1929                 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1930         } else {
1931                 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1932                     dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1933                         dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1934                 else {
1935                         dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1936
1937                         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1938                             dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1939                                 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1940                                           "set to use B0 steering. Falling back to A0 steering mode.\n");
1941                 }
1942                 dev->oper_log_mgm_entry_size =
1943                         mlx4_log_num_mgm_entry_size > 0 ?
1944                         mlx4_log_num_mgm_entry_size :
1945                         MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
1946                 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1947         }
1948         mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1949                  "log_num_mgm_entry_size = %d\n",
1950                  mlx4_steering_mode_str(dev->caps.steering_mode),
1951                  dev->oper_log_mgm_entry_size, mlx4_log_num_mgm_entry_size);
1952 }
1953
1954 static int mlx4_init_hca(struct mlx4_dev *dev)
1955 {
1956         struct mlx4_priv          *priv = mlx4_priv(dev);
1957         struct mlx4_dev_cap        *dev_cap = NULL;
1958         struct mlx4_adapter        adapter;
1959         struct mlx4_mod_stat_cfg   mlx4_cfg;
1960         struct mlx4_profile        profile;
1961         struct mlx4_init_hca_param init_hca;
1962         u64 icm_size;
1963         int err;
1964
1965         if (!mlx4_is_slave(dev)) {
1966                 err = mlx4_QUERY_FW(dev);
1967                 if (err) {
1968                         if (err == -EACCES)
1969                                 mlx4_info(dev, "non-primary physical function, skipping.\n");
1970                         else
1971                                 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
1972                         return err;
1973                 }
1974
1975                 err = mlx4_load_fw(dev);
1976                 if (err) {
1977                         mlx4_err(dev, "Failed to start FW, aborting.\n");
1978                         return err;
1979                 }
1980
1981                 mlx4_cfg.log_pg_sz_m = 1;
1982                 mlx4_cfg.log_pg_sz = 0;
1983                 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1984                 if (err)
1985                         mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
1986
1987                 dev_cap = kzalloc(sizeof *dev_cap, GFP_KERNEL);
1988                 if (!dev_cap) {
1989                         mlx4_err(dev, "Failed to allocate memory for dev_cap\n");
1990                         err = -ENOMEM;
1991                         goto err_stop_fw;
1992                 }
1993
1994                 err = mlx4_dev_cap(dev, dev_cap);
1995                 if (err) {
1996                         mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1997                         goto err_stop_fw;
1998                 }
1999
2000                 choose_steering_mode(dev, dev_cap);
2001
2002                 if (mlx4_is_master(dev))
2003                         mlx4_parav_master_pf_caps(dev);
2004
2005                 process_mod_param_profile(&profile);
2006                 if (dev->caps.steering_mode ==
2007                     MLX4_STEERING_MODE_DEVICE_MANAGED)
2008                         profile.num_mcg = MLX4_FS_NUM_MCG;
2009
2010                 icm_size = mlx4_make_profile(dev, &profile, dev_cap,
2011                                              &init_hca);
2012                 if ((long long) icm_size < 0) {
2013                         err = icm_size;
2014                         goto err_stop_fw;
2015                 }
2016
2017                 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2018
2019                 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2020                 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2021
2022                 err = mlx4_init_icm(dev, dev_cap, &init_hca, icm_size);
2023                 if (err)
2024                         goto err_stop_fw;
2025
2026                 init_hca.mw_enable = 1;
2027
2028                 err = mlx4_INIT_HCA(dev, &init_hca);
2029                 if (err) {
2030                         mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
2031                         goto err_free_icm;
2032                 }
2033
2034                 /*
2035                  * Read HCA frequency by QUERY_HCA command
2036                  */
2037                 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2038                         memset(&init_hca, 0, sizeof(init_hca));
2039                         err = mlx4_QUERY_HCA(dev, &init_hca);
2040                         if (err) {
2041                                 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
2042                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2043                         } else {
2044                                 dev->caps.hca_core_clock =
2045                                         init_hca.hca_core_clock;
2046                         }
2047
2048                         /* In case we got HCA frequency 0 - disable timestamping
2049                          * to avoid dividing by zero
2050                          */
2051                         if (!dev->caps.hca_core_clock) {
2052                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2053                                 mlx4_err(dev, "HCA frequency is 0. Timestamping is not supported.");
2054                         } else if (map_internal_clock(dev)) {
2055                                 /* Map internal clock,
2056                                  * in case of failure disable timestamping
2057                                  */
2058                                 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2059                                 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
2060                         }
2061                 }
2062         } else {
2063                 err = mlx4_init_slave(dev);
2064                 if (err) {
2065                         mlx4_err(dev, "Failed to initialize slave\n");
2066                         return err;
2067                 }
2068
2069                 err = mlx4_slave_cap(dev);
2070                 if (err) {
2071                         mlx4_err(dev, "Failed to obtain slave caps\n");
2072                         goto err_close;
2073                 }
2074         }
2075
2076         if (map_bf_area(dev))
2077                 mlx4_dbg(dev, "Failed to map blue flame area\n");
2078
2079         /* Only the master set the ports, all the rest got it from it.*/
2080         if (!mlx4_is_slave(dev))
2081                 mlx4_set_port_mask(dev);
2082
2083         err = mlx4_QUERY_ADAPTER(dev, &adapter);
2084         if (err) {
2085                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
2086                 goto unmap_bf;
2087         }
2088
2089         priv->eq_table.inta_pin = adapter.inta_pin;
2090         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
2091         memcpy(dev->vsd, adapter.vsd, sizeof(dev->vsd));
2092         dev->vsd_vendor_id = adapter.vsd_vendor_id;
2093
2094         if (!mlx4_is_slave(dev))
2095                 kfree(dev_cap);
2096
2097         return 0;
2098
2099 unmap_bf:
2100         if (!mlx4_is_slave(dev))
2101                 unmap_internal_clock(dev);
2102         unmap_bf_area(dev);
2103
2104         if (mlx4_is_slave(dev)) {
2105                 kfree(dev->caps.qp0_tunnel);
2106                 kfree(dev->caps.qp0_proxy);
2107                 kfree(dev->caps.qp1_tunnel);
2108                 kfree(dev->caps.qp1_proxy);
2109         }
2110
2111 err_close:
2112         if (mlx4_is_slave(dev))
2113                 mlx4_slave_exit(dev);
2114         else
2115                 mlx4_CLOSE_HCA(dev, 0);
2116
2117 err_free_icm:
2118         if (!mlx4_is_slave(dev))
2119                 mlx4_free_icms(dev);
2120
2121 err_stop_fw:
2122         if (!mlx4_is_slave(dev)) {
2123                 if (!mlx4_UNMAP_FA(dev))
2124                         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
2125                 else
2126                         pr_warn("mlx4_core: mlx4_UNMAP_FA failed.\n");
2127                 kfree(dev_cap);
2128         }
2129         return err;
2130 }
2131
2132 static int mlx4_init_counters_table(struct mlx4_dev *dev)
2133 {
2134         struct mlx4_priv *priv = mlx4_priv(dev);
2135         int nent_pow2, port_indx, vf_index, num_counters;
2136         int res, index = 0;
2137         struct counter_index *new_counter_index;
2138
2139
2140         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2141                 return -ENOENT;
2142
2143         if (!mlx4_is_slave(dev) &&
2144             dev->caps.max_counters == dev->caps.max_extended_counters) {
2145                 res = mlx4_cmd(dev, MLX4_IF_STATE_EXTENDED, 0, 0,
2146                                MLX4_CMD_SET_IF_STAT,
2147                                MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2148                 if (res) {
2149                         mlx4_err(dev, "Failed to set extended counters (err=%d)\n", res);
2150                         return res;
2151                 }
2152         }
2153
2154         mutex_init(&priv->counters_table.mutex);
2155
2156         if (mlx4_is_slave(dev)) {
2157                 for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2158                         INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]);
2159                         if (dev->caps.def_counter_index[port_indx] != 0xFF) {
2160                                 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2161                                 if (!new_counter_index)
2162                                         return -ENOMEM;
2163                                 new_counter_index->index = dev->caps.def_counter_index[port_indx];
2164                                 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port_indx]);
2165                         }
2166                 }
2167                 mlx4_dbg(dev, "%s: slave allocated %d counters for %d ports\n",
2168                          __func__, dev->caps.num_ports, dev->caps.num_ports);
2169                 return 0;
2170         }
2171
2172         nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2173
2174         for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2175                 INIT_LIST_HEAD(&priv->counters_table.global_port_list[port_indx]);
2176                 /* allocating 2 counters per port for PFs */
2177                 /* For the PF, the ETH default counters are 0,2; */
2178                 /* and the RoCE default counters are 1,3 */
2179                 for (num_counters = 0; num_counters < 2; num_counters++, index++) {
2180                         new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2181                         if (!new_counter_index)
2182                                 return -ENOMEM;
2183                         new_counter_index->index = index;
2184                         list_add_tail(&new_counter_index->list,
2185                                       &priv->counters_table.global_port_list[port_indx]);
2186                 }
2187         }
2188
2189         if (mlx4_is_master(dev)) {
2190                 for (vf_index = 0; vf_index < dev->num_vfs; vf_index++) {
2191                         for (port_indx = 0; port_indx < dev->caps.num_ports; port_indx++) {
2192                                 INIT_LIST_HEAD(&priv->counters_table.vf_list[vf_index][port_indx]);
2193                                 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2194                                 if (!new_counter_index)
2195                                         return -ENOMEM;
2196                                 if (index <  nent_pow2 - 2) {
2197                                         new_counter_index->index = index;
2198                                         index++;
2199                                 } else {
2200                                         new_counter_index->index = MLX4_SINK_COUNTER_INDEX;
2201                                 }
2202
2203                                 list_add_tail(&new_counter_index->list,
2204                                               &priv->counters_table.vf_list[vf_index][port_indx]);
2205                         }
2206                 }
2207
2208                 res = mlx4_bitmap_init(&priv->counters_table.bitmap,
2209                                        nent_pow2, nent_pow2 - 1,
2210                                        index, 1);
2211                 mlx4_dbg(dev, "%s: master allocated %d counters for %d VFs\n",
2212                          __func__, index, dev->num_vfs);
2213         } else {
2214                 res = mlx4_bitmap_init(&priv->counters_table.bitmap,
2215                                 nent_pow2, nent_pow2 - 1,
2216                                 index, 1);
2217                 mlx4_dbg(dev, "%s: native allocated %d counters for %d ports\n",
2218                          __func__, index, dev->caps.num_ports);
2219         }
2220
2221         return 0;
2222
2223 }
2224
2225 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2226 {
2227         struct mlx4_priv *priv = mlx4_priv(dev);
2228         int i, j;
2229         struct counter_index *port, *tmp_port;
2230         struct counter_index *vf, *tmp_vf;
2231
2232         mutex_lock(&priv->counters_table.mutex);
2233
2234         if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) {
2235                 for (i = 0; i < dev->caps.num_ports; i++) {
2236                         list_for_each_entry_safe(port, tmp_port,
2237                                                  &priv->counters_table.global_port_list[i],
2238                                                  list) {
2239                                 list_del(&port->list);
2240                                 kfree(port);
2241                         }
2242                 }
2243                 if (!mlx4_is_slave(dev)) {
2244                         for (i = 0; i < dev->num_vfs; i++) {
2245                                 for (j = 0; j < dev->caps.num_ports; j++) {
2246                                         list_for_each_entry_safe(vf, tmp_vf,
2247                                                                  &priv->counters_table.vf_list[i][j],
2248                                                                  list) {
2249                                                 /* clear the counter statistic */
2250                                                 if (__mlx4_clear_if_stat(dev, vf->index))
2251                                                         mlx4_dbg(dev, "%s: reset counter %d failed\n",
2252                                                                  __func__, vf->index);
2253                                                 list_del(&vf->list);
2254                                                 kfree(vf);
2255                                         }
2256                                 }
2257                         }
2258                         mlx4_bitmap_cleanup(&priv->counters_table.bitmap);
2259                 }
2260         }
2261         mutex_unlock(&priv->counters_table.mutex);
2262 }
2263
2264 int __mlx4_slave_counters_free(struct mlx4_dev *dev, int slave)
2265 {
2266         struct mlx4_priv *priv = mlx4_priv(dev);
2267         int i, first;
2268         struct counter_index *vf, *tmp_vf;
2269
2270         /* clean VF's counters for the next useg */
2271         if (slave > 0 && slave <= dev->num_vfs) {
2272                 mlx4_dbg(dev, "%s: free counters of slave(%d)\n"
2273                          , __func__, slave);
2274
2275                 mutex_lock(&priv->counters_table.mutex);
2276                 for (i = 0; i < dev->caps.num_ports; i++) {
2277                         first = 0;
2278                         list_for_each_entry_safe(vf, tmp_vf,
2279                                                  &priv->counters_table.vf_list[slave - 1][i],
2280                                                  list) {
2281                                 /* clear the counter statistic */
2282                                 if (__mlx4_clear_if_stat(dev, vf->index))
2283                                         mlx4_dbg(dev, "%s: reset counter %d failed\n",
2284                                                  __func__, vf->index);
2285                                 if (first++ && vf->index != MLX4_SINK_COUNTER_INDEX) {
2286                                         mlx4_dbg(dev, "%s: delete counter index %d for slave %d and port %d\n"
2287                                                  , __func__, vf->index, slave, i + 1);
2288                                         mlx4_bitmap_free(&priv->counters_table.bitmap, vf->index, MLX4_USE_RR);
2289                                         list_del(&vf->list);
2290                                         kfree(vf);
2291                                 } else {
2292                                         mlx4_dbg(dev, "%s: can't delete default counter index %d for slave %d and port %d\n"
2293                                                  , __func__, vf->index, slave, i + 1);
2294                                 }
2295                         }
2296                 }
2297                 mutex_unlock(&priv->counters_table.mutex);
2298         }
2299
2300         return 0;
2301 }
2302
2303 int __mlx4_counter_alloc(struct mlx4_dev *dev, int slave, int port, u32 *idx)
2304 {
2305         struct mlx4_priv *priv = mlx4_priv(dev);
2306         struct counter_index *new_counter_index;
2307
2308         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2309                 return -ENOENT;
2310
2311         if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) ||
2312             (port < 0) || (port > MLX4_MAX_PORTS)) {
2313                 mlx4_dbg(dev, "%s: invalid slave(%d) or port(%d) index\n",
2314                          __func__, slave, port);
2315                 return -EINVAL;
2316         }
2317
2318         /* handle old guest request does not support request by port index */
2319         if (port == 0) {
2320                 *idx = MLX4_SINK_COUNTER_INDEX;
2321                 mlx4_dbg(dev, "%s: allocated default counter index %d for slave %d port %d\n"
2322                          , __func__, *idx, slave, port);
2323                 return 0;
2324         }
2325
2326         mutex_lock(&priv->counters_table.mutex);
2327
2328         *idx = mlx4_bitmap_alloc(&priv->counters_table.bitmap);
2329         /* if no resources return the default counter of the slave and port */
2330         if (*idx == -1) {
2331                 if (slave == 0) { /* its the ethernet counter ?????? */
2332                         new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2333                                                        struct counter_index,
2334                                                        list);
2335                 } else {
2336                         new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next,
2337                                                        struct counter_index,
2338                                                        list);
2339                 }
2340
2341                 *idx = new_counter_index->index;
2342                 mlx4_dbg(dev, "%s: allocated defualt counter index %d for slave %d port %d\n"
2343                          , __func__, *idx, slave, port);
2344                 goto out;
2345         }
2346
2347         if (slave == 0) { /* native or master */
2348                 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2349                 if (!new_counter_index)
2350                         goto no_mem;
2351                 new_counter_index->index = *idx;
2352                 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]);
2353         } else {
2354                 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2355                 if (!new_counter_index)
2356                         goto no_mem;
2357                 new_counter_index->index = *idx;
2358                 list_add_tail(&new_counter_index->list, &priv->counters_table.vf_list[slave - 1][port - 1]);
2359         }
2360
2361         mlx4_dbg(dev, "%s: allocated counter index %d for slave %d port %d\n"
2362                  , __func__, *idx, slave, port);
2363 out:
2364         mutex_unlock(&priv->counters_table.mutex);
2365         return 0;
2366
2367 no_mem:
2368         mlx4_bitmap_free(&priv->counters_table.bitmap, *idx, MLX4_USE_RR);
2369         mutex_unlock(&priv->counters_table.mutex);
2370         *idx = MLX4_SINK_COUNTER_INDEX;
2371         mlx4_dbg(dev, "%s: failed err (%d)\n"
2372                  , __func__, -ENOMEM);
2373         return -ENOMEM;
2374 }
2375
2376 int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx)
2377 {
2378         u64 out_param;
2379         int err;
2380         struct mlx4_priv *priv = mlx4_priv(dev);
2381         struct counter_index *new_counter_index, *c_index;
2382
2383         if (mlx4_is_mfunc(dev)) {
2384                 err = mlx4_cmd_imm(dev, 0, &out_param,
2385                                    ((u32) port) << 8 | (u32) RES_COUNTER,
2386                                    RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2387                                    MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2388                 if (!err) {
2389                         *idx = get_param_l(&out_param);
2390                         if (*idx == MLX4_SINK_COUNTER_INDEX)
2391                                 return -ENOSPC;
2392
2393                         mutex_lock(&priv->counters_table.mutex);
2394                         c_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2395                                              struct counter_index,
2396                                              list);
2397                         mutex_unlock(&priv->counters_table.mutex);
2398                         if (c_index->index == *idx)
2399                                 return -EEXIST;
2400
2401                         if (mlx4_is_slave(dev)) {
2402                                 new_counter_index = kmalloc(sizeof(struct counter_index), GFP_KERNEL);
2403                                 if (!new_counter_index) {
2404                                         mlx4_counter_free(dev, port, *idx);
2405                                         return -ENOMEM;
2406                                 }
2407                                 new_counter_index->index = *idx;
2408                                 mutex_lock(&priv->counters_table.mutex);
2409                                 list_add_tail(&new_counter_index->list, &priv->counters_table.global_port_list[port - 1]);
2410                                 mutex_unlock(&priv->counters_table.mutex);
2411                                 mlx4_dbg(dev, "%s: allocated counter index %d for port %d\n"
2412                                          , __func__, *idx, port);
2413                         }
2414                 }
2415                 return err;
2416         }
2417         return __mlx4_counter_alloc(dev, 0, port, idx);
2418 }
2419 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2420
2421 void __mlx4_counter_free(struct mlx4_dev *dev, int slave, int port, u32 idx)
2422 {
2423         /* check if native or slave and deletes acordingly */
2424         struct mlx4_priv *priv = mlx4_priv(dev);
2425         struct counter_index *pf, *tmp_pf;
2426         struct counter_index *vf, *tmp_vf;
2427         int first;
2428
2429
2430         if (idx == MLX4_SINK_COUNTER_INDEX) {
2431                 mlx4_dbg(dev, "%s: try to delete default counter index %d for port %d\n"
2432                          , __func__, idx, port);
2433                         return;
2434         }
2435
2436         if ((slave > MLX4_MAX_NUM_VF) || (slave < 0) ||
2437             (port < 0) || (port > MLX4_MAX_PORTS)) {
2438                 mlx4_warn(dev, "%s: deletion failed due to invalid slave(%d) or port(%d) index\n"
2439                          , __func__, slave, idx);
2440                         return;
2441         }
2442
2443         mutex_lock(&priv->counters_table.mutex);
2444         if (slave == 0) {
2445                 first = 0;
2446                 list_for_each_entry_safe(pf, tmp_pf,
2447                                          &priv->counters_table.global_port_list[port - 1],
2448                                          list) {
2449                         /* the first 2 counters are reserved */
2450                         if (pf->index == idx) {
2451                                 /* clear the counter statistic */
2452                                 if (__mlx4_clear_if_stat(dev, pf->index))
2453                                         mlx4_dbg(dev, "%s: reset counter %d failed\n",
2454                                                  __func__, pf->index);
2455                                 if (1 < first && idx != MLX4_SINK_COUNTER_INDEX) {
2456                                         list_del(&pf->list);
2457                                         kfree(pf);
2458                                         mlx4_dbg(dev, "%s: delete counter index %d for native device (%d) port %d\n"
2459                                                  , __func__, idx, slave, port);
2460                                         mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR);
2461                                         goto out;
2462                                 } else {
2463                                         mlx4_dbg(dev, "%s: can't delete default counter index %d for native device (%d) port %d\n"
2464                                                  , __func__, idx, slave, port);
2465                                         goto out;
2466                                 }
2467                         }
2468                         first++;
2469                 }
2470                 mlx4_dbg(dev, "%s: can't delete counter index %d for native device (%d) port %d\n"
2471                          , __func__, idx, slave, port);
2472         } else {
2473                 first = 0;
2474                 list_for_each_entry_safe(vf, tmp_vf,
2475                                          &priv->counters_table.vf_list[slave - 1][port - 1],
2476                                          list) {
2477                         /* the first element is reserved */
2478                         if (vf->index == idx) {
2479                                 /* clear the counter statistic */
2480                                 if (__mlx4_clear_if_stat(dev, vf->index))
2481                                         mlx4_dbg(dev, "%s: reset counter %d failed\n",
2482                                                  __func__, vf->index);
2483                                 if (first) {
2484                                         list_del(&vf->list);
2485                                         kfree(vf);
2486                                         mlx4_dbg(dev, "%s: delete counter index %d for slave %d port %d\n",
2487                                                  __func__, idx, slave, port);
2488                                         mlx4_bitmap_free(&priv->counters_table.bitmap, idx, MLX4_USE_RR);
2489                                         goto out;
2490                                 } else {
2491                                         mlx4_dbg(dev, "%s: can't delete default slave (%d) counter index %d for port %d\n"
2492                                                  , __func__, slave, idx, port);
2493                                         goto out;
2494                                 }
2495                         }
2496                         first++;
2497                 }
2498                 mlx4_dbg(dev, "%s: can't delete slave (%d) counter index %d for port %d\n"
2499                          , __func__, slave, idx, port);
2500         }
2501
2502 out:
2503         mutex_unlock(&priv->counters_table.mutex);
2504 }
2505
2506 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx)
2507 {
2508         u64 in_param = 0;
2509         struct mlx4_priv *priv = mlx4_priv(dev);
2510         struct counter_index *counter, *tmp_counter;
2511         int first = 0;
2512
2513         if (mlx4_is_mfunc(dev)) {
2514                 set_param_l(&in_param, idx);
2515                 mlx4_cmd(dev, in_param,
2516                          ((u32) port) << 8 | (u32) RES_COUNTER,
2517                          RES_OP_RESERVE,
2518                          MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2519                          MLX4_CMD_WRAPPED);
2520
2521                 if (mlx4_is_slave(dev) && idx != MLX4_SINK_COUNTER_INDEX) {
2522                         mutex_lock(&priv->counters_table.mutex);
2523                         list_for_each_entry_safe(counter, tmp_counter,
2524                                                  &priv->counters_table.global_port_list[port - 1],
2525                                                  list) {
2526                                 if (counter->index == idx && first++) {
2527                                         list_del(&counter->list);
2528                                         kfree(counter);
2529                                         mlx4_dbg(dev, "%s: delete counter index %d for port %d\n"
2530                                                  , __func__, idx, port);
2531                                         mutex_unlock(&priv->counters_table.mutex);
2532                                         return;
2533                                 }
2534                         }
2535                         mutex_unlock(&priv->counters_table.mutex);
2536                 }
2537
2538                 return;
2539         }
2540         __mlx4_counter_free(dev, 0, port, idx);
2541 }
2542 EXPORT_SYMBOL_GPL(mlx4_counter_free);
2543
2544 int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2545                          u8 counter_index)
2546 {
2547         struct mlx4_cmd_mailbox *if_stat_mailbox = NULL;
2548         int err = 0;
2549         u32 if_stat_in_mod = (counter_index & 0xff) | (1 << 31);
2550
2551         if (counter_index == MLX4_SINK_COUNTER_INDEX)
2552                 return -EINVAL;
2553
2554         if (mlx4_is_slave(dev))
2555                 return 0;
2556
2557         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2558         if (IS_ERR(if_stat_mailbox)) {
2559                 err = PTR_ERR(if_stat_mailbox);
2560                 return err;
2561         }
2562
2563         err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2564                            MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2565                            MLX4_CMD_NATIVE);
2566
2567         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2568         return err;
2569 }
2570
2571 u8 mlx4_get_default_counter_index(struct mlx4_dev *dev, int slave, int port)
2572 {
2573         struct mlx4_priv *priv = mlx4_priv(dev);
2574         struct counter_index *new_counter_index;
2575
2576         if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) {
2577                 mlx4_dbg(dev, "%s: return counter index %d for slave %d port (MLX4_PORT_TYPE_IB) %d\n",
2578                          __func__, MLX4_SINK_COUNTER_INDEX, slave, port);
2579                 return (u8)MLX4_SINK_COUNTER_INDEX;
2580         }
2581
2582         mutex_lock(&priv->counters_table.mutex);
2583         if (slave == 0) {
2584                 new_counter_index = list_entry(priv->counters_table.global_port_list[port - 1].next,
2585                                                struct counter_index,
2586                                                list);
2587         } else {
2588                 new_counter_index = list_entry(priv->counters_table.vf_list[slave - 1][port - 1].next,
2589                                                struct counter_index,
2590                                                list);
2591         }
2592         mutex_unlock(&priv->counters_table.mutex);
2593
2594         mlx4_dbg(dev, "%s: return counter index %d for slave %d port %d\n",
2595                  __func__, new_counter_index->index, slave, port);
2596
2597
2598         return (u8)new_counter_index->index;
2599 }
2600
2601 int mlx4_get_vport_ethtool_stats(struct mlx4_dev *dev, int port,
2602                          struct mlx4_en_vport_stats *vport_stats,
2603                          int reset)
2604 {
2605         struct mlx4_priv *priv = mlx4_priv(dev);
2606         struct mlx4_cmd_mailbox *if_stat_mailbox = NULL;
2607         union  mlx4_counter *counter;
2608         int err = 0;
2609         u32 if_stat_in_mod;
2610         struct counter_index *vport, *tmp_vport;
2611
2612         if (!vport_stats)
2613                 return -EINVAL;
2614
2615         if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2616         if (IS_ERR(if_stat_mailbox)) {
2617                 err = PTR_ERR(if_stat_mailbox);
2618                 return err;
2619         }
2620
2621         mutex_lock(&priv->counters_table.mutex);
2622         list_for_each_entry_safe(vport, tmp_vport,
2623                                  &priv->counters_table.global_port_list[port - 1],
2624                                  list) {
2625                 if (vport->index == MLX4_SINK_COUNTER_INDEX)
2626                         continue;
2627
2628                 memset(if_stat_mailbox->buf, 0, sizeof(union  mlx4_counter));
2629                 if_stat_in_mod = (vport->index & 0xff) | ((reset & 1) << 31);
2630                 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma,
2631                                    if_stat_in_mod, 0,
2632                                    MLX4_CMD_QUERY_IF_STAT,
2633                                    MLX4_CMD_TIME_CLASS_C,
2634                                    MLX4_CMD_NATIVE);
2635                 if (err) {
2636                         mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n",
2637                                  __func__, vport->index);
2638                         goto if_stat_out;
2639                 }
2640                 counter = (union mlx4_counter *)if_stat_mailbox->buf;
2641                 if ((counter->control.cnt_mode & 0xf) == 1) {
2642                         vport_stats->rx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastFrames);
2643                         vport_stats->rx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxUnicastFrames);
2644                         vport_stats->rx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfRxMulticastFrames);
2645                         vport_stats->tx_broadcast_packets += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastFrames);
2646                         vport_stats->tx_unicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxUnicastFrames);
2647                         vport_stats->tx_multicast_packets += be64_to_cpu(counter->ext.counters[0].IfTxMulticastFrames);
2648                         vport_stats->rx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxBroadcastOctets);
2649                         vport_stats->rx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxUnicastOctets);
2650                         vport_stats->rx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfRxMulticastOctets);
2651                         vport_stats->tx_broadcast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxBroadcastOctets);
2652                         vport_stats->tx_unicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxUnicastOctets);
2653                         vport_stats->tx_multicast_bytes += be64_to_cpu(counter->ext.counters[0].IfTxMulticastOctets);
2654                         vport_stats->rx_errors += be64_to_cpu(counter->ext.counters[0].IfRxErrorFrames);
2655                         vport_stats->rx_dropped += be64_to_cpu(counter->ext.counters[0].IfRxNoBufferFrames);
2656                         vport_stats->tx_errors += be64_to_cpu(counter->ext.counters[0].IfTxDroppedFrames);
2657                 }
2658         }
2659
2660 if_stat_out:
2661         mutex_unlock(&priv->counters_table.mutex);
2662         mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2663
2664         return err;
2665 }
2666 EXPORT_SYMBOL_GPL(mlx4_get_vport_ethtool_stats);
2667
2668 static int mlx4_setup_hca(struct mlx4_dev *dev)
2669 {
2670         struct mlx4_priv *priv = mlx4_priv(dev);
2671         int err;
2672         int port;
2673         __be32 ib_port_default_caps;
2674
2675         err = mlx4_init_uar_table(dev);
2676         if (err) {
2677                 mlx4_err(dev, "Failed to initialize "
2678                          "user access region table (err=%d), aborting.\n",
2679                          err);
2680                 return err;
2681         }
2682
2683         err = mlx4_uar_alloc(dev, &priv->driver_uar);
2684         if (err) {
2685                 mlx4_err(dev, "Failed to allocate driver access region "
2686                          "(err=%d), aborting.\n", err);
2687                 goto err_uar_table_free;
2688         }
2689
2690         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2691         if (!priv->kar) {
2692                 mlx4_err(dev, "Couldn't map kernel access region, "
2693                          "aborting.\n");
2694                 err = -ENOMEM;
2695                 goto err_uar_free;
2696         }
2697
2698         err = mlx4_init_pd_table(dev);
2699         if (err) {
2700                 mlx4_err(dev, "Failed to initialize "
2701                          "protection domain table (err=%d), aborting.\n", err);
2702                 goto err_kar_unmap;
2703         }
2704
2705         err = mlx4_init_xrcd_table(dev);
2706         if (err) {
2707                 mlx4_err(dev, "Failed to initialize "
2708                          "reliable connection domain table (err=%d), "
2709                          "aborting.\n", err);
2710                 goto err_pd_table_free;
2711         }
2712
2713         err = mlx4_init_mr_table(dev);
2714         if (err) {
2715                 mlx4_err(dev, "Failed to initialize "
2716                          "memory region table (err=%d), aborting.\n", err);
2717                 goto err_xrcd_table_free;
2718         }
2719
2720         if (!mlx4_is_slave(dev)) {
2721                 err = mlx4_init_mcg_table(dev);
2722                 if (err) {
2723                         mlx4_err(dev, "Failed to initialize "
2724                                  "multicast group table (err=%d), aborting.\n",
2725                                  err);
2726                         goto err_mr_table_free;
2727                 }
2728         }
2729
2730         err = mlx4_init_eq_table(dev);
2731         if (err) {
2732                 mlx4_err(dev, "Failed to initialize "
2733                          "event queue table (err=%d), aborting.\n", err);
2734                 goto err_mcg_table_free;
2735         }
2736
2737         err = mlx4_cmd_use_events(dev);
2738         if (err) {
2739                 mlx4_err(dev, "Failed to switch to event-driven "
2740                          "firmware commands (err=%d), aborting.\n", err);
2741                 goto err_eq_table_free;
2742         }
2743
2744         err = mlx4_NOP(dev);
2745         if (err) {
2746                 if (dev->flags & MLX4_FLAG_MSI_X) {
2747                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
2748                                   "interrupt IRQ %d).\n",
2749                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2750                         mlx4_warn(dev, "Trying again without MSI-X.\n");
2751                 } else {
2752                         mlx4_err(dev, "NOP command failed to generate interrupt "
2753                                  "(IRQ %d), aborting.\n",
2754                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
2755                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2756                 }
2757
2758                 goto err_cmd_poll;
2759         }
2760
2761         mlx4_dbg(dev, "NOP command IRQ test passed\n");
2762
2763         err = mlx4_init_cq_table(dev);
2764         if (err) {
2765                 mlx4_err(dev, "Failed to initialize "
2766                          "completion queue table (err=%d), aborting.\n", err);
2767                 goto err_cmd_poll;
2768         }
2769
2770         err = mlx4_init_srq_table(dev);
2771         if (err) {
2772                 mlx4_err(dev, "Failed to initialize "
2773                          "shared receive queue table (err=%d), aborting.\n",
2774                          err);
2775                 goto err_cq_table_free;
2776         }
2777
2778         err = mlx4_init_qp_table(dev);
2779         if (err) {
2780                 mlx4_err(dev, "Failed to initialize "
2781                          "queue pair table (err=%d), aborting.\n", err);
2782                 goto err_srq_table_free;
2783         }
2784
2785         err = mlx4_init_counters_table(dev);
2786         if (err && err != -ENOENT) {
2787                 mlx4_err(dev, "Failed to initialize counters table (err=%d), "
2788                          "aborting.\n", err);
2789                 goto err_qp_table_free;
2790         }
2791
2792         if (!mlx4_is_slave(dev)) {
2793                 for (port = 1; port <= dev->caps.num_ports; port++) {
2794                         ib_port_default_caps = 0;
2795                         err = mlx4_get_port_ib_caps(dev, port,
2796                                                     &ib_port_default_caps);
2797                         if (err)
2798                                 mlx4_warn(dev, "failed to get port %d default "
2799                                           "ib capabilities (%d). Continuing "
2800                                           "with caps = 0\n", port, err);
2801                         dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2802
2803                         /* initialize per-slave default ib port capabilities */
2804                         if (mlx4_is_master(dev)) {
2805                                 int i;
2806                                 for (i = 0; i < dev->num_slaves; i++) {
2807                                         if (i == mlx4_master_func_num(dev))
2808                                                 continue;
2809                                         priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2810                                                         ib_port_default_caps;
2811                                 }
2812                         }
2813
2814                         dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2815
2816                         err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2817                                             dev->caps.pkey_table_len[port] : -1);
2818                         if (err) {
2819                                 mlx4_err(dev, "Failed to set port %d (err=%d), "
2820                                          "aborting\n", port, err);
2821                                 goto err_counters_table_free;
2822                         }
2823                 }
2824         }
2825
2826         return 0;
2827
2828 err_counters_table_free:
2829         mlx4_cleanup_counters_table(dev);
2830
2831 err_qp_table_free:
2832         mlx4_cleanup_qp_table(dev);
2833
2834 err_srq_table_free:
2835         mlx4_cleanup_srq_table(dev);
2836
2837 err_cq_table_free:
2838         mlx4_cleanup_cq_table(dev);
2839
2840 err_cmd_poll:
2841         mlx4_cmd_use_polling(dev);
2842
2843 err_eq_table_free:
2844         mlx4_cleanup_eq_table(dev);
2845
2846 err_mcg_table_free:
2847         if (!mlx4_is_slave(dev))
2848                 mlx4_cleanup_mcg_table(dev);
2849
2850 err_mr_table_free:
2851         mlx4_cleanup_mr_table(dev);
2852
2853 err_xrcd_table_free:
2854         mlx4_cleanup_xrcd_table(dev);
2855
2856 err_pd_table_free:
2857         mlx4_cleanup_pd_table(dev);
2858
2859 err_kar_unmap:
2860         iounmap(priv->kar);
2861
2862 err_uar_free:
2863         mlx4_uar_free(dev, &priv->driver_uar);
2864
2865 err_uar_table_free:
2866         mlx4_cleanup_uar_table(dev);
2867         return err;
2868 }
2869
2870 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2871 {
2872         struct mlx4_priv *priv = mlx4_priv(dev);
2873         struct msix_entry *entries;
2874         int nreq = min_t(int, dev->caps.num_ports *
2875                          min_t(int, num_possible_cpus() + 1, MAX_MSIX_P_PORT)
2876                                 + MSIX_LEGACY_SZ, MAX_MSIX);
2877         int err;
2878         int i;
2879
2880         if (msi_x) {
2881                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
2882                              nreq);
2883
2884                 if (msi_x > 1 && !mlx4_is_mfunc(dev))
2885                         nreq = min_t(int, nreq, msi_x);
2886
2887                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
2888                 if (!entries)
2889                         goto no_msi;
2890
2891                 for (i = 0; i < nreq; ++i)
2892                         entries[i].entry = i;
2893
2894         retry:
2895                 err = pci_enable_msix(dev->pdev, entries, nreq);
2896                 if (err) {
2897                         /* Try again if at least 2 vectors are available */
2898                         if (err > 1) {
2899                                 mlx4_info(dev, "Requested %d vectors, "
2900                                           "but only %d MSI-X vectors available, "
2901                                           "trying again\n", nreq, err);
2902                                 nreq = err;
2903                                 goto retry;
2904                         }
2905                         kfree(entries);
2906                         goto no_msi;
2907                 }
2908
2909                 if (nreq <
2910                     MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
2911                         /*Working in legacy mode , all EQ's shared*/
2912                         dev->caps.comp_pool           = 0;
2913                         dev->caps.num_comp_vectors = nreq - 1;
2914                 } else {
2915                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
2916                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2917                 }
2918                 for (i = 0; i < nreq; ++i)
2919                         priv->eq_table.eq[i].irq = entries[i].vector;
2920
2921                 dev->flags |= MLX4_FLAG_MSI_X;
2922
2923                 kfree(entries);
2924                 return;
2925         }
2926
2927 no_msi:
2928         dev->caps.num_comp_vectors = 1;
2929         dev->caps.comp_pool        = 0;
2930
2931         for (i = 0; i < 2; ++i)
2932                 priv->eq_table.eq[i].irq = dev->pdev->irq;
2933 }
2934
2935 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2936 {
2937         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2938         int err = 0;
2939
2940         info->dev = dev;
2941         info->port = port;
2942         if (!mlx4_is_slave(dev)) {
2943                 mlx4_init_mac_table(dev, &info->mac_table);
2944                 mlx4_init_vlan_table(dev, &info->vlan_table);
2945                 info->base_qpn = mlx4_get_base_qpn(dev, port);
2946         }
2947
2948         sprintf(info->dev_name, "mlx4_port%d", port);
2949         info->port_attr.attr.name = info->dev_name;
2950         if (mlx4_is_mfunc(dev))
2951                 info->port_attr.attr.mode = S_IRUGO;
2952         else {
2953                 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2954                 info->port_attr.store     = set_port_type;
2955         }
2956         info->port_attr.show      = show_port_type;
2957         sysfs_attr_init(&info->port_attr.attr);
2958
2959         err = device_create_file(&dev->pdev->dev, &info->port_attr);
2960         if (err) {
2961                 mlx4_err(dev, "Failed to create file for port %d\n", port);
2962                 info->port = -1;
2963         }
2964
2965         sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2966         info->port_mtu_attr.attr.name = info->dev_mtu_name;
2967         if (mlx4_is_mfunc(dev))
2968                 info->port_mtu_attr.attr.mode = S_IRUGO;
2969         else {
2970                 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2971                 info->port_mtu_attr.store     = set_port_ib_mtu;
2972         }
2973         info->port_mtu_attr.show      = show_port_ib_mtu;
2974         sysfs_attr_init(&info->port_mtu_attr.attr);
2975
2976         err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2977         if (err) {
2978                 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2979                 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2980                 info->port = -1;
2981         }
2982
2983         return err;
2984 }
2985
2986 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2987 {
2988         if (info->port < 0)
2989                 return;
2990
2991         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2992         device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2993 }
2994
2995 static int mlx4_init_steering(struct mlx4_dev *dev)
2996 {
2997         struct mlx4_priv *priv = mlx4_priv(dev);
2998         int num_entries = dev->caps.num_ports;
2999         int i, j;
3000
3001         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3002         if (!priv->steer)
3003                 return -ENOMEM;
3004
3005         for (i = 0; i < num_entries; i++)
3006                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3007                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3008                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3009                 }
3010         return 0;
3011 }
3012
3013 static void mlx4_clear_steering(struct mlx4_dev *dev)
3014 {
3015         struct mlx4_priv *priv = mlx4_priv(dev);
3016         struct mlx4_steer_index *entry, *tmp_entry;
3017         struct mlx4_promisc_qp *pqp, *tmp_pqp;
3018         int num_entries = dev->caps.num_ports;
3019         int i, j;
3020
3021         for (i = 0; i < num_entries; i++) {
3022                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3023                         list_for_each_entry_safe(pqp, tmp_pqp,
3024                                                  &priv->steer[i].promisc_qps[j],
3025                                                  list) {
3026                                 list_del(&pqp->list);
3027                                 kfree(pqp);
3028                         }
3029                         list_for_each_entry_safe(entry, tmp_entry,
3030                                                  &priv->steer[i].steer_entries[j],
3031                                                  list) {
3032                                 list_del(&entry->list);
3033                                 list_for_each_entry_safe(pqp, tmp_pqp,
3034                                                          &entry->duplicates,
3035                                                          list) {
3036                                         list_del(&pqp->list);
3037                                         kfree(pqp);
3038                                 }
3039                                 kfree(entry);
3040                         }
3041                 }
3042         }
3043         kfree(priv->steer);
3044 }
3045
3046 static int extended_func_num(struct pci_dev *pdev)
3047 {
3048         return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3049 }
3050
3051 #define MLX4_OWNER_BASE 0x8069c
3052 #define MLX4_OWNER_SIZE 4
3053
3054 static int mlx4_get_ownership(struct mlx4_dev *dev)
3055 {
3056         void __iomem *owner;
3057         u32 ret;
3058
3059         if (pci_channel_offline(dev->pdev))
3060                 return -EIO;
3061
3062         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
3063                         MLX4_OWNER_SIZE);
3064         if (!owner) {
3065                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3066                 return -ENOMEM;
3067         }
3068
3069         ret = readl(owner);
3070         iounmap(owner);
3071         return (int) !!ret;
3072 }
3073
3074 static void mlx4_free_ownership(struct mlx4_dev *dev)
3075 {
3076         void __iomem *owner;
3077
3078         if (pci_channel_offline(dev->pdev))
3079                 return;
3080
3081         owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
3082                         MLX4_OWNER_SIZE);
3083         if (!owner) {
3084                 mlx4_err(dev, "Failed to obtain ownership bit\n");
3085                 return;
3086         }
3087         writel(0, owner);
3088         msleep(1000);
3089         iounmap(owner);
3090 }
3091
3092 static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
3093 {
3094         struct mlx4_priv *priv;
3095         struct mlx4_dev *dev;
3096         int err;
3097         int port;
3098         int nvfs, prb_vf;
3099
3100         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3101
3102         err = pci_enable_device(pdev);
3103         if (err) {
3104                 dev_err(&pdev->dev, "Cannot enable PCI device, "
3105                         "aborting.\n");
3106                 return err;
3107         }
3108
3109         mlx4_get_val(num_vfs.dbdf2val.tbl, pci_physfn(pdev), 0, &nvfs);
3110         mlx4_get_val(probe_vf.dbdf2val.tbl, pci_physfn(pdev), 0, &prb_vf);
3111         if (nvfs > MLX4_MAX_NUM_VF) {
3112                 dev_err(&pdev->dev, "There are more VF's (%d) than allowed(%d)\n",
3113                         nvfs, MLX4_MAX_NUM_VF);
3114                 return -EINVAL;
3115         }
3116
3117         if (nvfs < 0) {
3118                 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3119                 return -EINVAL;
3120         }
3121         /*
3122          * Check for BARs.
3123          */
3124         if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3125             !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3126                 dev_err(&pdev->dev, "Missing DCS, aborting."
3127                         "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%x)\n",
3128                         pci_dev_data, pci_resource_flags(pdev, 0));
3129                 err = -ENODEV;
3130                 goto err_disable_pdev;
3131         }
3132         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3133                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
3134                 err = -ENODEV;
3135                 goto err_disable_pdev;
3136         }
3137
3138         err = pci_request_regions(pdev, DRV_NAME);
3139         if (err) {
3140                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3141                 goto err_disable_pdev;
3142         }
3143
3144         pci_set_master(pdev);
3145
3146         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3147         if (err) {
3148                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
3149                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3150                 if (err) {
3151                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
3152                         goto err_release_regions;
3153                 }
3154         }
3155         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3156         if (err) {
3157                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
3158                          "consistent PCI DMA mask.\n");
3159                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3160                 if (err) {
3161                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
3162                                 "aborting.\n");
3163                         goto err_release_regions;
3164                 }
3165         }
3166
3167         /* Allow large DMA segments, up to the firmware limit of 1 GB */
3168         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3169
3170         priv = kzalloc(sizeof *priv, GFP_KERNEL);
3171         if (!priv) {
3172                 dev_err(&pdev->dev, "Device struct alloc failed, "
3173                         "aborting.\n");
3174                 err = -ENOMEM;
3175                 goto err_release_regions;
3176         }
3177
3178         dev       = &priv->dev;
3179         dev->pdev = pdev;
3180         INIT_LIST_HEAD(&priv->dev_list);
3181         INIT_LIST_HEAD(&priv->ctx_list);
3182         spin_lock_init(&priv->ctx_lock);
3183
3184         mutex_init(&priv->port_mutex);
3185
3186         INIT_LIST_HEAD(&priv->pgdir_list);
3187         mutex_init(&priv->pgdir_mutex);
3188
3189         INIT_LIST_HEAD(&priv->bf_list);
3190         mutex_init(&priv->bf_mutex);
3191
3192         dev->rev_id = pdev->revision;
3193         dev->numa_node = dev_to_node(&pdev->dev);
3194         /* Detect if this device is a virtual function */
3195         if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3196                 /* When acting as pf, we normally skip vfs unless explicitly
3197                  * requested to probe them. */
3198                 if (nvfs && extended_func_num(pdev) > prb_vf) {
3199                         mlx4_warn(dev, "Skipping virtual function:%d\n",
3200                                                 extended_func_num(pdev));
3201                         err = -ENODEV;
3202                         goto err_free_dev;
3203                 }
3204                 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3205                 dev->flags |= MLX4_FLAG_SLAVE;
3206         } else {
3207                 /* We reset the device and enable SRIOV only for physical
3208                  * devices.  Try to claim ownership on the device;
3209                  * if already taken, skip -- do not allow multiple PFs */
3210                 err = mlx4_get_ownership(dev);
3211                 if (err) {
3212                         if (err < 0)
3213                                 goto err_free_dev;
3214                         else {
3215                                 mlx4_warn(dev, "Multiple PFs not yet supported."
3216                                           " Skipping PF.\n");
3217                                 err = -EINVAL;
3218                                 goto err_free_dev;
3219                         }
3220                 }
3221
3222                 if (nvfs) {
3223                         mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", nvfs);
3224                         err = pci_enable_sriov(pdev, nvfs);
3225                         if (err) {
3226                                 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
3227                                          err);
3228                                 err = 0;
3229                         } else {
3230                                 mlx4_warn(dev, "Running in master mode\n");
3231                                 dev->flags |= MLX4_FLAG_SRIOV |
3232                                               MLX4_FLAG_MASTER;
3233                                 dev->num_vfs = nvfs;
3234                         }
3235                 }
3236
3237                 atomic_set(&priv->opreq_count, 0);
3238                 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3239
3240                 /*
3241                  * Now reset the HCA before we touch the PCI capabilities or
3242                  * attempt a firmware command, since a boot ROM may have left
3243                  * the HCA in an undefined state.
3244                  */
3245                 err = mlx4_reset(dev);
3246                 if (err) {
3247                         mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3248                         goto err_sriov;
3249                 }
3250         }
3251
3252 slave_start:
3253         err = mlx4_cmd_init(dev);
3254         if (err) {
3255                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
3256                 goto err_sriov;
3257         }
3258
3259         /* In slave functions, the communication channel must be initialized
3260          * before posting commands. Also, init num_slaves before calling
3261          * mlx4_init_hca */
3262         if (mlx4_is_mfunc(dev)) {
3263                 if (mlx4_is_master(dev))
3264                         dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3265                 else {
3266                         dev->num_slaves = 0;
3267                         err = mlx4_multi_func_init(dev);
3268                         if (err) {
3269                                 mlx4_err(dev, "Failed to init slave mfunc"
3270                                          " interface, aborting.\n");
3271                                 goto err_cmd;
3272                         }
3273                 }
3274         }
3275
3276         err = mlx4_init_hca(dev);
3277         if (err) {
3278                 if (err == -EACCES) {
3279                         /* Not primary Physical function
3280                          * Running in slave mode */
3281                         mlx4_cmd_cleanup(dev);
3282                         dev->flags |= MLX4_FLAG_SLAVE;
3283                         dev->flags &= ~MLX4_FLAG_MASTER;
3284                         goto slave_start;
3285                 } else
3286                         goto err_mfunc;
3287         }
3288
3289         /* In master functions, the communication channel must be initialized
3290          * after obtaining its address from fw */
3291         if (mlx4_is_master(dev)) {
3292                 err = mlx4_multi_func_init(dev);
3293                 if (err) {
3294                         mlx4_err(dev, "Failed to init master mfunc"
3295                                  "interface, aborting.\n");
3296                         goto err_close;
3297                 }
3298         }
3299
3300         err = mlx4_alloc_eq_table(dev);
3301         if (err)
3302                 goto err_master_mfunc;
3303
3304         priv->msix_ctl.pool_bm = 0;
3305         mutex_init(&priv->msix_ctl.pool_lock);
3306
3307         mlx4_enable_msi_x(dev);
3308         if ((mlx4_is_mfunc(dev)) &&
3309             !(dev->flags & MLX4_FLAG_MSI_X)) {
3310                 err = -ENOSYS;
3311                 mlx4_err(dev, "INTx is not supported in multi-function mode."
3312                          " aborting.\n");
3313                 goto err_free_eq;
3314         }
3315
3316         if (!mlx4_is_slave(dev)) {
3317                 err = mlx4_init_steering(dev);
3318                 if (err)
3319                         goto err_free_eq;
3320         }
3321
3322         err = mlx4_setup_hca(dev);
3323         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3324             !mlx4_is_mfunc(dev)) {
3325                 dev->flags &= ~MLX4_FLAG_MSI_X;
3326                 dev->caps.num_comp_vectors = 1;
3327                 dev->caps.comp_pool        = 0;
3328                 pci_disable_msix(pdev);
3329                 err = mlx4_setup_hca(dev);
3330         }
3331
3332         if (err)
3333                 goto err_steer;
3334
3335         mlx4_init_quotas(dev);
3336
3337         for (port = 1; port <= dev->caps.num_ports; port++) {
3338                 err = mlx4_init_port_info(dev, port);
3339                 if (err)
3340                         goto err_port;
3341         }
3342
3343         err = mlx4_register_device(dev);
3344         if (err)
3345                 goto err_port;
3346
3347         mlx4_request_modules(dev);
3348
3349         mlx4_sense_init(dev);
3350         mlx4_start_sense(dev);
3351
3352         priv->pci_dev_data = pci_dev_data;
3353         pci_set_drvdata(pdev, dev);
3354
3355         return 0;
3356
3357 err_port:
3358         for (--port; port >= 1; --port)
3359                 mlx4_cleanup_port_info(&priv->port[port]);
3360
3361         mlx4_cleanup_counters_table(dev);
3362         mlx4_cleanup_qp_table(dev);
3363         mlx4_cleanup_srq_table(dev);
3364         mlx4_cleanup_cq_table(dev);
3365         mlx4_cmd_use_polling(dev);
3366         mlx4_cleanup_eq_table(dev);
3367         mlx4_cleanup_mcg_table(dev);
3368         mlx4_cleanup_mr_table(dev);
3369         mlx4_cleanup_xrcd_table(dev);
3370         mlx4_cleanup_pd_table(dev);
3371         mlx4_cleanup_uar_table(dev);
3372
3373 err_steer:
3374         if (!mlx4_is_slave(dev))
3375                 mlx4_clear_steering(dev);
3376
3377 err_free_eq:
3378         mlx4_free_eq_table(dev);
3379
3380 err_master_mfunc:
3381         if (mlx4_is_master(dev)) {
3382                 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3383                 mlx4_multi_func_cleanup(dev);
3384         }
3385
3386         if (mlx4_is_slave(dev)) {
3387                 kfree(dev->caps.qp0_tunnel);
3388                 kfree(dev->caps.qp0_proxy);
3389                 kfree(dev->caps.qp1_tunnel);
3390                 kfree(dev->caps.qp1_proxy);
3391         }
3392
3393 err_close:
3394         if (dev->flags & MLX4_FLAG_MSI_X)
3395                 pci_disable_msix(pdev);
3396
3397         mlx4_close_hca(dev);
3398
3399 err_mfunc:
3400         if (mlx4_is_slave(dev))
3401                 mlx4_multi_func_cleanup(dev);
3402
3403 err_cmd:
3404         mlx4_cmd_cleanup(dev);
3405
3406 err_sriov:
3407         if (dev->flags & MLX4_FLAG_SRIOV)
3408                 pci_disable_sriov(pdev);
3409
3410         if (!mlx4_is_slave(dev))
3411                 mlx4_free_ownership(dev);
3412
3413 err_free_dev:
3414         kfree(priv);
3415
3416 err_release_regions:
3417         pci_release_regions(pdev);
3418
3419 err_disable_pdev:
3420         pci_disable_device(pdev);
3421         pci_set_drvdata(pdev, NULL);
3422         return err;
3423 }
3424
3425 static int __devinit mlx4_init_one(struct pci_dev *pdev,
3426                                    const struct pci_device_id *id)
3427 {
3428         printk_once(KERN_INFO "%s", mlx4_version);
3429
3430         return __mlx4_init_one(pdev, id->driver_data);
3431 }
3432
3433 static void mlx4_remove_one(struct pci_dev *pdev)
3434 {
3435         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
3436         struct mlx4_priv *priv = mlx4_priv(dev);
3437         int p;
3438
3439         if (dev) {
3440                 /* in SRIOV it is not allowed to unload the pf's
3441                  * driver while there are alive vf's */
3442                 if (mlx4_is_master(dev)) {
3443                         if (mlx4_how_many_lives_vf(dev))
3444                                 mlx4_err(dev, "Removing PF when there are assigned VF's !!!\n");
3445                 }
3446                 mlx4_stop_sense(dev);
3447                 mlx4_unregister_device(dev);
3448
3449                 for (p = 1; p <= dev->caps.num_ports; p++) {
3450                         mlx4_cleanup_port_info(&priv->port[p]);
3451                         mlx4_CLOSE_PORT(dev, p);
3452                 }
3453
3454                 if (mlx4_is_master(dev))
3455                         mlx4_free_resource_tracker(dev,
3456                                                    RES_TR_FREE_SLAVES_ONLY);
3457
3458                 mlx4_cleanup_counters_table(dev);
3459                 mlx4_cleanup_qp_table(dev);
3460                 mlx4_cleanup_srq_table(dev);
3461                 mlx4_cleanup_cq_table(dev);
3462                 mlx4_cmd_use_polling(dev);
3463                 mlx4_cleanup_eq_table(dev);
3464                 mlx4_cleanup_mcg_table(dev);
3465                 mlx4_cleanup_mr_table(dev);
3466                 mlx4_cleanup_xrcd_table(dev);
3467                 mlx4_cleanup_pd_table(dev);
3468
3469                 if (mlx4_is_master(dev))
3470                         mlx4_free_resource_tracker(dev,
3471                                                    RES_TR_FREE_STRUCTS_ONLY);
3472
3473                 iounmap(priv->kar);
3474                 mlx4_uar_free(dev, &priv->driver_uar);
3475                 mlx4_cleanup_uar_table(dev);
3476                 if (!mlx4_is_slave(dev))
3477                         mlx4_clear_steering(dev);
3478                 mlx4_free_eq_table(dev);
3479                 if (mlx4_is_master(dev))
3480                         mlx4_multi_func_cleanup(dev);
3481                 mlx4_close_hca(dev);
3482                 if (mlx4_is_slave(dev))
3483                         mlx4_multi_func_cleanup(dev);
3484                 mlx4_cmd_cleanup(dev);
3485
3486                 if (dev->flags & MLX4_FLAG_MSI_X)
3487                         pci_disable_msix(pdev);
3488                 if (dev->flags & MLX4_FLAG_SRIOV) {
3489                         mlx4_warn(dev, "Disabling SR-IOV\n");
3490                         pci_disable_sriov(pdev);
3491                 }
3492
3493                 if (!mlx4_is_slave(dev))
3494                         mlx4_free_ownership(dev);
3495
3496                 kfree(dev->caps.qp0_tunnel);
3497                 kfree(dev->caps.qp0_proxy);
3498                 kfree(dev->caps.qp1_tunnel);
3499                 kfree(dev->caps.qp1_proxy);
3500
3501                 kfree(priv);
3502                 pci_release_regions(pdev);
3503                 pci_disable_device(pdev);
3504                 pci_set_drvdata(pdev, NULL);
3505         }
3506 }
3507
3508 static int restore_current_port_types(struct mlx4_dev *dev,
3509                                       enum mlx4_port_type *types,
3510                                       enum mlx4_port_type *poss_types)
3511 {
3512         struct mlx4_priv *priv = mlx4_priv(dev);
3513         int err, i;
3514
3515         mlx4_stop_sense(dev);
3516         mutex_lock(&priv->port_mutex);
3517         for (i = 0; i < dev->caps.num_ports; i++)
3518                 dev->caps.possible_type[i + 1] = poss_types[i];
3519         err = mlx4_change_port_types(dev, types);
3520         mlx4_start_sense(dev);
3521         mutex_unlock(&priv->port_mutex);
3522         return err;
3523 }
3524
3525 int mlx4_restart_one(struct pci_dev *pdev)
3526 {
3527         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
3528         struct mlx4_priv *priv = mlx4_priv(dev);
3529         enum mlx4_port_type curr_type[MLX4_MAX_PORTS];
3530         enum mlx4_port_type poss_type[MLX4_MAX_PORTS];
3531         int pci_dev_data, err, i;
3532
3533         pci_dev_data = priv->pci_dev_data;
3534         for (i = 0; i < dev->caps.num_ports; i++) {
3535                 curr_type[i] = dev->caps.port_type[i + 1];
3536                 poss_type[i] = dev->caps.possible_type[i + 1];
3537         }
3538
3539         mlx4_remove_one(pdev);
3540         err = __mlx4_init_one(pdev, pci_dev_data);
3541         if (err)
3542                 return err;
3543
3544         dev = pci_get_drvdata(pdev);
3545         err = restore_current_port_types(dev, curr_type, poss_type);
3546         if (err)
3547                 mlx4_err(dev, "mlx4_restart_one: could not restore original port types (%d)\n",
3548                          err);
3549         return 0;
3550 }
3551
3552 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
3553         /* MT25408 "Hermon" SDR */
3554         { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3555         /* MT25408 "Hermon" DDR */
3556         { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3557         /* MT25408 "Hermon" QDR */
3558         { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3559         /* MT25408 "Hermon" DDR PCIe gen2 */
3560         { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3561         /* MT25408 "Hermon" QDR PCIe gen2 */
3562         { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3563         /* MT25408 "Hermon" EN 10GigE */
3564         { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3565         /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
3566         { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3567         /* MT25458 ConnectX EN 10GBASE-T 10GigE */
3568         { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3569         /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
3570         { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3571         /* MT26468 ConnectX EN 10GigE PCIe gen2*/
3572         { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3573         /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
3574         { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3575         /* MT26478 ConnectX2 40GigE PCIe gen2 */
3576         { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
3577         /* MT25400 Family [ConnectX-2 Virtual Function] */
3578         { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
3579         /* MT27500 Family [ConnectX-3] */
3580         { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
3581         /* MT27500 Family [ConnectX-3 Virtual Function] */
3582         { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
3583         { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
3584         { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
3585         { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
3586         { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
3587         { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
3588         { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
3589         { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
3590         { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
3591         { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
3592         { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
3593         { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
3594         { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
3595         { 0, }
3596 };
3597
3598 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
3599
3600 static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
3601                                               pci_channel_state_t state)
3602 {
3603         mlx4_remove_one(pdev);
3604
3605         return state == pci_channel_io_perm_failure ?
3606                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
3607 }
3608
3609 static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
3610 {
3611         int ret = __mlx4_init_one(pdev, 0);
3612
3613         return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
3614 }
3615
3616 static const struct pci_error_handlers mlx4_err_handler = {
3617         .error_detected = mlx4_pci_err_detected,
3618         .slot_reset     = mlx4_pci_slot_reset,
3619 };
3620
3621 static int suspend(struct pci_dev *pdev, pm_message_t state)
3622 {
3623         mlx4_remove_one(pdev);
3624
3625         return 0;
3626 }
3627
3628 static int resume(struct pci_dev *pdev)
3629 {
3630         return __mlx4_init_one(pdev, 0);
3631 }
3632
3633 static struct pci_driver mlx4_driver = {
3634         .name           = DRV_NAME,
3635         .id_table       = mlx4_pci_table,
3636         .probe          = mlx4_init_one,
3637         .remove         = __devexit_p(mlx4_remove_one),
3638         .suspend        = suspend,
3639         .resume         = resume,
3640         .err_handler    = &mlx4_err_handler,
3641 };
3642
3643 static int __init mlx4_verify_params(void)
3644 {
3645         int status;
3646
3647         status = update_defaults(&port_type_array);
3648         if (status == INVALID_STR) {
3649                 if (mlx4_fill_dbdf2val_tbl(&port_type_array.dbdf2val))
3650                         return -1;
3651         } else if (status == INVALID_DATA) {
3652                 return -1;
3653         }
3654
3655         status = update_defaults(&num_vfs);
3656         if (status == INVALID_STR) {
3657                 if (mlx4_fill_dbdf2val_tbl(&num_vfs.dbdf2val))
3658                         return -1;
3659         } else if (status == INVALID_DATA) {
3660                 return -1;
3661         }
3662
3663         status = update_defaults(&probe_vf);
3664         if (status == INVALID_STR) {
3665                 if (mlx4_fill_dbdf2val_tbl(&probe_vf.dbdf2val))
3666                         return -1;
3667         } else if (status == INVALID_DATA) {
3668                 return -1;
3669         }
3670
3671         if (msi_x < 0) {
3672                 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x);
3673                 return -1;
3674         }
3675
3676         if ((log_num_mac < 0) || (log_num_mac > 7)) {
3677                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
3678                 return -1;
3679         }
3680
3681         if (log_num_vlan != 0)
3682                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
3683                            MLX4_LOG_NUM_VLANS);
3684
3685         if (mlx4_set_4k_mtu != -1)
3686                 pr_warning("mlx4_core: set_4k_mtu - obsolete module param\n");
3687
3688         if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) {
3689                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
3690                 return -1;
3691         }
3692
3693         if (mlx4_log_num_mgm_entry_size != -1 &&
3694             (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
3695              mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
3696                 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
3697                            "in legal range (-1 or %d..%d)\n",
3698                            mlx4_log_num_mgm_entry_size,
3699                            MLX4_MIN_MGM_LOG_ENTRY_SIZE,
3700                            MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3701                 return -1;
3702         }
3703
3704         if (mod_param_profile.num_qp < 18 || mod_param_profile.num_qp > 23) {
3705                 pr_warning("mlx4_core: bad log_num_qp: %d\n",
3706                            mod_param_profile.num_qp);
3707                 return -1;
3708         }
3709
3710         if (mod_param_profile.num_srq < 10) {
3711                 pr_warning("mlx4_core: too low log_num_srq: %d\n",
3712                            mod_param_profile.num_srq);
3713                 return -1;
3714         }
3715
3716         if (mod_param_profile.num_cq < 10) {
3717                 pr_warning("mlx4_core: too low log_num_cq: %d\n",
3718                            mod_param_profile.num_cq);
3719                 return -1;
3720         }
3721
3722         if (mod_param_profile.num_mpt < 10) {
3723                 pr_warning("mlx4_core: too low log_num_mpt: %d\n",
3724                            mod_param_profile.num_mpt);
3725                 return -1;
3726         }
3727
3728         if (mod_param_profile.num_mtt_segs &&
3729             mod_param_profile.num_mtt_segs < 15) {
3730                 pr_warning("mlx4_core: too low log_num_mtt: %d\n",
3731                            mod_param_profile.num_mtt_segs);
3732                 return -1;
3733         }
3734
3735         if (mod_param_profile.num_mtt_segs > MLX4_MAX_LOG_NUM_MTT) {
3736                 pr_warning("mlx4_core: too high log_num_mtt: %d\n",
3737                            mod_param_profile.num_mtt_segs);
3738                 return -1;
3739         }
3740         return 0;
3741 }
3742
3743 static int __init mlx4_init(void)
3744 {
3745         int ret;
3746
3747         if (mlx4_verify_params())
3748                 return -EINVAL;
3749
3750         mlx4_catas_init();
3751
3752         mlx4_wq = create_singlethread_workqueue("mlx4");
3753         if (!mlx4_wq)
3754                 return -ENOMEM;
3755
3756         if (enable_sys_tune)
3757                 sys_tune_init();
3758
3759         ret = pci_register_driver(&mlx4_driver);
3760         if (ret < 0)
3761                 goto err;
3762
3763         return 0;
3764
3765 err:
3766         if (enable_sys_tune)
3767                 sys_tune_fini();
3768
3769         destroy_workqueue(mlx4_wq);
3770
3771         return ret;
3772 }
3773
3774 static void __exit mlx4_cleanup(void)
3775 {
3776         if (enable_sys_tune)
3777                 sys_tune_fini();
3778
3779         pci_unregister_driver(&mlx4_driver);
3780         destroy_workqueue(mlx4_wq);
3781 }
3782
3783 module_init_order(mlx4_init, SI_ORDER_MIDDLE);
3784 module_exit(mlx4_cleanup);
3785
3786 #include <sys/module.h>
3787 static int
3788 mlx4_evhand(module_t mod, int event, void *arg)
3789 {
3790         return (0);
3791 }
3792
3793 static moduledata_t mlx4_mod = {
3794         .name = "mlx4",
3795         .evhand = mlx4_evhand,
3796 };
3797 MODULE_VERSION(mlx4, 1);
3798 DECLARE_MODULE(mlx4, mlx4_mod, SI_SUB_OFED_PREINIT, SI_ORDER_ANY);