2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/slab.h>
38 #include <linux/kernel.h>
39 #include <linux/vmalloc.h>
41 #include <linux/mlx4/cmd.h>
46 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
47 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
48 #define MLX4_MPT_FLAG_MIO (1 << 17)
49 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
50 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
51 #define MLX4_MPT_FLAG_REGION (1 << 8)
53 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
54 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
55 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
57 #define MLX4_MPT_STATUS_SW 0xF0
58 #define MLX4_MPT_STATUS_HW 0x00
60 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
66 spin_lock(&buddy->lock);
68 for (o = order; o <= buddy->max_order; ++o)
69 if (buddy->num_free[o]) {
70 m = 1 << (buddy->max_order - o);
71 seg = find_first_bit(buddy->bits[o], m);
76 spin_unlock(&buddy->lock);
80 clear_bit(seg, buddy->bits[o]);
86 set_bit(seg ^ 1, buddy->bits[o]);
90 spin_unlock(&buddy->lock);
97 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
101 spin_lock(&buddy->lock);
103 while (test_bit(seg ^ 1, buddy->bits[order])) {
104 clear_bit(seg ^ 1, buddy->bits[order]);
105 --buddy->num_free[order];
110 set_bit(seg, buddy->bits[order]);
111 ++buddy->num_free[order];
113 spin_unlock(&buddy->lock);
116 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
120 buddy->max_order = max_order;
121 spin_lock_init(&buddy->lock);
123 buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *),
125 buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free,
127 if (!buddy->bits || !buddy->num_free)
130 for (i = 0; i <= buddy->max_order; ++i) {
131 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
132 buddy->bits[i] = kcalloc(s, sizeof (long), GFP_KERNEL | __GFP_NOWARN);
133 if (!buddy->bits[i]) {
138 set_bit(0, buddy->bits[buddy->max_order]);
139 buddy->num_free[buddy->max_order] = 1;
144 for (i = 0; i <= buddy->max_order; ++i)
145 if ( buddy->bits[i] )
146 kfree(buddy->bits[i]);
150 kfree(buddy->num_free);
155 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
159 for (i = 0; i <= buddy->max_order; ++i)
160 kfree(buddy->bits[i]);
163 kfree(buddy->num_free);
166 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
168 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
173 seg_order = max_t(int, order - log_mtts_per_seg, 0);
175 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order);
179 offset = seg * (1 << log_mtts_per_seg);
181 if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset,
182 offset + (1 << order) - 1)) {
183 mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order);
190 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
196 if (mlx4_is_mfunc(dev)) {
197 set_param_l(&in_param, order);
198 err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT,
199 RES_OP_RESERVE_AND_MAP,
201 MLX4_CMD_TIME_CLASS_A,
205 return get_param_l(&out_param);
207 return __mlx4_alloc_mtt_range(dev, order);
210 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
211 struct mlx4_mtt *mtt)
217 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
220 mtt->page_shift = page_shift;
222 for (mtt->order = 0, i = 1; i < npages; i <<= 1)
225 mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order);
226 if (mtt->offset == -1) {
227 mlx4_err(dev, "Failed to allocate mtts for %d pages(order %d)\n",
234 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
236 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
240 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
242 seg_order = max_t(int, order - log_mtts_per_seg, 0);
243 first_seg = offset / (1 << log_mtts_per_seg);
245 mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order);
246 mlx4_table_put_range(dev, &mr_table->mtt_table, offset,
247 offset + (1 << order) - 1);
250 static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order)
255 if (mlx4_is_mfunc(dev)) {
256 set_param_l(&in_param, offset);
257 set_param_h(&in_param, order);
258 err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP,
260 MLX4_CMD_TIME_CLASS_A,
263 mlx4_warn(dev, "Failed to free mtt range at:"
264 "%d order:%d\n", offset, order);
267 __mlx4_free_mtt_range(dev, offset, order);
270 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
275 mlx4_free_mtt_range(dev, mtt->offset, mtt->order);
277 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
279 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
281 return (u64) mtt->offset * dev->caps.mtt_entry_sz;
283 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
285 static u32 hw_index_to_key(u32 ind)
287 return (ind >> 24) | (ind << 8);
290 static u32 key_to_hw_index(u32 key)
292 return (key << 24) | (key >> 8);
295 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
298 return mlx4_cmd(dev, mailbox->dma, mpt_index,
299 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B,
303 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
306 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
307 !mailbox, MLX4_CMD_HW2SW_MPT,
308 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
311 static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
312 u64 iova, u64 size, u32 access, int npages,
313 int page_shift, struct mlx4_mr *mr)
319 mr->enabled = MLX4_MR_DISABLED;
320 mr->key = hw_index_to_key(mridx);
322 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
325 static int mlx4_WRITE_MTT(struct mlx4_dev *dev,
326 struct mlx4_cmd_mailbox *mailbox,
329 return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT,
330 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
333 int __mlx4_mr_reserve(struct mlx4_dev *dev)
335 struct mlx4_priv *priv = mlx4_priv(dev);
337 return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
340 static int mlx4_mr_reserve(struct mlx4_dev *dev)
344 if (mlx4_is_mfunc(dev)) {
345 if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE,
347 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
349 return get_param_l(&out_param);
351 return __mlx4_mr_reserve(dev);
354 void __mlx4_mr_release(struct mlx4_dev *dev, u32 index)
356 struct mlx4_priv *priv = mlx4_priv(dev);
358 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
361 static void mlx4_mr_release(struct mlx4_dev *dev, u32 index)
365 if (mlx4_is_mfunc(dev)) {
366 set_param_l(&in_param, index);
367 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE,
369 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED))
370 mlx4_warn(dev, "Failed to release mr index:%d\n",
374 __mlx4_mr_release(dev, index);
377 int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index)
379 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
381 return mlx4_table_get(dev, &mr_table->dmpt_table, index);
384 static int mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index)
388 if (mlx4_is_mfunc(dev)) {
389 set_param_l(¶m, index);
390 return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM,
392 MLX4_CMD_TIME_CLASS_A,
395 return __mlx4_mr_alloc_icm(dev, index);
398 void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index)
400 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
402 mlx4_table_put(dev, &mr_table->dmpt_table, index);
405 static void mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index)
409 if (mlx4_is_mfunc(dev)) {
410 set_param_l(&in_param, index);
411 if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM,
412 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
414 mlx4_warn(dev, "Failed to free icm of mr index:%d\n",
418 return __mlx4_mr_free_icm(dev, index);
421 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
422 int npages, int page_shift, struct mlx4_mr *mr)
427 index = mlx4_mr_reserve(dev);
431 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
432 access, npages, page_shift, mr);
434 mlx4_mr_release(dev, index);
438 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
440 static void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
444 if (mr->enabled == MLX4_MR_EN_HW) {
445 err = mlx4_HW2SW_MPT(dev, NULL,
446 key_to_hw_index(mr->key) &
447 (dev->caps.num_mpts - 1));
449 mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err);
451 mr->enabled = MLX4_MR_EN_SW;
453 mlx4_mtt_cleanup(dev, &mr->mtt);
456 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
458 mlx4_mr_free_reserved(dev, mr);
460 mlx4_mr_free_icm(dev, key_to_hw_index(mr->key));
461 mlx4_mr_release(dev, key_to_hw_index(mr->key));
463 EXPORT_SYMBOL_GPL(mlx4_mr_free);
465 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
467 struct mlx4_cmd_mailbox *mailbox;
468 struct mlx4_mpt_entry *mpt_entry;
471 err = mlx4_mr_alloc_icm(dev, key_to_hw_index(mr->key));
475 mailbox = mlx4_alloc_cmd_mailbox(dev);
476 if (IS_ERR(mailbox)) {
477 err = PTR_ERR(mailbox);
480 mpt_entry = mailbox->buf;
482 memset(mpt_entry, 0, sizeof *mpt_entry);
484 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
485 MLX4_MPT_FLAG_REGION |
488 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
489 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
490 mpt_entry->start = cpu_to_be64(mr->iova);
491 mpt_entry->length = cpu_to_be64(mr->size);
492 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
494 if (mr->mtt.order < 0) {
495 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
496 mpt_entry->mtt_addr = 0;
498 mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev,
502 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
503 /* fast register MR in free state */
504 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
505 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
506 MLX4_MPT_PD_FLAG_RAE);
507 mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order);
509 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
512 err = mlx4_SW2HW_MPT(dev, mailbox,
513 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
515 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
518 mr->enabled = MLX4_MR_EN_HW;
520 mlx4_free_cmd_mailbox(dev, mailbox);
525 mlx4_free_cmd_mailbox(dev, mailbox);
528 mlx4_mr_free_icm(dev, key_to_hw_index(mr->key));
531 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
533 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
534 int start_index, int npages, u64 *page_list)
536 struct mlx4_priv *priv = mlx4_priv(dev);
538 dma_addr_t dma_handle;
541 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset +
542 start_index, &dma_handle);
547 dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle,
548 npages * sizeof (u64), DMA_TO_DEVICE);
550 for (i = 0; i < npages; ++i)
551 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
553 dma_sync_single_for_device(&dev->pdev->dev, dma_handle,
554 npages * sizeof (u64), DMA_TO_DEVICE);
559 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
560 int start_index, int npages, u64 *page_list)
565 int max_mtts_first_page;
567 /* compute how may mtts fit in the first page */
568 mtts_per_page = PAGE_SIZE / sizeof(u64);
569 max_mtts_first_page = mtts_per_page - (mtt->offset + start_index)
572 chunk = min_t(int, max_mtts_first_page, npages);
575 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
579 start_index += chunk;
582 chunk = min_t(int, mtts_per_page, npages);
587 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
588 int start_index, int npages, u64 *page_list)
590 struct mlx4_cmd_mailbox *mailbox = NULL;
591 __be64 *inbox = NULL;
599 if (mlx4_is_mfunc(dev)) {
600 mailbox = mlx4_alloc_cmd_mailbox(dev);
602 return PTR_ERR(mailbox);
603 inbox = mailbox->buf;
606 chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2,
608 inbox[0] = cpu_to_be64(mtt->offset + start_index);
610 for (i = 0; i < chunk; ++i)
611 inbox[i + 2] = cpu_to_be64(page_list[i] |
612 MLX4_MTT_FLAG_PRESENT);
613 err = mlx4_WRITE_MTT(dev, mailbox, chunk);
615 mlx4_free_cmd_mailbox(dev, mailbox);
620 start_index += chunk;
623 mlx4_free_cmd_mailbox(dev, mailbox);
627 return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list);
629 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
631 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
632 struct mlx4_buf *buf)
638 page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
642 for (i = 0; i < buf->npages; ++i)
644 page_list[i] = buf->direct.map + (i << buf->page_shift);
646 page_list[i] = buf->page_list[i].map;
648 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
653 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
655 int mlx4_init_mr_table(struct mlx4_dev *dev)
657 struct mlx4_priv *priv = mlx4_priv(dev);
658 struct mlx4_mr_table *mr_table = &priv->mr_table;
661 /* Nothing to do for slaves - all MR handling is forwarded
663 if (mlx4_is_slave(dev))
666 if (!is_power_of_2(dev->caps.num_mpts))
669 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
670 ~0, dev->caps.reserved_mrws, 0);
674 err = mlx4_buddy_init(&mr_table->mtt_buddy,
675 ilog2((u32)dev->caps.num_mtts /
676 (1 << log_mtts_per_seg)));
680 if (dev->caps.reserved_mtts) {
681 priv->reserved_mtts =
682 mlx4_alloc_mtt_range(dev,
683 fls(dev->caps.reserved_mtts - 1));
684 if (priv->reserved_mtts < 0) {
685 mlx4_warn(dev, "MTT table of order %u is too small.\n",
686 mr_table->mtt_buddy.max_order);
688 goto err_reserve_mtts;
695 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
698 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
703 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
705 struct mlx4_priv *priv = mlx4_priv(dev);
706 struct mlx4_mr_table *mr_table = &priv->mr_table;
708 if (mlx4_is_slave(dev))
710 if (priv->reserved_mtts >= 0)
711 mlx4_free_mtt_range(dev, priv->reserved_mtts,
712 fls(dev->caps.reserved_mtts - 1));
713 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
714 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
717 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
718 int npages, u64 iova)
722 if (npages > fmr->max_pages)
725 page_mask = (1 << fmr->page_shift) - 1;
727 /* We are getting page lists, so va must be page aligned. */
728 if (iova & page_mask)
731 /* Trust the user not to pass misaligned data in page_list */
733 for (i = 0; i < npages; ++i) {
734 if (page_list[i] & ~page_mask)
738 if (fmr->maps >= fmr->max_maps)
744 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
745 int npages, u64 iova, u32 *lkey, u32 *rkey)
750 err = mlx4_check_fmr(fmr, page_list, npages, iova);
756 key = key_to_hw_index(fmr->mr.key);
757 key += dev->caps.num_mpts;
758 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
760 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
762 /* Make sure MPT status is visible before writing MTT entries */
765 dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle,
766 npages * sizeof(u64), DMA_TO_DEVICE);
768 for (i = 0; i < npages; ++i)
769 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
771 dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle,
772 npages * sizeof(u64), DMA_TO_DEVICE);
774 fmr->mpt->key = cpu_to_be32(key);
775 fmr->mpt->lkey = cpu_to_be32(key);
776 fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift));
777 fmr->mpt->start = cpu_to_be64(iova);
779 /* Make MTT entries are visible before setting MPT status */
782 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
784 /* Make sure MPT status is visible before consumer can use FMR */
789 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
791 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
792 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
794 struct mlx4_priv *priv = mlx4_priv(dev);
797 if (max_maps > dev->caps.max_fmr_maps)
800 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
803 /* All MTTs must fit in the same page */
804 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
807 fmr->page_shift = page_shift;
808 fmr->max_pages = max_pages;
809 fmr->max_maps = max_maps;
812 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
813 page_shift, &fmr->mr);
817 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
829 mlx4_mr_free(dev, &fmr->mr);
832 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
834 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
836 struct mlx4_priv *priv = mlx4_priv(dev);
839 err = mlx4_mr_enable(dev, &fmr->mr);
843 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
844 key_to_hw_index(fmr->mr.key), NULL);
850 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
852 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
853 u32 *lkey, u32 *rkey)
855 struct mlx4_cmd_mailbox *mailbox;
863 mailbox = mlx4_alloc_cmd_mailbox(dev);
864 if (IS_ERR(mailbox)) {
865 err = PTR_ERR(mailbox);
866 mlx4_warn(dev, "mlx4_alloc_cmd_mailbox failed (%d)\n", err);
870 err = mlx4_HW2SW_MPT(dev, NULL,
871 key_to_hw_index(fmr->mr.key) &
872 (dev->caps.num_mpts - 1));
873 mlx4_free_cmd_mailbox(dev, mailbox);
875 mlx4_warn(dev, "mlx4_HW2SW_MPT failed (%d)\n", err);
878 fmr->mr.enabled = MLX4_MR_EN_SW;
880 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
882 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
887 mlx4_mr_free(dev, &fmr->mr);
888 fmr->mr.enabled = MLX4_MR_DISABLED;
892 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
894 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
896 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000,
899 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);