2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/errno.h>
38 #include <linux/mlx4/cmd.h>
44 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
46 struct mlx4_mpt_entry {
62 __be32 first_byte_offset;
63 } __attribute__((packed));
65 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
66 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
67 #define MLX4_MPT_FLAG_MIO (1 << 17)
68 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
69 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
70 #define MLX4_MPT_FLAG_REGION (1 << 8)
72 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
73 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
74 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
76 #define MLX4_MPT_FLAG2_FBO_EN (1 << 7)
78 #define MLX4_MPT_STATUS_SW 0xF0
79 #define MLX4_MPT_STATUS_HW 0x00
81 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
87 spin_lock(&buddy->lock);
89 for (o = order; o <= buddy->max_order; ++o)
90 if (buddy->num_free[o]) {
91 m = 1 << (buddy->max_order - o);
92 seg = find_first_bit(buddy->bits[o], m);
97 spin_unlock(&buddy->lock);
101 clear_bit(seg, buddy->bits[o]);
102 --buddy->num_free[o];
107 set_bit(seg ^ 1, buddy->bits[o]);
108 ++buddy->num_free[o];
111 spin_unlock(&buddy->lock);
118 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
122 spin_lock(&buddy->lock);
124 while (test_bit(seg ^ 1, buddy->bits[order])) {
125 clear_bit(seg ^ 1, buddy->bits[order]);
126 --buddy->num_free[order];
131 set_bit(seg, buddy->bits[order]);
132 ++buddy->num_free[order];
134 spin_unlock(&buddy->lock);
137 static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
141 buddy->max_order = max_order;
142 spin_lock_init(&buddy->lock);
144 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
146 buddy->num_free = kzalloc((buddy->max_order + 1) * sizeof (int *),
148 if (!buddy->bits || !buddy->num_free)
151 for (i = 0; i <= buddy->max_order; ++i) {
152 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
153 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
156 bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
159 set_bit(0, buddy->bits[buddy->max_order]);
160 buddy->num_free[buddy->max_order] = 1;
165 for (i = 0; i <= buddy->max_order; ++i)
166 kfree(buddy->bits[i]);
170 kfree(buddy->num_free);
175 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
179 for (i = 0; i <= buddy->max_order; ++i)
180 kfree(buddy->bits[i]);
183 kfree(buddy->num_free);
186 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
188 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
191 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
195 if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
196 seg + (1 << order) - 1)) {
197 mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
204 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
205 struct mlx4_mtt *mtt)
211 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
214 mtt->page_shift = page_shift;
216 for (mtt->order = 0, i = dev->caps.mtts_per_seg; i < npages; i <<= 1)
219 mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
220 if (mtt->first_seg == -1)
225 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
227 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
229 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
234 mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
235 mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
236 mtt->first_seg + (1 << mtt->order) - 1);
238 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
240 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
242 return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
244 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
246 static u32 hw_index_to_key(u32 ind)
248 return (ind >> 24) | (ind << 8);
251 static u32 key_to_hw_index(u32 key)
253 return (key << 24) | (key >> 8);
256 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
259 return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
260 MLX4_CMD_TIME_CLASS_B);
263 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
266 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
267 !mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B);
270 int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base_mridx)
272 struct mlx4_priv *priv = mlx4_priv(dev);
275 mridx = mlx4_bitmap_alloc_range(&priv->mr_table.mpt_bitmap, cnt, align);
283 EXPORT_SYMBOL_GPL(mlx4_mr_reserve_range);
285 void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt)
287 struct mlx4_priv *priv = mlx4_priv(dev);
288 mlx4_bitmap_free_range(&priv->mr_table.mpt_bitmap, base_mridx, cnt);
290 EXPORT_SYMBOL_GPL(mlx4_mr_release_range);
292 int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
293 u64 iova, u64 size, u32 access, int npages,
294 int page_shift, struct mlx4_mr *mr)
301 mr->key = hw_index_to_key(mridx);
303 return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
305 EXPORT_SYMBOL_GPL(mlx4_mr_alloc_reserved);
307 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
308 int npages, int page_shift, struct mlx4_mr *mr)
310 struct mlx4_priv *priv = mlx4_priv(dev);
314 index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
318 err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size,
319 access, npages, page_shift, mr);
321 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
325 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
327 void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
332 err = mlx4_HW2SW_MPT(dev, NULL,
333 key_to_hw_index(mr->key) &
334 (dev->caps.num_mpts - 1));
336 mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
339 mlx4_mtt_cleanup(dev, &mr->mtt);
341 EXPORT_SYMBOL_GPL(mlx4_mr_free_reserved);
343 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
345 struct mlx4_priv *priv = mlx4_priv(dev);
346 mlx4_mr_free_reserved(dev, mr);
347 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
349 EXPORT_SYMBOL_GPL(mlx4_mr_free);
351 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
353 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
354 struct mlx4_cmd_mailbox *mailbox;
355 struct mlx4_mpt_entry *mpt_entry;
358 err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
362 mailbox = mlx4_alloc_cmd_mailbox(dev);
363 if (IS_ERR(mailbox)) {
364 err = PTR_ERR(mailbox);
367 mpt_entry = mailbox->buf;
369 memset(mpt_entry, 0, sizeof *mpt_entry);
371 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO |
372 MLX4_MPT_FLAG_REGION |
375 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
376 mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV);
377 mpt_entry->start = cpu_to_be64(mr->iova);
378 mpt_entry->length = cpu_to_be64(mr->size);
379 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
381 if (mr->mtt.order < 0) {
382 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
383 mpt_entry->mtt_seg = 0;
385 mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
388 if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) {
389 /* fast register MR in free state */
390 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE);
391 mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG |
392 MLX4_MPT_PD_FLAG_RAE);
393 mpt_entry->mtt_sz = cpu_to_be32((1 << mr->mtt.order) *
394 dev->caps.mtts_per_seg);
396 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS);
399 err = mlx4_SW2HW_MPT(dev, mailbox,
400 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
402 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
408 mlx4_free_cmd_mailbox(dev, mailbox);
413 mlx4_free_cmd_mailbox(dev, mailbox);
416 mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
419 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
421 static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
422 int start_index, int npages, u64 *page_list)
424 struct mlx4_priv *priv = mlx4_priv(dev);
426 dma_addr_t dma_handle;
428 int s = start_index * sizeof (u64);
430 /* All MTTs must fit in the same page */
431 if (start_index / (PAGE_SIZE / sizeof (u64)) !=
432 (start_index + npages - 1) / (PAGE_SIZE / sizeof (u64)))
435 if (start_index & (dev->caps.mtts_per_seg - 1))
438 mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->first_seg +
439 s / dev->caps.mtt_entry_sz, &dma_handle);
443 for (i = 0; i < npages; ++i)
444 mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
446 dma_sync_single(&dev->pdev->dev, dma_handle, npages * sizeof (u64), DMA_TO_DEVICE);
451 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
452 int start_index, int npages, u64 *page_list)
461 chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
462 err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list);
467 start_index += chunk;
473 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
475 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
476 struct mlx4_buf *buf)
482 page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
486 for (i = 0; i < buf->npages; ++i)
488 page_list[i] = buf->direct.map + (i << buf->page_shift);
490 page_list[i] = buf->page_list[i].map;
492 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
497 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
499 int mlx4_init_mr_table(struct mlx4_dev *dev)
501 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
504 if (!is_power_of_2(dev->caps.num_mpts))
507 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
508 ~0, dev->caps.reserved_mrws, 0);
512 err = mlx4_buddy_init(&mr_table->mtt_buddy,
513 ilog2(dev->caps.num_mtt_segs));
517 if (dev->caps.reserved_mtts) {
518 if (mlx4_alloc_mtt_range(dev, fls(dev->caps.reserved_mtts - 1)) == -1) {
519 mlx4_warn(dev, "MTT table of order %d is too small.\n",
520 mr_table->mtt_buddy.max_order);
522 goto err_reserve_mtts;
529 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
532 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
537 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
539 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
541 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
542 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
545 static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list,
546 int npages, u64 iova)
550 if (npages > fmr->max_pages)
553 page_mask = (1 << fmr->page_shift) - 1;
555 /* We are getting page lists, so va must be page aligned. */
556 if (iova & page_mask)
559 /* Trust the user not to pass misaligned data in page_list */
561 for (i = 0; i < npages; ++i) {
562 if (page_list[i] & ~page_mask)
566 if (fmr->maps >= fmr->max_maps)
572 int mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
573 u64 *page_list, int npages, u64 iova, u32 fbo,
574 u32 len, u32 *lkey, u32 *rkey, int same_key)
579 err = mlx4_check_fmr(fmr, page_list, npages, iova);
585 key = key_to_hw_index(fmr->mr.key);
587 key += dev->caps.num_mpts;
588 *lkey = *rkey = fmr->mr.key = hw_index_to_key(key);
590 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
592 /* Make sure MPT status is visible before writing MTT entries */
595 for (i = 0; i < npages; ++i)
596 fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT);
598 dma_sync_single(&dev->pdev->dev, fmr->dma_handle,
599 npages * sizeof(u64), DMA_TO_DEVICE);
601 fmr->mpt->key = cpu_to_be32(key);
602 fmr->mpt->lkey = cpu_to_be32(key);
603 fmr->mpt->length = cpu_to_be64(len);
604 fmr->mpt->start = cpu_to_be64(iova);
605 fmr->mpt->first_byte_offset = cpu_to_be32(fbo & 0x001fffff);
606 fmr->mpt->flags2 = (fbo ? MLX4_MPT_FLAG2_FBO_EN : 0);
608 /* Make MTT entries are visible before setting MPT status */
611 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW;
613 /* Make sure MPT status is visible before consumer can use FMR */
618 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr_fbo);
620 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
621 int npages, u64 iova, u32 *lkey, u32 *rkey)
623 u32 len = npages * (1ull << fmr->page_shift);
625 return mlx4_map_phys_fmr_fbo(dev, fmr, page_list, npages, iova, 0,
628 EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr);
630 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
631 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
633 struct mlx4_priv *priv = mlx4_priv(dev);
637 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
640 /* All MTTs must fit in the same page */
641 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
644 fmr->page_shift = page_shift;
645 fmr->max_pages = max_pages;
646 fmr->max_maps = max_maps;
649 err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages,
650 page_shift, &fmr->mr);
654 mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
656 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
657 fmr->mr.mtt.first_seg,
667 mlx4_mr_free(dev, &fmr->mr);
670 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
672 int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx,
673 u32 pd, u32 access, int max_pages,
674 int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
676 struct mlx4_priv *priv = mlx4_priv(dev);
680 if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32)
683 /* All MTTs must fit in the same page */
684 if (max_pages * sizeof *fmr->mtts > PAGE_SIZE)
687 fmr->page_shift = page_shift;
688 fmr->max_pages = max_pages;
689 fmr->max_maps = max_maps;
692 err = mlx4_mr_alloc_reserved(dev, mridx, pd, 0, 0, access, max_pages,
693 page_shift, &fmr->mr);
697 mtt_seg = fmr->mr.mtt.first_seg * dev->caps.mtt_entry_sz;
699 fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table,
700 fmr->mr.mtt.first_seg,
710 mlx4_mr_free_reserved(dev, &fmr->mr);
713 EXPORT_SYMBOL_GPL(mlx4_fmr_alloc_reserved);
715 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
717 struct mlx4_priv *priv = mlx4_priv(dev);
720 err = mlx4_mr_enable(dev, &fmr->mr);
724 fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table,
725 key_to_hw_index(fmr->mr.key), NULL);
731 EXPORT_SYMBOL_GPL(mlx4_fmr_enable);
733 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
734 u32 *lkey, u32 *rkey)
741 *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW;
743 EXPORT_SYMBOL_GPL(mlx4_fmr_unmap);
745 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
751 mlx4_mr_free(dev, &fmr->mr);
755 EXPORT_SYMBOL_GPL(mlx4_fmr_free);
757 int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
763 mlx4_mr_free_reserved(dev, &fmr->mr);
767 EXPORT_SYMBOL_GPL(mlx4_fmr_free_reserved);
769 int mlx4_SYNC_TPT(struct mlx4_dev *dev)
771 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000);
773 EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT);