2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
39 #include <linux/types.h>
40 #include <linux/bitops.h>
41 #include <linux/workqueue.h>
42 #include <asm/atomic.h>
44 #include <linux/clocksource.h>
46 #define MAX_MSIX_P_PORT 17
48 #define MSIX_LEGACY_SZ 4
49 #define MIN_MSIX_P_PORT 5
51 #define MLX4_ROCE_MAX_GIDS 128
52 #define MLX4_ROCE_PF_GIDS 16
56 #define MLX4_MAX_100M_UNITS_VAL 255 /*
57 * work around: can't set values
58 * greater then this value when
59 * using 100 Mbps units.
61 #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */
62 #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */
63 #define MLX4_RATELIMIT_DEFAULT 0x00ff
65 #define CORE_CLOCK_MASK 0xffffffffffffULL
68 MLX4_FLAG_MSI_X = 1 << 0,
69 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
70 MLX4_FLAG_MASTER = 1 << 2,
71 MLX4_FLAG_SLAVE = 1 << 3,
72 MLX4_FLAG_SRIOV = 1 << 4,
73 MLX4_FLAG_DEV_NUM_STR = 1 << 5,
74 MLX4_FLAG_OLD_REG_MAC = 1 << 6,
78 MLX4_PORT_CAP_IS_SM = 1 << 1,
79 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
84 MLX4_MAX_PORT_PKEYS = 128
87 /* base qkey for use in sriov tunnel-qp/proxy-qp communication.
88 * These qkeys must not be allowed for general use. This is a 64k range,
89 * and to test for violation, we use the mask (protect against future chg).
91 #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
92 #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
95 MLX4_BOARD_ID_LEN = 64,
100 MLX4_MAX_NUM_PF = 16,
101 MLX4_MAX_NUM_VF = 64,
103 MLX4_MAX_EQ_NUM = 1024,
104 MLX4_MFUNC_EQ_NUM = 4,
105 MLX4_MFUNC_MAX_EQES = 8,
106 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
109 /* Driver supports 3 diffrent device methods to manage traffic steering:
110 * -device managed - High level API for ib and eth flow steering. FW is
111 * managing flow steering tables.
112 * - B0 steering mode - Common low level API for ib and (if supported) eth.
113 * - A0 steering mode - Limited low level API for eth. In case of IB,
117 MLX4_STEERING_MODE_A0,
118 MLX4_STEERING_MODE_B0,
119 MLX4_STEERING_MODE_DEVICE_MANAGED
122 static inline const char *mlx4_steering_mode_str(int steering_mode)
124 switch (steering_mode) {
125 case MLX4_STEERING_MODE_A0:
126 return "A0 steering";
128 case MLX4_STEERING_MODE_B0:
129 return "B0 steering";
131 case MLX4_STEERING_MODE_DEVICE_MANAGED:
132 return "Device managed flow steering";
135 return "Unrecognize steering mode";
140 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
141 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
142 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
143 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
144 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
145 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
146 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
147 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
148 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
149 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
150 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
151 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
152 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
153 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
154 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
155 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
156 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
157 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
158 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
159 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
160 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
161 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
162 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
163 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
164 MLX4_DEV_CAP_FLAG_CROSS_CHANNEL = 1LL << 44,
165 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
166 MLX4_DEV_CAP_FLAG_COUNTERS_EXT = 1LL << 49,
167 MLX4_DEV_CAP_FLAG_SET_PORT_ETH_SCHED = 1LL << 53,
168 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
169 MLX4_DEV_CAP_FLAG_FAST_DROP = 1LL << 57,
170 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
171 MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61,
172 MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62
176 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
177 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
178 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
179 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3,
180 MLX4_DEV_CAP_FLAG2_FSM = 1LL << 4,
181 MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 5,
182 MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 6,
183 MLX4_DEV_CAP_FLAG2_LB_SRC_CHK = 1LL << 7,
184 MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 8,
185 MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 9,
186 MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP = 1LL << 10,
187 MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 11,
188 MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 12,
189 MLX4_DEV_CAP_FLAG2_TS = 1LL << 13,
190 MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW = 1LL << 14,
191 MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 15,
192 MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 16,
193 MLX4_DEV_CAP_FLAG2_FS_EN_NCSI = 1LL << 17,
194 MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18,
195 MLX4_DEV_CAP_FLAG2_DMFS_TAG_MODE = 1LL << 19,
196 MLX4_DEV_CAP_FLAG2_ROCEV2 = 1LL << 20,
197 MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 21,
198 MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 22,
199 MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 23,
200 MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB = 1LL << 24,
201 MLX4_DEV_CAP_FLAG2_RX_CSUM_MODE = 1LL << 25,
202 MLX4_DEV_CAP_FLAG2_SYS_EQS = 1LL << 26,
205 /* bit enums for an 8-bit flags field indicating special use
206 * QPs which require special handling in qp_reserve_range.
207 * Currently, this only includes QPs used by the ETH interface,
208 * where we expect to use blueflame. These QPs must not have
209 * bits 6 and 7 set in their qp number.
211 * This enum may use only bits 0..7.
214 MLX4_RESERVE_BF_QP = 1 << 7,
218 MLX4_DEV_CAP_CQ_FLAG_IO = 1 << 0
222 MLX4_QUERY_FUNC_FLAGS_BF_RES_QP = 1LL << 0
225 /* bit enums for an 8-bit flags field indicating special use
226 * QPs which require special handling in qp_reserve_range.
227 * Currently, this only includes QPs used by the ETH interface,
228 * where we expect to use blueflame. These QPs must not have
229 * bits 6 and 7 set in their qp number.
231 * This enum may use only bits 0..7.
234 MLX4_RESERVE_ETH_BF_QP = 1 << 7,
239 MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0,
240 MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1
244 MLX4_USER_DEV_CAP_64B_CQE = 1L << 0
248 MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0
252 #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
255 MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1,
256 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
257 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
258 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
259 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
260 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
264 MLX4_EVENT_TYPE_COMP = 0x00,
265 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
266 MLX4_EVENT_TYPE_COMM_EST = 0x02,
267 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
268 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
269 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
270 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
271 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
272 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
273 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
274 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
275 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
276 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
277 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
278 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
279 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
280 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
281 MLX4_EVENT_TYPE_CMD = 0x0a,
282 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
283 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
284 MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a,
285 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
286 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
287 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
288 MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT = 0x3e,
289 MLX4_EVENT_TYPE_NONE = 0xff,
293 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
294 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
298 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE = 1,
299 MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE = 2,
303 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
306 enum slave_port_state {
312 enum slave_port_gen_event {
313 SLAVE_PORT_GEN_EVENT_DOWN = 0,
314 SLAVE_PORT_GEN_EVENT_UP,
315 SLAVE_PORT_GEN_EVENT_NONE,
318 enum slave_port_state_event {
319 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
320 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
321 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
322 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
326 MLX4_PERM_LOCAL_READ = 1 << 10,
327 MLX4_PERM_LOCAL_WRITE = 1 << 11,
328 MLX4_PERM_REMOTE_READ = 1 << 12,
329 MLX4_PERM_REMOTE_WRITE = 1 << 13,
330 MLX4_PERM_ATOMIC = 1 << 14,
331 MLX4_PERM_BIND_MW = 1 << 15,
335 MLX4_OPCODE_NOP = 0x00,
336 MLX4_OPCODE_SEND_INVAL = 0x01,
337 MLX4_OPCODE_RDMA_WRITE = 0x08,
338 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
339 MLX4_OPCODE_SEND = 0x0a,
340 MLX4_OPCODE_SEND_IMM = 0x0b,
341 MLX4_OPCODE_LSO = 0x0e,
342 MLX4_OPCODE_RDMA_READ = 0x10,
343 MLX4_OPCODE_ATOMIC_CS = 0x11,
344 MLX4_OPCODE_ATOMIC_FA = 0x12,
345 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
346 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
347 MLX4_OPCODE_BIND_MW = 0x18,
348 MLX4_OPCODE_FMR = 0x19,
349 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
350 MLX4_OPCODE_CONFIG_CMD = 0x1f,
352 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
353 MLX4_RECV_OPCODE_SEND = 0x01,
354 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
355 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
357 MLX4_CQE_OPCODE_ERROR = 0x1e,
358 MLX4_CQE_OPCODE_RESIZE = 0x16,
362 MLX4_STAT_RATE_OFFSET = 5
366 MLX4_PROT_IB_IPV6 = 0,
373 MLX4_MTT_FLAG_PRESENT = 1
377 MLX4_MAX_MTT_SHIFT = 31
380 enum mlx4_qp_region {
381 MLX4_QP_REGION_FW = 0,
382 MLX4_QP_REGION_ETH_ADDR,
383 MLX4_QP_REGION_FC_ADDR,
384 MLX4_QP_REGION_FC_EXCH,
388 enum mlx4_port_type {
389 MLX4_PORT_TYPE_NONE = 0,
390 MLX4_PORT_TYPE_IB = 1,
391 MLX4_PORT_TYPE_ETH = 2,
392 MLX4_PORT_TYPE_AUTO = 3,
393 MLX4_PORT_TYPE_NA = 4
396 enum mlx4_special_vlan_idx {
397 MLX4_NO_VLAN_IDX = 0,
402 enum mlx4_steer_type {
409 MLX4_NUM_FEXCH = 64 * 1024,
413 MLX4_MAX_FAST_REG_PAGES = 511,
417 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
418 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
419 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
422 /* Port mgmt change event handling */
424 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
425 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
426 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
427 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
428 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
431 #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
432 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
434 enum mlx4_module_id {
435 MLX4_MODULE_ID_SFP = 0x3,
436 MLX4_MODULE_ID_QSFP = 0xC,
437 MLX4_MODULE_ID_QSFP_PLUS = 0xD,
438 MLX4_MODULE_ID_QSFP28 = 0x11,
441 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
443 return (major << 32) | (minor << 16) | subminor;
446 struct mlx4_phys_caps {
447 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
448 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
452 u32 base_tunnel_sqpn;
459 int vl_cap[MLX4_MAX_PORTS + 1];
460 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
461 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
462 u64 def_mac[MLX4_MAX_PORTS + 1];
463 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
464 int gid_table_len[MLX4_MAX_PORTS + 1];
465 int pkey_table_len[MLX4_MAX_PORTS + 1];
466 int trans_type[MLX4_MAX_PORTS + 1];
467 int vendor_oui[MLX4_MAX_PORTS + 1];
468 int wavelength[MLX4_MAX_PORTS + 1];
469 u64 trans_code[MLX4_MAX_PORTS + 1];
470 int local_ca_ack_delay;
474 int bf_regs_per_page;
481 int max_qp_init_rdma;
482 int max_qp_dest_rdma;
497 int num_comp_vectors;
502 int fmr_reserved_mtts;
522 u16 stat_rate_support;
524 u8 port_width_cap[MLX4_MAX_PORTS + 1];
527 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
529 int reserved_qps_base[MLX4_NUM_QP_REGION];
532 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
533 u8 supported_type[MLX4_MAX_PORTS + 1];
534 u8 suggested_type[MLX4_MAX_PORTS + 1];
535 u8 default_sense[MLX4_MAX_PORTS + 1];
536 u32 port_mask[MLX4_MAX_PORTS + 1];
537 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
539 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
546 u32 userspace_caps; /* userspace must be aware to */
547 u32 function_caps; /* functions must be aware to */
550 u32 max_basic_counters;
551 u32 max_extended_counters;
552 u8 def_counter_index[MLX4_MAX_PORTS + 1];
553 u8 alloc_res_qp_mask;
556 struct mlx4_buf_list {
562 struct mlx4_buf_list direct;
563 struct mlx4_buf_list *page_list;
576 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
579 struct mlx4_db_pgdir {
580 struct list_head list;
581 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
582 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
583 unsigned long *bits[2];
588 struct mlx4_ib_user_db_page;
593 struct mlx4_db_pgdir *pgdir;
594 struct mlx4_ib_user_db_page *user_page;
601 struct mlx4_hwq_resources {
625 enum mlx4_mw_type type;
631 struct mlx4_mpt_entry *mpt;
633 dma_addr_t dma_handle;
643 struct list_head bf_list;
644 unsigned free_bf_bmap;
646 void __iomem *bf_map;
650 unsigned long offset;
652 struct mlx4_uar *uar;
657 void (*comp) (struct mlx4_cq *);
658 void (*event) (struct mlx4_cq *, enum mlx4_event);
660 struct mlx4_uar *uar;
672 struct completion free;
678 void (*event) (struct mlx4_qp *, enum mlx4_event);
683 struct completion free;
687 void (*event) (struct mlx4_srq *, enum mlx4_event);
695 struct completion free;
707 __be32 sl_tclass_flowlabel;
720 __be32 sl_tclass_flowlabel;
730 struct mlx4_eth_av eth;
733 struct mlx4_if_stat_control {
735 /* Extended counters enabled */
737 /* Number of interfaces */
742 struct mlx4_if_stat_basic {
743 struct mlx4_if_stat_control control;
751 #define MLX4_IF_STAT_BSC_SZ(ports)(sizeof(struct mlx4_if_stat_extended) +\
752 sizeof(((struct mlx4_if_stat_extended *)0)->\
753 counters[0]) * ports)
755 struct mlx4_if_stat_extended {
756 struct mlx4_if_stat_control control;
758 __be64 IfRxUnicastFrames;
759 __be64 IfRxUnicastOctets;
760 __be64 IfRxMulticastFrames;
761 __be64 IfRxMulticastOctets;
762 __be64 IfRxBroadcastFrames;
763 __be64 IfRxBroadcastOctets;
764 __be64 IfRxNoBufferFrames;
765 __be64 IfRxNoBufferOctets;
766 __be64 IfRxErrorFrames;
767 __be64 IfRxErrorOctets;
769 __be64 IfTxUnicastFrames;
770 __be64 IfTxUnicastOctets;
771 __be64 IfTxMulticastFrames;
772 __be64 IfTxMulticastOctets;
773 __be64 IfTxBroadcastFrames;
774 __be64 IfTxBroadcastOctets;
775 __be64 IfTxDroppedFrames;
776 __be64 IfTxDroppedOctets;
777 __be64 IfTxRequestedFramesSent;
778 __be64 IfTxGeneratedFramesSent;
779 __be64 IfTxTsoOctets;
780 } __packed counters[];
782 #define MLX4_IF_STAT_EXT_SZ(ports) (sizeof(struct mlx4_if_stat_extended) +\
783 sizeof(((struct mlx4_if_stat_extended *)\
784 0)->counters[0]) * ports)
787 struct mlx4_if_stat_control control;
788 struct mlx4_if_stat_basic basic;
789 struct mlx4_if_stat_extended ext;
791 #define MLX4_IF_STAT_SZ(ports) MLX4_IF_STAT_EXT_SZ(ports)
804 struct pci_dev *pdev;
806 unsigned long num_slaves;
807 struct mlx4_caps caps;
808 struct mlx4_phys_caps phys_caps;
809 struct mlx4_quotas quotas;
810 struct radix_tree_root qp_table_tree;
812 char board_id[MLX4_BOARD_ID_LEN];
814 char vsd[MLX4_VSD_LEN];
817 int oper_log_mgm_entry_size;
818 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
819 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
822 struct mlx4_clock_params {
861 } __packed port_change;
863 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
865 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
866 } __packed comm_channel_arm;
871 } __packed mac_update;
874 } __packed flr_event;
876 __be16 current_temperature;
877 __be16 warning_threshold;
890 } __packed port_info;
893 __be32 tbl_entries_mask;
894 } __packed tbl_change_info;
896 } __packed port_mgmt_change;
901 } __packed bad_cable;
908 struct mlx4_init_port_param {
922 #define MAD_IFC_DATA_SZ 192
923 /* MAD IFC Mailbox */
924 struct mlx4_mad_ifc {
930 __be16 class_specific;
939 u8 data[MAD_IFC_DATA_SZ];
942 #define mlx4_foreach_port(port, dev, type) \
943 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
944 if ((type) == (dev)->caps.port_mask[(port)])
946 #define mlx4_foreach_non_ib_transport_port(port, dev) \
947 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
948 if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB))
950 #define mlx4_foreach_ib_transport_port(port, dev) \
951 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
952 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
953 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
955 #define MLX4_INVALID_SLAVE_ID 0xFF
957 #define MLX4_SINK_COUNTER_INDEX 0xff
959 void handle_port_mgmt_change_event(struct work_struct *work);
961 static inline int mlx4_master_func_num(struct mlx4_dev *dev)
963 return dev->caps.function;
966 static inline int mlx4_is_master(struct mlx4_dev *dev)
968 return dev->flags & MLX4_FLAG_MASTER;
971 static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev)
973 return dev->phys_caps.base_sqpn + 8 +
974 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev);
977 static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
979 return (qpn < dev->phys_caps.base_sqpn + 8 +
980 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
983 static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
985 int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8;
987 if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8)
993 static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
995 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
998 static inline int mlx4_is_slave(struct mlx4_dev *dev)
1000 return dev->flags & MLX4_FLAG_SLAVE;
1003 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
1004 struct mlx4_buf *buf);
1005 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1006 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
1008 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
1009 return (u8 *)buf->direct.buf + offset;
1011 return (u8 *)buf->page_list[offset >> PAGE_SHIFT].buf +
1012 (offset & (PAGE_SIZE - 1));
1015 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
1016 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
1017 int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1018 void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1020 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
1021 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
1022 int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node);
1023 void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
1025 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
1026 struct mlx4_mtt *mtt);
1027 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1028 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
1030 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
1031 int npages, int page_shift, struct mlx4_mr *mr);
1032 int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
1033 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
1034 int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type,
1035 struct mlx4_mw *mw);
1036 void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw);
1037 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw);
1038 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1039 int start_index, int npages, u64 *page_list);
1040 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1041 struct mlx4_buf *buf);
1043 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
1044 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
1046 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
1047 int size, int max_direct);
1048 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
1051 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
1052 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
1053 unsigned vector, int collapsed, int timestamp_en);
1054 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
1056 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1057 int *base, u8 flags);
1058 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1060 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
1061 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
1063 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
1064 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
1065 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
1066 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
1067 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
1069 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
1070 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
1072 int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1073 int block_mcast_loopback, enum mlx4_protocol prot);
1074 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1075 enum mlx4_protocol prot);
1076 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1077 u8 port, int block_mcast_loopback,
1078 enum mlx4_protocol protocol, u64 *reg_id);
1079 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1080 enum mlx4_protocol protocol, u64 reg_id);
1083 MLX4_DOMAIN_UVERBS = 0x1000,
1084 MLX4_DOMAIN_ETHTOOL = 0x2000,
1085 MLX4_DOMAIN_RFS = 0x3000,
1086 MLX4_DOMAIN_NIC = 0x5000,
1089 enum mlx4_net_trans_rule_id {
1090 MLX4_NET_TRANS_RULE_ID_ETH = 0,
1091 MLX4_NET_TRANS_RULE_ID_IB,
1092 MLX4_NET_TRANS_RULE_ID_IPV6,
1093 MLX4_NET_TRANS_RULE_ID_IPV4,
1094 MLX4_NET_TRANS_RULE_ID_TCP,
1095 MLX4_NET_TRANS_RULE_ID_UDP,
1096 MLX4_NET_TRANS_RULE_NUM, /* should be last */
1097 MLX4_NET_TRANS_RULE_DUMMY = -1, /* force enum to be signed */
1100 extern const u16 __sw_id_hw[];
1102 static inline int map_hw_to_sw_id(u16 header_id)
1106 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
1107 if (header_id == __sw_id_hw[i])
1113 enum mlx4_net_trans_promisc_mode {
1114 MLX4_FS_REGULAR = 1,
1115 MLX4_FS_ALL_DEFAULT,
1119 MLX4_FS_MODE_NUM, /* should be last */
1120 MLX4_FS_MODE_DUMMY = -1, /* force enum to be signed */
1123 struct mlx4_spec_eth {
1128 u8 ether_type_enable;
1134 struct mlx4_spec_tcp_udp {
1136 __be16 dst_port_msk;
1138 __be16 src_port_msk;
1141 struct mlx4_spec_ipv4 {
1148 struct mlx4_spec_ib {
1155 struct mlx4_spec_list {
1156 struct list_head list;
1157 enum mlx4_net_trans_rule_id id;
1159 struct mlx4_spec_eth eth;
1160 struct mlx4_spec_ib ib;
1161 struct mlx4_spec_ipv4 ipv4;
1162 struct mlx4_spec_tcp_udp tcp_udp;
1166 enum mlx4_net_trans_hw_rule_queue {
1167 MLX4_NET_TRANS_Q_FIFO,
1168 MLX4_NET_TRANS_Q_LIFO,
1171 struct mlx4_net_trans_rule {
1172 struct list_head list;
1173 enum mlx4_net_trans_hw_rule_queue queue_mode;
1175 bool allow_loopback;
1176 enum mlx4_net_trans_promisc_mode promisc_mode;
1182 struct mlx4_net_trans_rule_hw_ctrl {
1194 struct mlx4_net_trans_rule_hw_ib {
1205 struct mlx4_net_trans_rule_hw_eth {
1218 u8 ether_type_enable;
1220 __be16 vlan_tag_msk;
1224 struct mlx4_net_trans_rule_hw_tcp_udp {
1231 __be16 dst_port_msk;
1235 __be16 src_port_msk;
1238 struct mlx4_net_trans_rule_hw_ipv4 {
1256 struct mlx4_net_trans_rule_hw_eth eth;
1257 struct mlx4_net_trans_rule_hw_ib ib;
1258 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
1259 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
1263 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
1264 enum mlx4_net_trans_promisc_mode mode);
1265 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1266 enum mlx4_net_trans_promisc_mode mode);
1267 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1268 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1269 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
1270 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
1272 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1273 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1274 int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port);
1275 int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
1276 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
1277 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
1278 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
1280 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
1281 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
1282 u8 *pg, u16 *ratelimit);
1283 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
1284 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1285 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1287 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
1288 int npages, u64 iova, u32 *lkey, u32 *rkey);
1289 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
1290 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
1291 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1292 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
1293 u32 *lkey, u32 *rkey);
1294 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
1295 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
1296 int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length,
1297 u8 op_modifier, u32 in_offset[],
1300 int mlx4_test_interrupts(struct mlx4_dev *dev);
1301 int mlx4_assign_eq(struct mlx4_dev *dev, char* name, int * vector);
1302 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
1304 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
1305 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
1307 int mlx4_counter_alloc(struct mlx4_dev *dev, u8 port, u32 *idx);
1308 void mlx4_counter_free(struct mlx4_dev *dev, u8 port, u32 idx);
1310 int mlx4_flow_attach(struct mlx4_dev *dev,
1311 struct mlx4_net_trans_rule *rule, u64 *reg_id);
1312 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
1313 int map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
1314 enum mlx4_net_trans_promisc_mode flow_type);
1315 int map_sw_to_hw_steering_id(struct mlx4_dev *dev,
1316 enum mlx4_net_trans_rule_id id);
1317 int hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id);
1319 void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
1322 int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
1324 int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
1325 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
1326 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
1327 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr, u16 lid, u8 sl);
1328 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
1329 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
1330 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
1332 void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid);
1333 __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave);
1334 int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, int *slave_id);
1335 int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, u8 *gid);
1337 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, u32 max_range_qpn);
1339 s64 mlx4_read_clock(struct mlx4_dev *dev);
1340 int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1341 struct mlx4_clock_params *params);
1343 int mlx4_get_module_info(struct mlx4_dev *dev, u8 port,
1344 u16 offset, u16 size, u8 *data);
1346 #endif /* MLX4_DEVICE_H */