2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
49 * probably the worst PCI ethernet controller ever made, with the possible
50 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
51 * DMA, but it has a terrible interface that nullifies any performance
52 * gains that bus-master DMA usually offers.
54 * For transmission, the chip offers a series of four TX descriptor
55 * registers. Each transmit frame must be in a contiguous buffer, aligned
56 * on a longword (32-bit) boundary. This means we almost always have to
57 * do mbuf copies in order to transmit a frame, except in the unlikely
58 * case where a) the packet fits into a single mbuf, and b) the packet
59 * is 32-bit aligned within the mbuf's data area. The presence of only
60 * four descriptor registers means that we can never have more than four
61 * packets queued for transmission at any one time.
63 * Reception is not much better. The driver has to allocate a single large
64 * buffer area (up to 64K in size) into which the chip will DMA received
65 * frames. Because we don't know where within this region received packets
66 * will begin or end, we have no choice but to copy data from the buffer
67 * area into mbufs in order to pass the packets up to the higher protocol
70 * It's impossible given this rotten design to really achieve decent
71 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
72 * some equally overmuscled CPU to drive it.
74 * On the bright side, the 8139 does have a built-in PHY, although
75 * rather than using an MDIO serial interface like most other NICs, the
76 * PHY registers are directly accessible through the 8139's register
77 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * The 8129 chip is an older version of the 8139 that uses an external PHY
81 * chip. The 8129 has a serial MDIO interface for accessing the MII where
82 * the 8139 lets you directly access the on-board PHY registers. We need
83 * to select which interface to use depending on the chip type.
86 #ifdef HAVE_KERNEL_OPTION_HEADERS
87 #include "opt_device_polling.h"
90 #include <sys/param.h>
91 #include <sys/endian.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/module.h>
98 #include <sys/socket.h>
99 #include <sys/sysctl.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
110 #include <machine/bus.h>
111 #include <machine/resource.h>
113 #include <sys/rman.h>
115 #include <dev/mii/mii.h>
116 #include <dev/mii/miivar.h>
118 #include <dev/pci/pcireg.h>
119 #include <dev/pci/pcivar.h>
121 MODULE_DEPEND(rl, pci, 1, 1, 1);
122 MODULE_DEPEND(rl, ether, 1, 1, 1);
123 MODULE_DEPEND(rl, miibus, 1, 1, 1);
125 /* "device miibus" required. See GENERIC if you get errors here. */
126 #include "miibus_if.h"
129 * Default to using PIO access for this driver. On SMP systems,
130 * there appear to be problems with memory mapped mode: it looks like
131 * doing too many memory mapped access back to back in rapid succession
132 * can hang the bus. I'm inclined to blame this on crummy design/construction
133 * on the part of RealTek. Memory mapped mode does appear to work on
134 * uniprocessor systems though.
136 #define RL_USEIOSPACE
138 #include <pci/if_rlreg.h>
141 * Various supported device vendors/types and their names.
143 static struct rl_type rl_devs[] = {
144 { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
145 "RealTek 8129 10/100BaseTX" },
146 { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
147 "RealTek 8139 10/100BaseTX" },
148 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
149 "RealTek 8139 10/100BaseTX" },
150 { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
151 "RealTek 8139 10/100BaseTX CardBus" },
152 { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
153 "RealTek 8100 10/100BaseTX" },
154 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
155 "Accton MPX 5030/5038 10/100BaseTX" },
156 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
157 "Delta Electronics 8139 10/100BaseTX" },
158 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
159 "Addtron Technology 8139 10/100BaseTX" },
160 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
161 "D-Link DFE-530TX+ 10/100BaseTX" },
162 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
163 "D-Link DFE-690TXD 10/100BaseTX" },
164 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
165 "Nortel Networks 10/100BaseTX" },
166 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
167 "Corega FEther CB-TXD" },
168 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
169 "Corega FEtherII CB-TXD" },
170 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
171 "Peppercon AG ROL-F" },
172 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
173 "Planex FNW-3603-TX" },
174 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
175 "Planex FNW-3800-TX" },
176 { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
178 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
179 "LevelOne FPC-0106TX" },
180 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
181 "Edimax EP-4103DL CardBus" }
184 static int rl_attach(device_t);
185 static int rl_detach(device_t);
186 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
187 static int rl_dma_alloc(struct rl_softc *);
188 static void rl_dma_free(struct rl_softc *);
189 static void rl_eeprom_putbyte(struct rl_softc *, int);
190 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
191 static int rl_encap(struct rl_softc *, struct mbuf **);
192 static int rl_list_tx_init(struct rl_softc *);
193 static int rl_list_rx_init(struct rl_softc *);
194 static int rl_ifmedia_upd(struct ifnet *);
195 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
196 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
197 static void rl_intr(void *);
198 static void rl_init(void *);
199 static void rl_init_locked(struct rl_softc *sc);
200 static void rl_mii_send(struct rl_softc *, uint32_t, int);
201 static void rl_mii_sync(struct rl_softc *);
202 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
203 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
204 static int rl_miibus_readreg(device_t, int, int);
205 static void rl_miibus_statchg(device_t);
206 static int rl_miibus_writereg(device_t, int, int, int);
207 #ifdef DEVICE_POLLING
208 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
209 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
211 static int rl_probe(device_t);
212 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
213 static void rl_reset(struct rl_softc *);
214 static int rl_resume(device_t);
215 static int rl_rxeof(struct rl_softc *);
216 static void rl_setmulti(struct rl_softc *);
217 static int rl_shutdown(device_t);
218 static void rl_start(struct ifnet *);
219 static void rl_start_locked(struct ifnet *);
220 static void rl_stop(struct rl_softc *);
221 static int rl_suspend(device_t);
222 static void rl_tick(void *);
223 static void rl_txeof(struct rl_softc *);
224 static void rl_watchdog(struct rl_softc *);
227 #define RL_RES SYS_RES_IOPORT
228 #define RL_RID RL_PCI_LOIO
230 #define RL_RES SYS_RES_MEMORY
231 #define RL_RID RL_PCI_LOMEM
234 static device_method_t rl_methods[] = {
235 /* Device interface */
236 DEVMETHOD(device_probe, rl_probe),
237 DEVMETHOD(device_attach, rl_attach),
238 DEVMETHOD(device_detach, rl_detach),
239 DEVMETHOD(device_suspend, rl_suspend),
240 DEVMETHOD(device_resume, rl_resume),
241 DEVMETHOD(device_shutdown, rl_shutdown),
244 DEVMETHOD(bus_print_child, bus_generic_print_child),
245 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
248 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
249 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
250 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
255 static driver_t rl_driver = {
258 sizeof(struct rl_softc)
261 static devclass_t rl_devclass;
263 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
264 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
265 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
268 CSR_WRITE_1(sc, RL_EECMD, \
269 CSR_READ_1(sc, RL_EECMD) | x)
272 CSR_WRITE_1(sc, RL_EECMD, \
273 CSR_READ_1(sc, RL_EECMD) & ~x)
276 * Send a read command and address to the EEPROM, check for ACK.
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
283 d = addr | sc->rl_eecmd_read;
286 * Feed in each bit and strobe the clock.
288 for (i = 0x400; i; i >>= 1) {
290 EE_SET(RL_EE_DATAIN);
292 EE_CLR(RL_EE_DATAIN);
303 * Read a word of data stored in the EEPROM at address 'addr.'
306 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
311 /* Enter EEPROM access mode. */
312 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
315 * Send address of word we want to read.
317 rl_eeprom_putbyte(sc, addr);
319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
322 * Start reading bits from EEPROM.
324 for (i = 0x8000; i; i >>= 1) {
327 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
333 /* Turn off EEPROM access mode. */
334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
340 * Read a sequence of words from the EEPROM.
343 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
346 uint16_t word = 0, *ptr;
348 for (i = 0; i < cnt; i++) {
349 rl_eeprom_getword(sc, off + i, &word);
350 ptr = (uint16_t *)(dest + (i * 2));
359 * MII access routines are provided for the 8129, which
360 * doesn't have a built-in PHY. For the 8139, we fake things
361 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
362 * direct access PHY registers.
365 CSR_WRITE_1(sc, RL_MII, \
366 CSR_READ_1(sc, RL_MII) | (x))
369 CSR_WRITE_1(sc, RL_MII, \
370 CSR_READ_1(sc, RL_MII) & ~(x))
373 * Sync the PHYs by setting data bit and strobing the clock 32 times.
376 rl_mii_sync(struct rl_softc *sc)
380 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
382 for (i = 0; i < 32; i++) {
391 * Clock a series of bits through the MII.
394 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
402 MII_SET(RL_MII_DATAOUT);
404 MII_CLR(RL_MII_DATAOUT);
414 * Read an PHY register through the MII.
417 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
421 /* Set up frame for RX. */
422 frame->mii_stdelim = RL_MII_STARTDELIM;
423 frame->mii_opcode = RL_MII_READOP;
424 frame->mii_turnaround = 0;
427 CSR_WRITE_2(sc, RL_MII, 0);
429 /* Turn on data xmit. */
434 /* Send command/address info. */
435 rl_mii_send(sc, frame->mii_stdelim, 2);
436 rl_mii_send(sc, frame->mii_opcode, 2);
437 rl_mii_send(sc, frame->mii_phyaddr, 5);
438 rl_mii_send(sc, frame->mii_regaddr, 5);
441 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
452 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
457 * Now try reading data bits. If the ack failed, we still
458 * need to clock through 16 cycles to keep the PHY(s) in sync.
461 for(i = 0; i < 16; i++) {
470 for (i = 0x8000; i; i >>= 1) {
474 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
475 frame->mii_data |= i;
488 return (ack ? 1 : 0);
492 * Write to a PHY register through the MII.
495 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
498 /* Set up frame for TX. */
499 frame->mii_stdelim = RL_MII_STARTDELIM;
500 frame->mii_opcode = RL_MII_WRITEOP;
501 frame->mii_turnaround = RL_MII_TURNAROUND;
503 /* Turn on data output. */
508 rl_mii_send(sc, frame->mii_stdelim, 2);
509 rl_mii_send(sc, frame->mii_opcode, 2);
510 rl_mii_send(sc, frame->mii_phyaddr, 5);
511 rl_mii_send(sc, frame->mii_regaddr, 5);
512 rl_mii_send(sc, frame->mii_turnaround, 2);
513 rl_mii_send(sc, frame->mii_data, 16);
528 rl_miibus_readreg(device_t dev, int phy, int reg)
531 struct rl_mii_frame frame;
533 uint16_t rl8139_reg = 0;
535 sc = device_get_softc(dev);
537 if (sc->rl_type == RL_8139) {
538 /* Pretend the internal PHY is only at address 0 */
544 rl8139_reg = RL_BMCR;
547 rl8139_reg = RL_BMSR;
550 rl8139_reg = RL_ANAR;
553 rl8139_reg = RL_ANER;
556 rl8139_reg = RL_LPAR;
562 * Allow the rlphy driver to read the media status
563 * register. If we have a link partner which does not
564 * support NWAY, this is the register which will tell
565 * us the results of parallel detection.
568 rval = CSR_READ_1(sc, RL_MEDIASTAT);
571 device_printf(sc->rl_dev, "bad phy register\n");
574 rval = CSR_READ_2(sc, rl8139_reg);
578 bzero((char *)&frame, sizeof(frame));
579 frame.mii_phyaddr = phy;
580 frame.mii_regaddr = reg;
581 rl_mii_readreg(sc, &frame);
583 return (frame.mii_data);
587 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
590 struct rl_mii_frame frame;
591 uint16_t rl8139_reg = 0;
593 sc = device_get_softc(dev);
595 if (sc->rl_type == RL_8139) {
596 /* Pretend the internal PHY is only at address 0 */
602 rl8139_reg = RL_BMCR;
605 rl8139_reg = RL_BMSR;
608 rl8139_reg = RL_ANAR;
611 rl8139_reg = RL_ANER;
614 rl8139_reg = RL_LPAR;
621 device_printf(sc->rl_dev, "bad phy register\n");
624 CSR_WRITE_2(sc, rl8139_reg, data);
628 bzero((char *)&frame, sizeof(frame));
629 frame.mii_phyaddr = phy;
630 frame.mii_regaddr = reg;
631 frame.mii_data = data;
632 rl_mii_writereg(sc, &frame);
638 rl_miibus_statchg(device_t dev)
642 struct mii_data *mii;
644 sc = device_get_softc(dev);
645 mii = device_get_softc(sc->rl_miibus);
647 if (mii == NULL || ifp == NULL ||
648 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
651 sc->rl_flags &= ~RL_FLAG_LINK;
652 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
653 (IFM_ACTIVE | IFM_AVALID)) {
654 switch (IFM_SUBTYPE(mii->mii_media_active)) {
657 sc->rl_flags |= RL_FLAG_LINK;
664 * RealTek controllers do not provide any interface to
665 * Tx/Rx MACs for resolved speed, duplex and flow-control
671 * Program the 64-bit multicast hash filter.
674 rl_setmulti(struct rl_softc *sc)
676 struct ifnet *ifp = sc->rl_ifp;
678 uint32_t hashes[2] = { 0, 0 };
679 struct ifmultiaddr *ifma;
685 rxfilt = CSR_READ_4(sc, RL_RXCFG);
687 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
688 rxfilt |= RL_RXCFG_RX_MULTI;
689 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
690 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
691 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
695 /* first, zot all the existing hash bits */
696 CSR_WRITE_4(sc, RL_MAR0, 0);
697 CSR_WRITE_4(sc, RL_MAR4, 0);
699 /* now program new ones */
701 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
702 if (ifma->ifma_addr->sa_family != AF_LINK)
704 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
705 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
707 hashes[0] |= (1 << h);
709 hashes[1] |= (1 << (h - 32));
712 if_maddr_runlock(ifp);
715 rxfilt |= RL_RXCFG_RX_MULTI;
717 rxfilt &= ~RL_RXCFG_RX_MULTI;
719 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
720 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
721 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
725 rl_reset(struct rl_softc *sc)
731 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
733 for (i = 0; i < RL_TIMEOUT; i++) {
735 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
739 device_printf(sc->rl_dev, "reset never completed!\n");
743 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
744 * IDs against our list and return a device name if we find a match.
747 rl_probe(device_t dev)
750 uint16_t devid, revid, vendor;
753 vendor = pci_get_vendor(dev);
754 devid = pci_get_device(dev);
755 revid = pci_get_revid(dev);
757 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
759 /* 8139C+, let re(4) take care of this device. */
764 for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
765 if (vendor == t->rl_vid && devid == t->rl_did) {
766 device_set_desc(dev, t->rl_name);
767 return (BUS_PROBE_DEFAULT);
774 struct rl_dmamap_arg {
775 bus_addr_t rl_busaddr;
779 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
781 struct rl_dmamap_arg *ctx;
786 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
788 ctx = (struct rl_dmamap_arg *)arg;
789 ctx->rl_busaddr = segs[0].ds_addr;
793 * Attach the interface. Allocate softc structures, do ifmedia
794 * setup and ethernet/BPF attach.
797 rl_attach(device_t dev)
799 uint8_t eaddr[ETHER_ADDR_LEN];
804 struct sysctl_ctx_list *ctx;
805 struct sysctl_oid_list *children;
806 int error = 0, i, rid;
811 sc = device_get_softc(dev);
812 unit = device_get_unit(dev);
815 sc->rl_twister_enable = 0;
816 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
817 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
818 ctx = device_get_sysctl_ctx(sc->rl_dev);
819 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
820 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
821 &sc->rl_twister_enable, 0, "");
823 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
825 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
827 pci_enable_busmaster(dev);
829 /* Map control/status registers. */
831 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
833 if (sc->rl_res == NULL) {
834 device_printf(dev, "couldn't map ports/memory\n");
841 * Detect the Realtek 8139B. For some reason, this chip is very
842 * unstable when left to autoselect the media
843 * The best workaround is to set the device to the required
844 * media type or to set it to the 10 Meg speed.
846 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
848 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
851 sc->rl_btag = rman_get_bustag(sc->rl_res);
852 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
854 /* Allocate interrupt */
856 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
857 RF_SHAREABLE | RF_ACTIVE);
859 if (sc->rl_irq[0] == NULL) {
860 device_printf(dev, "couldn't map interrupt\n");
866 * Reset the adapter. Only take the lock here as it's needed in
867 * order to call rl_reset().
873 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
874 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
875 if (rl_did != 0x8129)
876 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
879 * Get station address from the EEPROM.
881 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
882 for (i = 0; i < 3; i++) {
883 eaddr[(i * 2) + 0] = as[i] & 0xff;
884 eaddr[(i * 2) + 1] = as[i] >> 8;
888 * Now read the exact device type from the EEPROM to find
889 * out if it's an 8129 or 8139.
891 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
895 while(t->rl_name != NULL) {
896 if (rl_did == t->rl_did) {
897 sc->rl_type = t->rl_basetype;
903 if (sc->rl_type == 0) {
904 device_printf(dev, "unknown device ID: %x assuming 8139\n",
906 sc->rl_type = RL_8139;
908 * Read RL_IDR register to get ethernet address as accessing
909 * EEPROM may not extract correct address.
911 for (i = 0; i < ETHER_ADDR_LEN; i++)
912 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
915 if ((error = rl_dma_alloc(sc)) != 0)
918 ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
920 device_printf(dev, "can not if_alloc()\n");
926 if (mii_phy_probe(dev, &sc->rl_miibus,
927 rl_ifmedia_upd, rl_ifmedia_sts)) {
928 device_printf(dev, "MII without any phy!\n");
934 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
935 ifp->if_mtu = ETHERMTU;
936 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
937 ifp->if_ioctl = rl_ioctl;
938 ifp->if_start = rl_start;
939 ifp->if_init = rl_init;
940 ifp->if_capabilities = IFCAP_VLAN_MTU;
941 ifp->if_capenable = ifp->if_capabilities;
942 #ifdef DEVICE_POLLING
943 ifp->if_capabilities |= IFCAP_POLLING;
945 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
946 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
947 IFQ_SET_READY(&ifp->if_snd);
950 * Call MI attach routine.
952 ether_ifattach(ifp, eaddr);
954 /* Hook interrupt last to avoid having to lock softc */
955 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
956 NULL, rl_intr, sc, &sc->rl_intrhand[0]);
958 device_printf(sc->rl_dev, "couldn't set up irq\n");
970 * Shutdown hardware and free up resources. This can be called any
971 * time after the mutex has been initialized. It is called in both
972 * the error case in attach and the normal detach case so it needs
973 * to be careful about only freeing resources that have actually been
977 rl_detach(device_t dev)
982 sc = device_get_softc(dev);
985 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
987 #ifdef DEVICE_POLLING
988 if (ifp->if_capenable & IFCAP_POLLING)
989 ether_poll_deregister(ifp);
991 /* These should only be active if attach succeeded */
992 if (device_is_attached(dev)) {
996 callout_drain(&sc->rl_stat_callout);
1003 device_delete_child(dev, sc->rl_miibus);
1004 bus_generic_detach(dev);
1006 if (sc->rl_intrhand[0])
1007 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1009 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1011 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
1018 mtx_destroy(&sc->rl_mtx);
1024 rl_dma_alloc(struct rl_softc *sc)
1026 struct rl_dmamap_arg ctx;
1030 * Allocate the parent bus DMA tag appropriate for PCI.
1032 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1033 1, 0, /* alignment, boundary */
1034 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1035 BUS_SPACE_MAXADDR, /* highaddr */
1036 NULL, NULL, /* filter, filterarg */
1037 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1038 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1040 NULL, NULL, /* lockfunc, lockarg */
1041 &sc->rl_parent_tag);
1043 device_printf(sc->rl_dev,
1044 "failed to create parent DMA tag.\n");
1047 /* Create DMA tag for Rx memory block. */
1048 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1049 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */
1050 BUS_SPACE_MAXADDR, /* lowaddr */
1051 BUS_SPACE_MAXADDR, /* highaddr */
1052 NULL, NULL, /* filter, filterarg */
1053 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */
1054 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */
1056 NULL, NULL, /* lockfunc, lockarg */
1057 &sc->rl_cdata.rl_rx_tag);
1059 device_printf(sc->rl_dev,
1060 "failed to create Rx memory block DMA tag.\n");
1063 /* Create DMA tag for Tx buffer. */
1064 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
1065 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */
1066 BUS_SPACE_MAXADDR, /* lowaddr */
1067 BUS_SPACE_MAXADDR, /* highaddr */
1068 NULL, NULL, /* filter, filterarg */
1069 MCLBYTES, 1, /* maxsize, nsegments */
1070 MCLBYTES, /* maxsegsize */
1072 NULL, NULL, /* lockfunc, lockarg */
1073 &sc->rl_cdata.rl_tx_tag);
1075 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
1080 * Allocate DMA'able memory and load DMA map for Rx memory block.
1082 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
1083 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
1084 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
1086 device_printf(sc->rl_dev,
1087 "failed to allocate Rx DMA memory block.\n");
1091 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
1092 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
1093 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
1095 if (error != 0 || ctx.rl_busaddr == 0) {
1096 device_printf(sc->rl_dev,
1097 "could not load Rx DMA memory block.\n");
1100 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
1102 /* Create DMA maps for Tx buffers. */
1103 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1104 sc->rl_cdata.rl_tx_chain[i] = NULL;
1105 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1106 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1107 &sc->rl_cdata.rl_tx_dmamap[i]);
1109 device_printf(sc->rl_dev,
1110 "could not create Tx dmamap.\n");
1115 /* Leave a few bytes before the start of the RX ring buffer. */
1116 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1117 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1124 rl_dma_free(struct rl_softc *sc)
1128 /* Rx memory block. */
1129 if (sc->rl_cdata.rl_rx_tag != NULL) {
1130 if (sc->rl_cdata.rl_rx_dmamap != NULL)
1131 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1132 sc->rl_cdata.rl_rx_dmamap);
1133 if (sc->rl_cdata.rl_rx_dmamap != NULL &&
1134 sc->rl_cdata.rl_rx_buf_ptr != NULL)
1135 bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1136 sc->rl_cdata.rl_rx_buf_ptr,
1137 sc->rl_cdata.rl_rx_dmamap);
1138 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1139 sc->rl_cdata.rl_rx_buf = NULL;
1140 sc->rl_cdata.rl_rx_dmamap = NULL;
1141 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1142 sc->rl_cdata.rl_tx_tag = NULL;
1146 if (sc->rl_cdata.rl_tx_tag != NULL) {
1147 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1148 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1150 sc->rl_cdata.rl_tx_tag,
1151 sc->rl_cdata.rl_tx_dmamap[i]);
1152 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1155 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1156 sc->rl_cdata.rl_tx_tag = NULL;
1159 if (sc->rl_parent_tag != NULL) {
1160 bus_dma_tag_destroy(sc->rl_parent_tag);
1161 sc->rl_parent_tag = NULL;
1166 * Initialize the transmit descriptors.
1169 rl_list_tx_init(struct rl_softc *sc)
1171 struct rl_chain_data *cd;
1177 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1178 cd->rl_tx_chain[i] = NULL;
1180 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1183 sc->rl_cdata.cur_tx = 0;
1184 sc->rl_cdata.last_tx = 0;
1190 rl_list_rx_init(struct rl_softc *sc)
1195 bzero(sc->rl_cdata.rl_rx_buf_ptr,
1196 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1197 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1198 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1204 * A frame has been uploaded: pass the resulting mbuf chain up to
1205 * the higher level protocols.
1207 * You know there's something wrong with a PCI bus-master chip design
1208 * when you have to use m_devget().
1210 * The receive operation is badly documented in the datasheet, so I'll
1211 * attempt to document it here. The driver provides a buffer area and
1212 * places its base address in the RX buffer start address register.
1213 * The chip then begins copying frames into the RX buffer. Each frame
1214 * is preceded by a 32-bit RX status word which specifies the length
1215 * of the frame and certain other status bits. Each frame (starting with
1216 * the status word) is also 32-bit aligned. The frame length is in the
1217 * first 16 bits of the status word; the lower 15 bits correspond with
1218 * the 'rx status register' mentioned in the datasheet.
1220 * Note: to make the Alpha happy, the frame payload needs to be aligned
1221 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1222 * as the offset argument to m_devget().
1225 rl_rxeof(struct rl_softc *sc)
1228 struct ifnet *ifp = sc->rl_ifp;
1236 uint16_t max_bytes, rx_bytes = 0;
1240 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1241 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1243 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1245 /* Do not try to read past this point. */
1246 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1249 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1251 max_bytes = limit - cur_rx;
1253 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1254 #ifdef DEVICE_POLLING
1255 if (ifp->if_capenable & IFCAP_POLLING) {
1256 if (sc->rxcycles <= 0)
1261 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1262 rxstat = le32toh(*(uint32_t *)rxbufpos);
1265 * Here's a totally undocumented fact for you. When the
1266 * RealTek chip is in the process of copying a packet into
1267 * RAM for you, the length will be 0xfff0. If you spot a
1268 * packet header with this value, you need to stop. The
1269 * datasheet makes absolutely no mention of this and
1270 * RealTek should be shot for this.
1272 total_len = rxstat >> 16;
1273 if (total_len == RL_RXSTAT_UNFINISHED)
1276 if (!(rxstat & RL_RXSTAT_RXOK) ||
1277 total_len < ETHER_MIN_LEN ||
1278 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1284 /* No errors; receive the packet. */
1285 rx_bytes += total_len + 4;
1288 * XXX The RealTek chip includes the CRC with every
1289 * received frame, and there's no way to turn this
1290 * behavior off (at least, I can't find anything in
1291 * the manual that explains how to do it) so we have
1292 * to trim off the CRC manually.
1294 total_len -= ETHER_CRC_LEN;
1297 * Avoid trying to read more bytes than we know
1298 * the chip has prepared for us.
1300 if (rx_bytes > max_bytes)
1303 rxbufpos = sc->rl_cdata.rl_rx_buf +
1304 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1305 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1306 rxbufpos = sc->rl_cdata.rl_rx_buf;
1308 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1309 if (total_len > wrap) {
1310 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1313 m_copyback(m, wrap, total_len - wrap,
1314 sc->rl_cdata.rl_rx_buf);
1315 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1317 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1319 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1322 /* Round up to 32-bit boundary. */
1323 cur_rx = (cur_rx + 3) & ~3;
1324 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1333 (*ifp->if_input)(ifp, m);
1338 /* No need to sync Rx memory block as we didn't modify it. */
1343 * A frame was downloaded to the chip. It's safe for us to clean up
1347 rl_txeof(struct rl_softc *sc)
1349 struct ifnet *ifp = sc->rl_ifp;
1355 * Go through our tx list and free mbufs for those
1356 * frames that have been uploaded.
1359 if (RL_LAST_TXMBUF(sc) == NULL)
1361 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1362 if (!(txstat & (RL_TXSTAT_TX_OK|
1363 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1366 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1368 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1369 BUS_DMASYNC_POSTWRITE);
1370 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1371 m_freem(RL_LAST_TXMBUF(sc));
1372 RL_LAST_TXMBUF(sc) = NULL;
1374 * If there was a transmit underrun, bump the TX threshold.
1375 * Make sure not to overflow the 63 * 32byte we can address
1376 * with the 6 available bit.
1378 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1379 (sc->rl_txthresh < 2016))
1380 sc->rl_txthresh += 32;
1381 if (txstat & RL_TXSTAT_TX_OK)
1386 if ((txstat & RL_TXSTAT_TXABRT) ||
1387 (txstat & RL_TXSTAT_OUTOFWIN))
1388 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1389 oldthresh = sc->rl_txthresh;
1390 /* error recovery */
1392 /* restore original threshold */
1393 sc->rl_txthresh = oldthresh;
1396 RL_INC(sc->rl_cdata.last_tx);
1397 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1398 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1400 if (RL_LAST_TXMBUF(sc) == NULL)
1401 sc->rl_watchdog_timer = 0;
1405 rl_twister_update(struct rl_softc *sc)
1409 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1410 * Linux driver. Values undocumented otherwise.
1412 static const uint32_t param[4][4] = {
1413 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1414 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1415 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1416 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1420 * Tune the so-called twister registers of the RTL8139. These
1421 * are used to compensate for impedance mismatches. The
1422 * method for tuning these registers is undocumented and the
1423 * following procedure is collected from public sources.
1425 switch (sc->rl_twister)
1429 * If we have a sufficient link, then we can proceed in
1430 * the state machine to the next stage. If not, then
1431 * disable further tuning after writing sane defaults.
1433 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1434 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1435 sc->rl_twister = FIND_ROW;
1437 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1438 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1439 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1440 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1441 sc->rl_twister = DONE;
1446 * Read how long it took to see the echo to find the tuning
1449 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1450 if (linktest == RL_CSCFG_ROW3)
1451 sc->rl_twist_row = 3;
1452 else if (linktest == RL_CSCFG_ROW2)
1453 sc->rl_twist_row = 2;
1454 else if (linktest == RL_CSCFG_ROW1)
1455 sc->rl_twist_row = 1;
1457 sc->rl_twist_row = 0;
1458 sc->rl_twist_col = 0;
1459 sc->rl_twister = SET_PARAM;
1462 if (sc->rl_twist_col == 0)
1463 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1464 CSR_WRITE_4(sc, RL_PARA7C,
1465 param[sc->rl_twist_row][sc->rl_twist_col]);
1466 if (++sc->rl_twist_col == 4) {
1467 if (sc->rl_twist_row == 3)
1468 sc->rl_twister = RECHK_LONG;
1470 sc->rl_twister = DONE;
1475 * For long cables, we have to double check to make sure we
1478 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1479 if (linktest == RL_CSCFG_ROW3)
1480 sc->rl_twister = DONE;
1482 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1483 sc->rl_twister = RETUNE;
1487 /* Retune for a shorter cable (try column 2) */
1488 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1489 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1490 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1491 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1493 sc->rl_twist_col = 0;
1494 sc->rl_twister = SET_PARAM;
1506 struct rl_softc *sc = xsc;
1507 struct mii_data *mii;
1512 * If we're doing the twister cable calibration, then we need to defer
1513 * watchdog timeouts. This is a no-op in normal operations, but
1514 * can falsely trigger when the cable calibration takes a while and
1515 * there was traffic ready to go when rl was started.
1517 * We don't defer mii_tick since that updates the mii status, which
1518 * helps the twister process, at least according to similar patches
1519 * for the Linux driver I found online while doing the fixes. Worst
1520 * case is a few extra mii reads during calibration.
1522 mii = device_get_softc(sc->rl_miibus);
1524 if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1525 rl_miibus_statchg(sc->rl_dev);
1526 if (sc->rl_twister_enable) {
1527 if (sc->rl_twister == DONE)
1530 rl_twister_update(sc);
1531 if (sc->rl_twister == DONE)
1540 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1543 #ifdef DEVICE_POLLING
1545 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1547 struct rl_softc *sc = ifp->if_softc;
1551 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1552 rx_npkts = rl_poll_locked(ifp, cmd, count);
1558 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1560 struct rl_softc *sc = ifp->if_softc;
1565 sc->rxcycles = count;
1566 rx_npkts = rl_rxeof(sc);
1569 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1570 rl_start_locked(ifp);
1572 if (cmd == POLL_AND_CHECK_STATUS) {
1575 /* We should also check the status register. */
1576 status = CSR_READ_2(sc, RL_ISR);
1577 if (status == 0xffff)
1580 CSR_WRITE_2(sc, RL_ISR, status);
1582 /* XXX We should check behaviour on receiver stalls. */
1584 if (status & RL_ISR_SYSTEM_ERR)
1589 #endif /* DEVICE_POLLING */
1594 struct rl_softc *sc = arg;
1595 struct ifnet *ifp = sc->rl_ifp;
1603 #ifdef DEVICE_POLLING
1604 if (ifp->if_capenable & IFCAP_POLLING)
1609 status = CSR_READ_2(sc, RL_ISR);
1610 /* If the card has gone away, the read returns 0xffff. */
1611 if (status == 0xffff)
1614 CSR_WRITE_2(sc, RL_ISR, status);
1615 if ((status & RL_INTRS) == 0)
1617 if (status & RL_ISR_RX_OK)
1619 if (status & RL_ISR_RX_ERR)
1621 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1623 if (status & RL_ISR_SYSTEM_ERR)
1627 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1628 rl_start_locked(ifp);
1635 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1636 * pointers to the fragment pointers.
1639 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1642 bus_dma_segment_t txsegs[1];
1643 int error, nsegs, padlen;
1650 * Hardware doesn't auto-pad, so we have to make sure
1651 * pad short frames out to the minimum frame length.
1653 if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1654 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1656 * The RealTek is brain damaged and wants longword-aligned
1657 * TX buffers, plus we can only have one fragment buffer
1658 * per packet. We have to copy pretty much all the time.
1660 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1661 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1662 m = m_defrag(*m_head, M_DONTWAIT);
1673 * Make security-conscious people happy: zero out the
1674 * bytes in the pad area, since we don't know what
1675 * this mbuf cluster buffer's previous user might
1678 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1679 m->m_pkthdr.len += padlen;
1680 m->m_len = m->m_pkthdr.len;
1683 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1684 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1693 RL_CUR_TXMBUF(sc) = m;
1694 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1695 BUS_DMASYNC_PREWRITE);
1696 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1702 * Main transmit routine.
1705 rl_start(struct ifnet *ifp)
1707 struct rl_softc *sc = ifp->if_softc;
1710 rl_start_locked(ifp);
1715 rl_start_locked(struct ifnet *ifp)
1717 struct rl_softc *sc = ifp->if_softc;
1718 struct mbuf *m_head = NULL;
1722 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1723 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1726 while (RL_CUR_TXMBUF(sc) == NULL) {
1728 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1733 if (rl_encap(sc, &m_head)) {
1736 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1737 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1741 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1742 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1744 /* Transmit the frame. */
1745 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1746 RL_TXTHRESH(sc->rl_txthresh) |
1747 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1749 RL_INC(sc->rl_cdata.cur_tx);
1751 /* Set a timeout in case the chip goes out to lunch. */
1752 sc->rl_watchdog_timer = 5;
1756 * We broke out of the loop because all our TX slots are
1757 * full. Mark the NIC as busy until it drains some of the
1758 * packets from the queue.
1760 if (RL_CUR_TXMBUF(sc) != NULL)
1761 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1767 struct rl_softc *sc = xsc;
1775 rl_init_locked(struct rl_softc *sc)
1777 struct ifnet *ifp = sc->rl_ifp;
1778 struct mii_data *mii;
1784 mii = device_get_softc(sc->rl_miibus);
1787 * Cancel pending I/O and free all RX/TX buffers.
1792 if (sc->rl_twister_enable) {
1794 * Reset twister register tuning state. The twister
1795 * registers and their tuning are undocumented, but
1796 * are necessary to cope with bad links. rl_twister =
1797 * DONE here will disable this entirely.
1799 sc->rl_twister = CHK_LINK;
1803 * Init our MAC address. Even though the chipset
1804 * documentation doesn't mention it, we need to enter "Config
1805 * register write enable" mode to modify the ID registers.
1807 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1808 bzero(eaddr, sizeof(eaddr));
1809 bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1810 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1811 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1812 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1814 /* Init the RX memory block pointer register. */
1815 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1816 RL_RX_8139_BUF_RESERVE);
1817 /* Init TX descriptors. */
1818 rl_list_tx_init(sc);
1819 /* Init Rx memory block. */
1820 rl_list_rx_init(sc);
1823 * Enable transmit and receive.
1825 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1828 * Set the initial TX and RX configuration.
1830 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1831 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1833 /* Set the individual bit to receive frames for this host only. */
1834 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1835 rxcfg |= RL_RXCFG_RX_INDIV;
1837 /* If we want promiscuous mode, set the allframes bit. */
1838 if (ifp->if_flags & IFF_PROMISC) {
1839 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1840 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1842 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1843 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1846 /* Set capture broadcast bit to capture broadcast frames. */
1847 if (ifp->if_flags & IFF_BROADCAST) {
1848 rxcfg |= RL_RXCFG_RX_BROAD;
1849 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1851 rxcfg &= ~RL_RXCFG_RX_BROAD;
1852 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1855 /* Program the multicast filter, if necessary. */
1858 #ifdef DEVICE_POLLING
1859 /* Disable interrupts if we are polling. */
1860 if (ifp->if_capenable & IFCAP_POLLING)
1861 CSR_WRITE_2(sc, RL_IMR, 0);
1864 /* Enable interrupts. */
1865 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1867 /* Set initial TX threshold */
1868 sc->rl_txthresh = RL_TX_THRESH_INIT;
1870 /* Start RX/TX process. */
1871 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1873 /* Enable receiver and transmitter. */
1874 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1876 sc->rl_flags &= ~RL_FLAG_LINK;
1879 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1881 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1882 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1884 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1888 * Set media options.
1891 rl_ifmedia_upd(struct ifnet *ifp)
1893 struct rl_softc *sc = ifp->if_softc;
1894 struct mii_data *mii;
1896 mii = device_get_softc(sc->rl_miibus);
1906 * Report current media status.
1909 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1911 struct rl_softc *sc = ifp->if_softc;
1912 struct mii_data *mii;
1914 mii = device_get_softc(sc->rl_miibus);
1919 ifmr->ifm_active = mii->mii_media_active;
1920 ifmr->ifm_status = mii->mii_media_status;
1924 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1926 struct ifreq *ifr = (struct ifreq *)data;
1927 struct mii_data *mii;
1928 struct rl_softc *sc = ifp->if_softc;
1934 if (ifp->if_flags & IFF_UP) {
1937 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1952 mii = device_get_softc(sc->rl_miibus);
1953 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1956 #ifdef DEVICE_POLLING
1957 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1958 !(ifp->if_capenable & IFCAP_POLLING)) {
1959 error = ether_poll_register(rl_poll, ifp);
1963 /* Disable interrupts */
1964 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1965 ifp->if_capenable |= IFCAP_POLLING;
1970 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1971 ifp->if_capenable & IFCAP_POLLING) {
1972 error = ether_poll_deregister(ifp);
1973 /* Enable interrupts. */
1975 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1976 ifp->if_capenable &= ~IFCAP_POLLING;
1980 #endif /* DEVICE_POLLING */
1983 error = ether_ioctl(ifp, command, data);
1991 rl_watchdog(struct rl_softc *sc)
1996 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
1999 device_printf(sc->rl_dev, "watchdog timeout\n");
2000 sc->rl_ifp->if_oerrors++;
2008 * Stop the adapter and free any mbufs allocated to the
2012 rl_stop(struct rl_softc *sc)
2015 struct ifnet *ifp = sc->rl_ifp;
2019 sc->rl_watchdog_timer = 0;
2020 callout_stop(&sc->rl_stat_callout);
2021 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2022 sc->rl_flags &= ~RL_FLAG_LINK;
2024 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2025 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2026 for (i = 0; i < RL_TIMEOUT; i++) {
2028 if ((CSR_READ_1(sc, RL_COMMAND) &
2029 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
2032 if (i == RL_TIMEOUT)
2033 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
2036 * Free the TX list buffers.
2038 for (i = 0; i < RL_TX_LIST_CNT; i++) {
2039 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2040 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2041 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
2042 sc->rl_cdata.rl_tx_dmamap[i],
2043 BUS_DMASYNC_POSTWRITE);
2044 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
2045 sc->rl_cdata.rl_tx_dmamap[i]);
2046 m_freem(sc->rl_cdata.rl_tx_chain[i]);
2047 sc->rl_cdata.rl_tx_chain[i] = NULL;
2049 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
2056 * Device suspend routine. Stop the interface and save some PCI
2057 * settings in case the BIOS doesn't restore them properly on
2061 rl_suspend(device_t dev)
2063 struct rl_softc *sc;
2065 sc = device_get_softc(dev);
2076 * Device resume routine. Restore some PCI settings in case the BIOS
2077 * doesn't, re-enable busmastering, and restart the interface if
2081 rl_resume(device_t dev)
2083 struct rl_softc *sc;
2086 sc = device_get_softc(dev);
2091 /* reinitialize interface if necessary */
2092 if (ifp->if_flags & IFF_UP)
2103 * Stop all chip I/O so that the kernel's probe routines don't
2104 * get confused by errant DMAs when rebooting.
2107 rl_shutdown(device_t dev)
2109 struct rl_softc *sc;
2111 sc = device_get_softc(dev);