sys/pci/if_rl.c

   1 /*-
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * RealTek 8129/8139 PCI NIC driver
  38  *
  39  * Supports several extremely cheap PCI 10/100 adapters based on
  40  * the RealTek chipset. Datasheets can be obtained from
  41  * www.realtek.com.tw.
  42  *
  43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  44  * Electrical Engineering Department
  45  * Columbia University, New York City
  46  */
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a longword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  */
  85
  86 #ifdef HAVE_KERNEL_OPTION_HEADERS
  87 #include "opt_device_polling.h"
  88 #endif
  89
  90 #include <sys/param.h>
  91 #include <sys/endian.h>
  92 #include <sys/systm.h>
  93 #include <sys/sockio.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/module.h>
  98 #include <sys/socket.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106 #include <net/if_types.h>
 107
 108 #include <net/bpf.h>
 109
 110 #include <machine/bus.h>
 111 #include <machine/resource.h>
 112 #include <sys/bus.h>
 113 #include <sys/rman.h>
 114
 115 #include <dev/mii/mii.h>
 116 #include <dev/mii/miivar.h>
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 MODULE_DEPEND(rl, pci, 1, 1, 1);
 122 MODULE_DEPEND(rl, ether, 1, 1, 1);
 123 MODULE_DEPEND(rl, miibus, 1, 1, 1);
 124
 125 /* "device miibus" required.  See GENERIC if you get errors here. */
 126 #include "miibus_if.h"
 127
 128 #include <pci/if_rlreg.h>
 129
 130 /*
 131  * Various supported device vendors/types and their names.
 132  */
 133 static struct rl_type rl_devs[] = {
 134         { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
 135                 "RealTek 8129 10/100BaseTX" },
 136         { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
 137                 "RealTek 8139 10/100BaseTX" },
 138         { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
 139                 "RealTek 8139 10/100BaseTX" },
 140         { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
 141                 "RealTek 8139 10/100BaseTX CardBus" },
 142         { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
 143                 "RealTek 8100 10/100BaseTX" },
 144         { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 145                 "Accton MPX 5030/5038 10/100BaseTX" },
 146         { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
 147                 "Delta Electronics 8139 10/100BaseTX" },
 148         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
 149                 "Addtron Technology 8139 10/100BaseTX" },
 150         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
 151                 "D-Link DFE-530TX+ 10/100BaseTX" },
 152         { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
 153                 "D-Link DFE-690TXD 10/100BaseTX" },
 154         { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 155                 "Nortel Networks 10/100BaseTX" },
 156         { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
 157                 "Corega FEther CB-TXD" },
 158         { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
 159                 "Corega FEtherII CB-TXD" },
 160         { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
 161                 "Peppercon AG ROL-F" },
 162         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
 163                 "Planex FNW-3603-TX" },
 164         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
 165                 "Planex FNW-3800-TX" },
 166         { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
 167                 "Compaq HNE-300" },
 168         { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
 169                 "LevelOne FPC-0106TX" },
 170         { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
 171                 "Edimax EP-4103DL CardBus" }
 172 };
 173
 174 static int rl_attach(device_t);
 175 static int rl_detach(device_t);
 176 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 177 static int rl_dma_alloc(struct rl_softc *);
 178 static void rl_dma_free(struct rl_softc *);
 179 static void rl_eeprom_putbyte(struct rl_softc *, int);
 180 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
 181 static int rl_encap(struct rl_softc *, struct mbuf **);
 182 static int rl_list_tx_init(struct rl_softc *);
 183 static int rl_list_rx_init(struct rl_softc *);
 184 static int rl_ifmedia_upd(struct ifnet *);
 185 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 186 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
 187 static void rl_intr(void *);
 188 static void rl_init(void *);
 189 static void rl_init_locked(struct rl_softc *sc);
 190 static void rl_mii_send(struct rl_softc *, uint32_t, int);
 191 static void rl_mii_sync(struct rl_softc *);
 192 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
 193 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
 194 static int rl_miibus_readreg(device_t, int, int);
 195 static void rl_miibus_statchg(device_t);
 196 static int rl_miibus_writereg(device_t, int, int, int);
 197 #ifdef DEVICE_POLLING
 198 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 199 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
 200 #endif
 201 static int rl_probe(device_t);
 202 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
 203 static void rl_reset(struct rl_softc *);
 204 static int rl_resume(device_t);
 205 static int rl_rxeof(struct rl_softc *);
 206 static void rl_rxfilter(struct rl_softc *);
 207 static int rl_shutdown(device_t);
 208 static void rl_start(struct ifnet *);
 209 static void rl_start_locked(struct ifnet *);
 210 static void rl_stop(struct rl_softc *);
 211 static int rl_suspend(device_t);
 212 static void rl_tick(void *);
 213 static void rl_txeof(struct rl_softc *);
 214 static void rl_watchdog(struct rl_softc *);
 215 static void rl_setwol(struct rl_softc *);
 216 static void rl_clrwol(struct rl_softc *);
 217
 218 static device_method_t rl_methods[] = {
 219         /* Device interface */
 220         DEVMETHOD(device_probe,         rl_probe),
 221         DEVMETHOD(device_attach,        rl_attach),
 222         DEVMETHOD(device_detach,        rl_detach),
 223         DEVMETHOD(device_suspend,       rl_suspend),
 224         DEVMETHOD(device_resume,        rl_resume),
 225         DEVMETHOD(device_shutdown,      rl_shutdown),
 226
 227         /* bus interface */
 228         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 229         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 230
 231         /* MII interface */
 232         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
 233         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
 234         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
 235
 236         { 0, 0 }
 237 };
 238
 239 static driver_t rl_driver = {
 240         "rl",
 241         rl_methods,
 242         sizeof(struct rl_softc)
 243 };
 244
 245 static devclass_t rl_devclass;
 246
 247 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
 248 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
 249 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
 250
 251 #define EE_SET(x)                                       \
 252         CSR_WRITE_1(sc, RL_EECMD,                       \
 253                 CSR_READ_1(sc, RL_EECMD) | x)
 254
 255 #define EE_CLR(x)                                       \
 256         CSR_WRITE_1(sc, RL_EECMD,                       \
 257                 CSR_READ_1(sc, RL_EECMD) & ~x)
 258
 259 /*
 260  * Send a read command and address to the EEPROM, check for ACK.
 261  */
 262 static void
 263 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
 264 {
 265         register int            d, i;
 266
 267         d = addr | sc->rl_eecmd_read;
 268
 269         /*
 270          * Feed in each bit and strobe the clock.
 271          */
 272         for (i = 0x400; i; i >>= 1) {
 273                 if (d & i) {
 274                         EE_SET(RL_EE_DATAIN);
 275                 } else {
 276                         EE_CLR(RL_EE_DATAIN);
 277                 }
 278                 DELAY(100);
 279                 EE_SET(RL_EE_CLK);
 280                 DELAY(150);
 281                 EE_CLR(RL_EE_CLK);
 282                 DELAY(100);
 283         }
 284 }
 285
 286 /*
 287  * Read a word of data stored in the EEPROM at address 'addr.'
 288  */
 289 static void
 290 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
 291 {
 292         register int            i;
 293         uint16_t                word = 0;
 294
 295         /* Enter EEPROM access mode. */
 296         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 297
 298         /*
 299          * Send address of word we want to read.
 300          */
 301         rl_eeprom_putbyte(sc, addr);
 302
 303         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 304
 305         /*
 306          * Start reading bits from EEPROM.
 307          */
 308         for (i = 0x8000; i; i >>= 1) {
 309                 EE_SET(RL_EE_CLK);
 310                 DELAY(100);
 311                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 312                         word |= i;
 313                 EE_CLR(RL_EE_CLK);
 314                 DELAY(100);
 315         }
 316
 317         /* Turn off EEPROM access mode. */
 318         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 319
 320         *dest = word;
 321 }
 322
 323 /*
 324  * Read a sequence of words from the EEPROM.
 325  */
 326 static void
 327 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
 328 {
 329         int                     i;
 330         uint16_t                word = 0, *ptr;
 331
 332         for (i = 0; i < cnt; i++) {
 333                 rl_eeprom_getword(sc, off + i, &word);
 334                 ptr = (uint16_t *)(dest + (i * 2));
 335                 if (swap)
 336                         *ptr = ntohs(word);
 337                 else
 338                         *ptr = word;
 339         }
 340 }
 341
 342 /*
 343  * MII access routines are provided for the 8129, which
 344  * doesn't have a built-in PHY. For the 8139, we fake things
 345  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 346  * direct access PHY registers.
 347  */
 348 #define MII_SET(x)                                      \
 349         CSR_WRITE_1(sc, RL_MII,                         \
 350                 CSR_READ_1(sc, RL_MII) | (x))
 351
 352 #define MII_CLR(x)                                      \
 353         CSR_WRITE_1(sc, RL_MII,                         \
 354                 CSR_READ_1(sc, RL_MII) & ~(x))
 355
 356 /*
 357  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 358  */
 359 static void
 360 rl_mii_sync(struct rl_softc *sc)
 361 {
 362         register int            i;
 363
 364         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 365
 366         for (i = 0; i < 32; i++) {
 367                 MII_SET(RL_MII_CLK);
 368                 DELAY(1);
 369                 MII_CLR(RL_MII_CLK);
 370                 DELAY(1);
 371         }
 372 }
 373
 374 /*
 375  * Clock a series of bits through the MII.
 376  */
 377 static void
 378 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
 379 {
 380         int                     i;
 381
 382         MII_CLR(RL_MII_CLK);
 383
 384         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 385                 if (bits & i) {
 386                         MII_SET(RL_MII_DATAOUT);
 387                 } else {
 388                         MII_CLR(RL_MII_DATAOUT);
 389                 }
 390                 DELAY(1);
 391                 MII_CLR(RL_MII_CLK);
 392                 DELAY(1);
 393                 MII_SET(RL_MII_CLK);
 394         }
 395 }
 396
 397 /*
 398  * Read an PHY register through the MII.
 399  */
 400 static int
 401 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
 402 {
 403         int                     i, ack;
 404
 405         /* Set up frame for RX. */
 406         frame->mii_stdelim = RL_MII_STARTDELIM;
 407         frame->mii_opcode = RL_MII_READOP;
 408         frame->mii_turnaround = 0;
 409         frame->mii_data = 0;
 410
 411         CSR_WRITE_2(sc, RL_MII, 0);
 412
 413         /* Turn on data xmit. */
 414         MII_SET(RL_MII_DIR);
 415
 416         rl_mii_sync(sc);
 417
 418         /* Send command/address info. */
 419         rl_mii_send(sc, frame->mii_stdelim, 2);
 420         rl_mii_send(sc, frame->mii_opcode, 2);
 421         rl_mii_send(sc, frame->mii_phyaddr, 5);
 422         rl_mii_send(sc, frame->mii_regaddr, 5);
 423
 424         /* Idle bit */
 425         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 426         DELAY(1);
 427         MII_SET(RL_MII_CLK);
 428         DELAY(1);
 429
 430         /* Turn off xmit. */
 431         MII_CLR(RL_MII_DIR);
 432
 433         /* Check for ack */
 434         MII_CLR(RL_MII_CLK);
 435         DELAY(1);
 436         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 437         MII_SET(RL_MII_CLK);
 438         DELAY(1);
 439
 440         /*
 441          * Now try reading data bits. If the ack failed, we still
 442          * need to clock through 16 cycles to keep the PHY(s) in sync.
 443          */
 444         if (ack) {
 445                 for(i = 0; i < 16; i++) {
 446                         MII_CLR(RL_MII_CLK);
 447                         DELAY(1);
 448                         MII_SET(RL_MII_CLK);
 449                         DELAY(1);
 450                 }
 451                 goto fail;
 452         }
 453
 454         for (i = 0x8000; i; i >>= 1) {
 455                 MII_CLR(RL_MII_CLK);
 456                 DELAY(1);
 457                 if (!ack) {
 458                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 459                                 frame->mii_data |= i;
 460                         DELAY(1);
 461                 }
 462                 MII_SET(RL_MII_CLK);
 463                 DELAY(1);
 464         }
 465
 466 fail:
 467         MII_CLR(RL_MII_CLK);
 468         DELAY(1);
 469         MII_SET(RL_MII_CLK);
 470         DELAY(1);
 471
 472         return (ack ? 1 : 0);
 473 }
 474
 475 /*
 476  * Write to a PHY register through the MII.
 477  */
 478 static int
 479 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
 480 {
 481
 482         /* Set up frame for TX. */
 483         frame->mii_stdelim = RL_MII_STARTDELIM;
 484         frame->mii_opcode = RL_MII_WRITEOP;
 485         frame->mii_turnaround = RL_MII_TURNAROUND;
 486
 487         /* Turn on data output. */
 488         MII_SET(RL_MII_DIR);
 489
 490         rl_mii_sync(sc);
 491
 492         rl_mii_send(sc, frame->mii_stdelim, 2);
 493         rl_mii_send(sc, frame->mii_opcode, 2);
 494         rl_mii_send(sc, frame->mii_phyaddr, 5);
 495         rl_mii_send(sc, frame->mii_regaddr, 5);
 496         rl_mii_send(sc, frame->mii_turnaround, 2);
 497         rl_mii_send(sc, frame->mii_data, 16);
 498
 499         /* Idle bit. */
 500         MII_SET(RL_MII_CLK);
 501         DELAY(1);
 502         MII_CLR(RL_MII_CLK);
 503         DELAY(1);
 504
 505         /* Turn off xmit. */
 506         MII_CLR(RL_MII_DIR);
 507
 508         return (0);
 509 }
 510
 511 static int
 512 rl_miibus_readreg(device_t dev, int phy, int reg)
 513 {
 514         struct rl_softc         *sc;
 515         struct rl_mii_frame     frame;
 516         uint16_t                rval = 0;
 517         uint16_t                rl8139_reg = 0;
 518
 519         sc = device_get_softc(dev);
 520
 521         if (sc->rl_type == RL_8139) {
 522                 /* Pretend the internal PHY is only at address 0 */
 523                 if (phy) {
 524                         return (0);
 525                 }
 526                 switch (reg) {
 527                 case MII_BMCR:
 528                         rl8139_reg = RL_BMCR;
 529                         break;
 530                 case MII_BMSR:
 531                         rl8139_reg = RL_BMSR;
 532                         break;
 533                 case MII_ANAR:
 534                         rl8139_reg = RL_ANAR;
 535                         break;
 536                 case MII_ANER:
 537                         rl8139_reg = RL_ANER;
 538                         break;
 539                 case MII_ANLPAR:
 540                         rl8139_reg = RL_LPAR;
 541                         break;
 542                 case MII_PHYIDR1:
 543                 case MII_PHYIDR2:
 544                         return (0);
 545                 /*
 546                  * Allow the rlphy driver to read the media status
 547                  * register. If we have a link partner which does not
 548                  * support NWAY, this is the register which will tell
 549                  * us the results of parallel detection.
 550                  */
 551                 case RL_MEDIASTAT:
 552                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
 553                         return (rval);
 554                 default:
 555                         device_printf(sc->rl_dev, "bad phy register\n");
 556                         return (0);
 557                 }
 558                 rval = CSR_READ_2(sc, rl8139_reg);
 559                 return (rval);
 560         }
 561
 562         bzero((char *)&frame, sizeof(frame));
 563         frame.mii_phyaddr = phy;
 564         frame.mii_regaddr = reg;
 565         rl_mii_readreg(sc, &frame);
 566
 567         return (frame.mii_data);
 568 }
 569
 570 static int
 571 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
 572 {
 573         struct rl_softc         *sc;
 574         struct rl_mii_frame     frame;
 575         uint16_t                rl8139_reg = 0;
 576
 577         sc = device_get_softc(dev);
 578
 579         if (sc->rl_type == RL_8139) {
 580                 /* Pretend the internal PHY is only at address 0 */
 581                 if (phy) {
 582                         return (0);
 583                 }
 584                 switch (reg) {
 585                 case MII_BMCR:
 586                         rl8139_reg = RL_BMCR;
 587                         break;
 588                 case MII_BMSR:
 589                         rl8139_reg = RL_BMSR;
 590                         break;
 591                 case MII_ANAR:
 592                         rl8139_reg = RL_ANAR;
 593                         break;
 594                 case MII_ANER:
 595                         rl8139_reg = RL_ANER;
 596                         break;
 597                 case MII_ANLPAR:
 598                         rl8139_reg = RL_LPAR;
 599                         break;
 600                 case MII_PHYIDR1:
 601                 case MII_PHYIDR2:
 602                         return (0);
 603                         break;
 604                 default:
 605                         device_printf(sc->rl_dev, "bad phy register\n");
 606                         return (0);
 607                 }
 608                 CSR_WRITE_2(sc, rl8139_reg, data);
 609                 return (0);
 610         }
 611
 612         bzero((char *)&frame, sizeof(frame));
 613         frame.mii_phyaddr = phy;
 614         frame.mii_regaddr = reg;
 615         frame.mii_data = data;
 616         rl_mii_writereg(sc, &frame);
 617
 618         return (0);
 619 }
 620
 621 static void
 622 rl_miibus_statchg(device_t dev)
 623 {
 624         struct rl_softc         *sc;
 625         struct ifnet            *ifp;
 626         struct mii_data         *mii;
 627
 628         sc = device_get_softc(dev);
 629         mii = device_get_softc(sc->rl_miibus);
 630         ifp = sc->rl_ifp;
 631         if (mii == NULL || ifp == NULL ||
 632             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 633                 return;
 634
 635         sc->rl_flags &= ~RL_FLAG_LINK;
 636         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 637             (IFM_ACTIVE | IFM_AVALID)) {
 638                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 639                 case IFM_10_T:
 640                 case IFM_100_TX:
 641                         sc->rl_flags |= RL_FLAG_LINK;
 642                         break;
 643                 default:
 644                         break;
 645                 }
 646         }
 647         /*
 648          * RealTek controllers do not provide any interface to
 649          * Tx/Rx MACs for resolved speed, duplex and flow-control
 650          * parameters.
 651          */
 652 }
 653
 654 /*
 655  * Program the 64-bit multicast hash filter.
 656  */
 657 static void
 658 rl_rxfilter(struct rl_softc *sc)
 659 {
 660         struct ifnet            *ifp = sc->rl_ifp;
 661         int                     h = 0;
 662         uint32_t                hashes[2] = { 0, 0 };
 663         struct ifmultiaddr      *ifma;
 664         uint32_t                rxfilt;
 665
 666         RL_LOCK_ASSERT(sc);
 667
 668         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 669         rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
 670             RL_RXCFG_RX_MULTI);
 671         /* Always accept frames destined for this host. */
 672         rxfilt |= RL_RXCFG_RX_INDIV;
 673         /* Set capture broadcast bit to capture broadcast frames. */
 674         if (ifp->if_flags & IFF_BROADCAST)
 675                 rxfilt |= RL_RXCFG_RX_BROAD;
 676         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 677                 rxfilt |= RL_RXCFG_RX_MULTI;
 678                 if (ifp->if_flags & IFF_PROMISC)
 679                         rxfilt |= RL_RXCFG_RX_ALLPHYS;
 680                 hashes[0] = 0xFFFFFFFF;
 681                 hashes[1] = 0xFFFFFFFF;
 682         } else {
 683                 /* Now program new ones. */
 684                 if_maddr_rlock(ifp);
 685                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 686                         if (ifma->ifma_addr->sa_family != AF_LINK)
 687                                 continue;
 688                         h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 689                             ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 690                         if (h < 32)
 691                                 hashes[0] |= (1 << h);
 692                         else
 693                                 hashes[1] |= (1 << (h - 32));
 694                 }
 695                 if_maddr_runlock(ifp);
 696                 if (hashes[0] != 0 || hashes[1] != 0)
 697                         rxfilt |= RL_RXCFG_RX_MULTI;
 698         }
 699
 700         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 701         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 702         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 703 }
 704
 705 static void
 706 rl_reset(struct rl_softc *sc)
 707 {
 708         register int            i;
 709
 710         RL_LOCK_ASSERT(sc);
 711
 712         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 713
 714         for (i = 0; i < RL_TIMEOUT; i++) {
 715                 DELAY(10);
 716                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 717                         break;
 718         }
 719         if (i == RL_TIMEOUT)
 720                 device_printf(sc->rl_dev, "reset never completed!\n");
 721 }
 722
 723 /*
 724  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 725  * IDs against our list and return a device name if we find a match.
 726  */
 727 static int
 728 rl_probe(device_t dev)
 729 {
 730         struct rl_type          *t;
 731         uint16_t                devid, revid, vendor;
 732         int                     i;
 733
 734         vendor = pci_get_vendor(dev);
 735         devid = pci_get_device(dev);
 736         revid = pci_get_revid(dev);
 737
 738         if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
 739                 if (revid == 0x20) {
 740                         /* 8139C+, let re(4) take care of this device. */
 741                         return (ENXIO);
 742                 }
 743         }
 744         t = rl_devs;
 745         for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
 746                 if (vendor == t->rl_vid && devid == t->rl_did) {
 747                         device_set_desc(dev, t->rl_name);
 748                         return (BUS_PROBE_DEFAULT);
 749                 }
 750         }
 751
 752         return (ENXIO);
 753 }
 754
 755 struct rl_dmamap_arg {
 756         bus_addr_t      rl_busaddr;
 757 };
 758
 759 static void
 760 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 761 {
 762         struct rl_dmamap_arg    *ctx;
 763
 764         if (error != 0)
 765                 return;
 766
 767         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 768
 769         ctx = (struct rl_dmamap_arg *)arg;
 770         ctx->rl_busaddr = segs[0].ds_addr;
 771 }
 772
 773 /*
 774  * Attach the interface. Allocate softc structures, do ifmedia
 775  * setup and ethernet/BPF attach.
 776  */
 777 static int
 778 rl_attach(device_t dev)
 779 {
 780         uint8_t                 eaddr[ETHER_ADDR_LEN];
 781         uint16_t                as[3];
 782         struct ifnet            *ifp;
 783         struct rl_softc         *sc;
 784         struct rl_type          *t;
 785         struct sysctl_ctx_list  *ctx;
 786         struct sysctl_oid_list  *children;
 787         int                     error = 0, hwrev, i, pmc, rid;
 788         int                     prefer_iomap, unit;
 789         uint16_t                rl_did = 0;
 790         char                    tn[32];
 791
 792         sc = device_get_softc(dev);
 793         unit = device_get_unit(dev);
 794         sc->rl_dev = dev;
 795
 796         sc->rl_twister_enable = 0;
 797         snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
 798         TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
 799         ctx = device_get_sysctl_ctx(sc->rl_dev);
 800         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
 801         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
 802            &sc->rl_twister_enable, 0, "");
 803
 804         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 805             MTX_DEF);
 806         callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
 807
 808         pci_enable_busmaster(dev);
 809
 810
 811         /*
 812          * Map control/status registers.
 813          * Default to using PIO access for this driver. On SMP systems,
 814          * there appear to be problems with memory mapped mode: it looks
 815          * like doing too many memory mapped access back to back in rapid
 816          * succession can hang the bus. I'm inclined to blame this on
 817          * crummy design/construction on the part of RealTek. Memory
 818          * mapped mode does appear to work on uniprocessor systems though.
 819          */
 820         prefer_iomap = 1;
 821         snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
 822         TUNABLE_INT_FETCH(tn, &prefer_iomap);
 823         if (prefer_iomap) {
 824                 sc->rl_res_id = PCIR_BAR(0);
 825                 sc->rl_res_type = SYS_RES_IOPORT;
 826                 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
 827                     &sc->rl_res_id, RF_ACTIVE);
 828         }
 829         if (prefer_iomap == 0 || sc->rl_res == NULL) {
 830                 sc->rl_res_id = PCIR_BAR(1);
 831                 sc->rl_res_type = SYS_RES_MEMORY;
 832                 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
 833                     &sc->rl_res_id, RF_ACTIVE);
 834         }
 835         if (sc->rl_res == NULL) {
 836                 device_printf(dev, "couldn't map ports/memory\n");
 837                 error = ENXIO;
 838                 goto fail;
 839         }
 840
 841 #ifdef notdef
 842         /*
 843          * Detect the Realtek 8139B. For some reason, this chip is very
 844          * unstable when left to autoselect the media
 845          * The best workaround is to set the device to the required
 846          * media type or to set it to the 10 Meg speed.
 847          */
 848         if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
 849                 device_printf(dev,
 850 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
 851 #endif
 852
 853         sc->rl_btag = rman_get_bustag(sc->rl_res);
 854         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
 855
 856         /* Allocate interrupt */
 857         rid = 0;
 858         sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 859             RF_SHAREABLE | RF_ACTIVE);
 860
 861         if (sc->rl_irq[0] == NULL) {
 862                 device_printf(dev, "couldn't map interrupt\n");
 863                 error = ENXIO;
 864                 goto fail;
 865         }
 866
 867         /*
 868          * Reset the adapter. Only take the lock here as it's needed in
 869          * order to call rl_reset().
 870          */
 871         RL_LOCK(sc);
 872         rl_reset(sc);
 873         RL_UNLOCK(sc);
 874
 875         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
 876         rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
 877         if (rl_did != 0x8129)
 878                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
 879
 880         /*
 881          * Get station address from the EEPROM.
 882          */
 883         rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
 884         for (i = 0; i < 3; i++) {
 885                 eaddr[(i * 2) + 0] = as[i] & 0xff;
 886                 eaddr[(i * 2) + 1] = as[i] >> 8;
 887         }
 888
 889         /*
 890          * Now read the exact device type from the EEPROM to find
 891          * out if it's an 8129 or 8139.
 892          */
 893         rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
 894
 895         t = rl_devs;
 896         sc->rl_type = 0;
 897         while(t->rl_name != NULL) {
 898                 if (rl_did == t->rl_did) {
 899                         sc->rl_type = t->rl_basetype;
 900                         break;
 901                 }
 902                 t++;
 903         }
 904
 905         if (sc->rl_type == 0) {
 906                 device_printf(dev, "unknown device ID: %x assuming 8139\n",
 907                     rl_did);
 908                 sc->rl_type = RL_8139;
 909                 /*
 910                  * Read RL_IDR register to get ethernet address as accessing
 911                  * EEPROM may not extract correct address.
 912                  */
 913                 for (i = 0; i < ETHER_ADDR_LEN; i++)
 914                         eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
 915         }
 916
 917         if ((error = rl_dma_alloc(sc)) != 0)
 918                 goto fail;
 919
 920         ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
 921         if (ifp == NULL) {
 922                 device_printf(dev, "can not if_alloc()\n");
 923                 error = ENOSPC;
 924                 goto fail;
 925         }
 926
 927         /* Do MII setup */
 928         if (mii_phy_probe(dev, &sc->rl_miibus,
 929             rl_ifmedia_upd, rl_ifmedia_sts)) {
 930                 device_printf(dev, "MII without any phy!\n");
 931                 error = ENXIO;
 932                 goto fail;
 933         }
 934
 935         ifp->if_softc = sc;
 936         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 937         ifp->if_mtu = ETHERMTU;
 938         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 939         ifp->if_ioctl = rl_ioctl;
 940         ifp->if_start = rl_start;
 941         ifp->if_init = rl_init;
 942         ifp->if_capabilities = IFCAP_VLAN_MTU;
 943         /* Check WOL for RTL8139B or newer controllers. */
 944         if (sc->rl_type == RL_8139 &&
 945             pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
 946                 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
 947                 switch (hwrev) {
 948                 case RL_HWREV_8139B:
 949                 case RL_HWREV_8130:
 950                 case RL_HWREV_8139C:
 951                 case RL_HWREV_8139D:
 952                 case RL_HWREV_8101:
 953                 case RL_HWREV_8100:
 954                         ifp->if_capabilities |= IFCAP_WOL;
 955                         /* Disable WOL. */
 956                         rl_clrwol(sc);
 957                         break;
 958                 default:
 959                         break;
 960                 }
 961         }
 962         ifp->if_capenable = ifp->if_capabilities;
 963 #ifdef DEVICE_POLLING
 964         ifp->if_capabilities |= IFCAP_POLLING;
 965 #endif
 966         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
 967         ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
 968         IFQ_SET_READY(&ifp->if_snd);
 969
 970         /*
 971          * Call MI attach routine.
 972          */
 973         ether_ifattach(ifp, eaddr);
 974
 975         /* Hook interrupt last to avoid having to lock softc */
 976         error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
 977             NULL, rl_intr, sc, &sc->rl_intrhand[0]);
 978         if (error) {
 979                 device_printf(sc->rl_dev, "couldn't set up irq\n");
 980                 ether_ifdetach(ifp);
 981         }
 982
 983 fail:
 984         if (error)
 985                 rl_detach(dev);
 986
 987         return (error);
 988 }
 989
 990 /*
 991  * Shutdown hardware and free up resources. This can be called any
 992  * time after the mutex has been initialized. It is called in both
 993  * the error case in attach and the normal detach case so it needs
 994  * to be careful about only freeing resources that have actually been
 995  * allocated.
 996  */
 997 static int
 998 rl_detach(device_t dev)
 999 {
1000         struct rl_softc         *sc;
1001         struct ifnet            *ifp;
1002
1003         sc = device_get_softc(dev);
1004         ifp = sc->rl_ifp;
1005
1006         KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1007
1008 #ifdef DEVICE_POLLING
1009         if (ifp->if_capenable & IFCAP_POLLING)
1010                 ether_poll_deregister(ifp);
1011 #endif
1012         /* These should only be active if attach succeeded */
1013         if (device_is_attached(dev)) {
1014                 RL_LOCK(sc);
1015                 rl_stop(sc);
1016                 RL_UNLOCK(sc);
1017                 callout_drain(&sc->rl_stat_callout);
1018                 ether_ifdetach(ifp);
1019         }
1020 #if 0
1021         sc->suspended = 1;
1022 #endif
1023         if (sc->rl_miibus)
1024                 device_delete_child(dev, sc->rl_miibus);
1025         bus_generic_detach(dev);
1026
1027         if (sc->rl_intrhand[0])
1028                 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1029         if (sc->rl_irq[0])
1030                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1031         if (sc->rl_res)
1032                 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1033                     sc->rl_res);
1034
1035         if (ifp)
1036                 if_free(ifp);
1037
1038         rl_dma_free(sc);
1039
1040         mtx_destroy(&sc->rl_mtx);
1041
1042         return (0);
1043 }
1044
1045 static int
1046 rl_dma_alloc(struct rl_softc *sc)
1047 {
1048         struct rl_dmamap_arg    ctx;
1049         int                     error, i;
1050
1051         /*
1052          * Allocate the parent bus DMA tag appropriate for PCI.
1053          */
1054         error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1055             1, 0,                       /* alignment, boundary */
1056             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1057             BUS_SPACE_MAXADDR,          /* highaddr */
1058             NULL, NULL,                 /* filter, filterarg */
1059             BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1060             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1061             0,                          /* flags */
1062             NULL, NULL,                 /* lockfunc, lockarg */
1063             &sc->rl_parent_tag);
1064         if (error) {
1065                 device_printf(sc->rl_dev,
1066                     "failed to create parent DMA tag.\n");
1067                 goto fail;
1068         }
1069         /* Create DMA tag for Rx memory block. */
1070         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1071             RL_RX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1072             BUS_SPACE_MAXADDR,          /* lowaddr */
1073             BUS_SPACE_MAXADDR,          /* highaddr */
1074             NULL, NULL,                 /* filter, filterarg */
1075             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1,   /* maxsize,nsegments */
1076             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ,      /* maxsegsize */
1077             0,                          /* flags */
1078             NULL, NULL,                 /* lockfunc, lockarg */
1079             &sc->rl_cdata.rl_rx_tag);
1080         if (error) {
1081                 device_printf(sc->rl_dev,
1082                     "failed to create Rx memory block DMA tag.\n");
1083                 goto fail;
1084         }
1085         /* Create DMA tag for Tx buffer. */
1086         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1087             RL_TX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1088             BUS_SPACE_MAXADDR,          /* lowaddr */
1089             BUS_SPACE_MAXADDR,          /* highaddr */
1090             NULL, NULL,                 /* filter, filterarg */
1091             MCLBYTES, 1,                /* maxsize, nsegments */
1092             MCLBYTES,                   /* maxsegsize */
1093             0,                          /* flags */
1094             NULL, NULL,                 /* lockfunc, lockarg */
1095             &sc->rl_cdata.rl_tx_tag);
1096         if (error) {
1097                 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
1098                 goto fail;
1099         }
1100
1101         /*
1102          * Allocate DMA'able memory and load DMA map for Rx memory block.
1103          */
1104         error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
1105             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
1106             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
1107         if (error != 0) {
1108                 device_printf(sc->rl_dev,
1109                     "failed to allocate Rx DMA memory block.\n");
1110                 goto fail;
1111         }
1112         ctx.rl_busaddr = 0;
1113         error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
1114             sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
1115             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
1116             BUS_DMA_NOWAIT);
1117         if (error != 0 || ctx.rl_busaddr == 0) {
1118                 device_printf(sc->rl_dev,
1119                     "could not load Rx DMA memory block.\n");
1120                 goto fail;
1121         }
1122         sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
1123
1124         /* Create DMA maps for Tx buffers. */
1125         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1126                 sc->rl_cdata.rl_tx_chain[i] = NULL;
1127                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1128                 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1129                     &sc->rl_cdata.rl_tx_dmamap[i]);
1130                 if (error != 0) {
1131                         device_printf(sc->rl_dev,
1132                             "could not create Tx dmamap.\n");
1133                         goto fail;
1134                 }
1135         }
1136
1137         /* Leave a few bytes before the start of the RX ring buffer. */
1138         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1139         sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1140
1141 fail:
1142         return (error);
1143 }
1144
1145 static void
1146 rl_dma_free(struct rl_softc *sc)
1147 {
1148         int                     i;
1149
1150         /* Rx memory block. */
1151         if (sc->rl_cdata.rl_rx_tag != NULL) {
1152                 if (sc->rl_cdata.rl_rx_dmamap != NULL)
1153                         bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1154                             sc->rl_cdata.rl_rx_dmamap);
1155                 if (sc->rl_cdata.rl_rx_dmamap != NULL &&
1156                     sc->rl_cdata.rl_rx_buf_ptr != NULL)
1157                         bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1158                             sc->rl_cdata.rl_rx_buf_ptr,
1159                             sc->rl_cdata.rl_rx_dmamap);
1160                 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1161                 sc->rl_cdata.rl_rx_buf = NULL;
1162                 sc->rl_cdata.rl_rx_dmamap = NULL;
1163                 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1164                 sc->rl_cdata.rl_tx_tag = NULL;
1165         }
1166
1167         /* Tx buffers. */
1168         if (sc->rl_cdata.rl_tx_tag != NULL) {
1169                 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1170                         if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1171                                 bus_dmamap_destroy(
1172                                     sc->rl_cdata.rl_tx_tag,
1173                                     sc->rl_cdata.rl_tx_dmamap[i]);
1174                                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1175                         }
1176                 }
1177                 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1178                 sc->rl_cdata.rl_tx_tag = NULL;
1179         }
1180
1181         if (sc->rl_parent_tag != NULL) {
1182                 bus_dma_tag_destroy(sc->rl_parent_tag);
1183                 sc->rl_parent_tag = NULL;
1184         }
1185 }
1186
1187 /*
1188  * Initialize the transmit descriptors.
1189  */
1190 static int
1191 rl_list_tx_init(struct rl_softc *sc)
1192 {
1193         struct rl_chain_data    *cd;
1194         int                     i;
1195
1196         RL_LOCK_ASSERT(sc);
1197
1198         cd = &sc->rl_cdata;
1199         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1200                 cd->rl_tx_chain[i] = NULL;
1201                 CSR_WRITE_4(sc,
1202                     RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1203         }
1204
1205         sc->rl_cdata.cur_tx = 0;
1206         sc->rl_cdata.last_tx = 0;
1207
1208         return (0);
1209 }
1210
1211 static int
1212 rl_list_rx_init(struct rl_softc *sc)
1213 {
1214
1215         RL_LOCK_ASSERT(sc);
1216
1217         bzero(sc->rl_cdata.rl_rx_buf_ptr,
1218             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1219         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1220             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1221
1222         return (0);
1223 }
1224
1225 /*
1226  * A frame has been uploaded: pass the resulting mbuf chain up to
1227  * the higher level protocols.
1228  *
1229  * You know there's something wrong with a PCI bus-master chip design
1230  * when you have to use m_devget().
1231  *
1232  * The receive operation is badly documented in the datasheet, so I'll
1233  * attempt to document it here. The driver provides a buffer area and
1234  * places its base address in the RX buffer start address register.
1235  * The chip then begins copying frames into the RX buffer. Each frame
1236  * is preceded by a 32-bit RX status word which specifies the length
1237  * of the frame and certain other status bits. Each frame (starting with
1238  * the status word) is also 32-bit aligned. The frame length is in the
1239  * first 16 bits of the status word; the lower 15 bits correspond with
1240  * the 'rx status register' mentioned in the datasheet.
1241  *
1242  * Note: to make the Alpha happy, the frame payload needs to be aligned
1243  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1244  * as the offset argument to m_devget().
1245  */
1246 static int
1247 rl_rxeof(struct rl_softc *sc)
1248 {
1249         struct mbuf             *m;
1250         struct ifnet            *ifp = sc->rl_ifp;
1251         uint8_t                 *rxbufpos;
1252         int                     total_len = 0;
1253         int                     wrap = 0;
1254         int                     rx_npkts = 0;
1255         uint32_t                rxstat;
1256         uint16_t                cur_rx;
1257         uint16_t                limit;
1258         uint16_t                max_bytes, rx_bytes = 0;
1259
1260         RL_LOCK_ASSERT(sc);
1261
1262         bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1263             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1264
1265         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1266
1267         /* Do not try to read past this point. */
1268         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1269
1270         if (limit < cur_rx)
1271                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1272         else
1273                 max_bytes = limit - cur_rx;
1274
1275         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1276 #ifdef DEVICE_POLLING
1277                 if (ifp->if_capenable & IFCAP_POLLING) {
1278                         if (sc->rxcycles <= 0)
1279                                 break;
1280                         sc->rxcycles--;
1281                 }
1282 #endif
1283                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1284                 rxstat = le32toh(*(uint32_t *)rxbufpos);
1285
1286                 /*
1287                  * Here's a totally undocumented fact for you. When the
1288                  * RealTek chip is in the process of copying a packet into
1289                  * RAM for you, the length will be 0xfff0. If you spot a
1290                  * packet header with this value, you need to stop. The
1291                  * datasheet makes absolutely no mention of this and
1292                  * RealTek should be shot for this.
1293                  */
1294                 total_len = rxstat >> 16;
1295                 if (total_len == RL_RXSTAT_UNFINISHED)
1296                         break;
1297
1298                 if (!(rxstat & RL_RXSTAT_RXOK) ||
1299                     total_len < ETHER_MIN_LEN ||
1300                     total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1301                         ifp->if_ierrors++;
1302                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1303                         rl_init_locked(sc);
1304                         return (rx_npkts);
1305                 }
1306
1307                 /* No errors; receive the packet. */
1308                 rx_bytes += total_len + 4;
1309
1310                 /*
1311                  * XXX The RealTek chip includes the CRC with every
1312                  * received frame, and there's no way to turn this
1313                  * behavior off (at least, I can't find anything in
1314                  * the manual that explains how to do it) so we have
1315                  * to trim off the CRC manually.
1316                  */
1317                 total_len -= ETHER_CRC_LEN;
1318
1319                 /*
1320                  * Avoid trying to read more bytes than we know
1321                  * the chip has prepared for us.
1322                  */
1323                 if (rx_bytes > max_bytes)
1324                         break;
1325
1326                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1327                         ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1328                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1329                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1330
1331                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1332                 if (total_len > wrap) {
1333                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1334                             NULL);
1335                         if (m != NULL)
1336                                 m_copyback(m, wrap, total_len - wrap,
1337                                         sc->rl_cdata.rl_rx_buf);
1338                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1339                 } else {
1340                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1341                             NULL);
1342                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
1343                 }
1344
1345                 /* Round up to 32-bit boundary. */
1346                 cur_rx = (cur_rx + 3) & ~3;
1347                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1348
1349                 if (m == NULL) {
1350                         ifp->if_iqdrops++;
1351                         continue;
1352                 }
1353
1354                 ifp->if_ipackets++;
1355                 RL_UNLOCK(sc);
1356                 (*ifp->if_input)(ifp, m);
1357                 RL_LOCK(sc);
1358                 rx_npkts++;
1359         }
1360
1361         /* No need to sync Rx memory block as we didn't modify it. */
1362         return (rx_npkts);
1363 }
1364
1365 /*
1366  * A frame was downloaded to the chip. It's safe for us to clean up
1367  * the list buffers.
1368  */
1369 static void
1370 rl_txeof(struct rl_softc *sc)
1371 {
1372         struct ifnet            *ifp = sc->rl_ifp;
1373         uint32_t                txstat;
1374
1375         RL_LOCK_ASSERT(sc);
1376
1377         /*
1378          * Go through our tx list and free mbufs for those
1379          * frames that have been uploaded.
1380          */
1381         do {
1382                 if (RL_LAST_TXMBUF(sc) == NULL)
1383                         break;
1384                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1385                 if (!(txstat & (RL_TXSTAT_TX_OK|
1386                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1387                         break;
1388
1389                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1390
1391                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1392                     BUS_DMASYNC_POSTWRITE);
1393                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1394                 m_freem(RL_LAST_TXMBUF(sc));
1395                 RL_LAST_TXMBUF(sc) = NULL;
1396                 /*
1397                  * If there was a transmit underrun, bump the TX threshold.
1398                  * Make sure not to overflow the 63 * 32byte we can address
1399                  * with the 6 available bit.
1400                  */
1401                 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1402                     (sc->rl_txthresh < 2016))
1403                         sc->rl_txthresh += 32;
1404                 if (txstat & RL_TXSTAT_TX_OK)
1405                         ifp->if_opackets++;
1406                 else {
1407                         int                     oldthresh;
1408                         ifp->if_oerrors++;
1409                         if ((txstat & RL_TXSTAT_TXABRT) ||
1410                             (txstat & RL_TXSTAT_OUTOFWIN))
1411                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1412                         oldthresh = sc->rl_txthresh;
1413                         /* error recovery */
1414                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1415                         rl_init_locked(sc);
1416                         /* restore original threshold */
1417                         sc->rl_txthresh = oldthresh;
1418                         return;
1419                 }
1420                 RL_INC(sc->rl_cdata.last_tx);
1421                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1422         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1423
1424         if (RL_LAST_TXMBUF(sc) == NULL)
1425                 sc->rl_watchdog_timer = 0;
1426 }
1427
1428 static void
1429 rl_twister_update(struct rl_softc *sc)
1430 {
1431         uint16_t linktest;
1432         /*
1433          * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1434          * Linux driver.  Values undocumented otherwise.
1435          */
1436         static const uint32_t param[4][4] = {
1437                 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1438                 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1439                 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1440                 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1441         };
1442
1443         /*
1444          * Tune the so-called twister registers of the RTL8139.  These
1445          * are used to compensate for impedance mismatches.  The
1446          * method for tuning these registers is undocumented and the
1447          * following procedure is collected from public sources.
1448          */
1449         switch (sc->rl_twister)
1450         {
1451         case CHK_LINK:
1452                 /*
1453                  * If we have a sufficient link, then we can proceed in
1454                  * the state machine to the next stage.  If not, then
1455                  * disable further tuning after writing sane defaults.
1456                  */
1457                 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1458                         CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1459                         sc->rl_twister = FIND_ROW;
1460                 } else {
1461                         CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1462                         CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1463                         CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1464                         CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1465                         sc->rl_twister = DONE;
1466                 }
1467                 break;
1468         case FIND_ROW:
1469                 /*
1470                  * Read how long it took to see the echo to find the tuning
1471                  * row to use.
1472                  */
1473                 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1474                 if (linktest == RL_CSCFG_ROW3)
1475                         sc->rl_twist_row = 3;
1476                 else if (linktest == RL_CSCFG_ROW2)
1477                         sc->rl_twist_row = 2;
1478                 else if (linktest == RL_CSCFG_ROW1)
1479                         sc->rl_twist_row = 1;
1480                 else
1481                         sc->rl_twist_row = 0;
1482                 sc->rl_twist_col = 0;
1483                 sc->rl_twister = SET_PARAM;
1484                 break;
1485         case SET_PARAM:
1486                 if (sc->rl_twist_col == 0)
1487                         CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1488                 CSR_WRITE_4(sc, RL_PARA7C,
1489                     param[sc->rl_twist_row][sc->rl_twist_col]);
1490                 if (++sc->rl_twist_col == 4) {
1491                         if (sc->rl_twist_row == 3)
1492                                 sc->rl_twister = RECHK_LONG;
1493                         else
1494                                 sc->rl_twister = DONE;
1495                 }
1496                 break;
1497         case RECHK_LONG:
1498                 /*
1499                  * For long cables, we have to double check to make sure we
1500                  * don't mistune.
1501                  */
1502                 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1503                 if (linktest == RL_CSCFG_ROW3)
1504                         sc->rl_twister = DONE;
1505                 else {
1506                         CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1507                         sc->rl_twister = RETUNE;
1508                 }
1509                 break;
1510         case RETUNE:
1511                 /* Retune for a shorter cable (try column 2) */
1512                 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1513                 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1514                 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1515                 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1516                 sc->rl_twist_row--;
1517                 sc->rl_twist_col = 0;
1518                 sc->rl_twister = SET_PARAM;
1519                 break;
1520
1521         case DONE:
1522                 break;
1523         }
1524
1525 }
1526
1527 static void
1528 rl_tick(void *xsc)
1529 {
1530         struct rl_softc         *sc = xsc;
1531         struct mii_data         *mii;
1532         int ticks;
1533
1534         RL_LOCK_ASSERT(sc);
1535         /*
1536          * If we're doing the twister cable calibration, then we need to defer
1537          * watchdog timeouts.  This is a no-op in normal operations, but
1538          * can falsely trigger when the cable calibration takes a while and
1539          * there was traffic ready to go when rl was started.
1540          *
1541          * We don't defer mii_tick since that updates the mii status, which
1542          * helps the twister process, at least according to similar patches
1543          * for the Linux driver I found online while doing the fixes.  Worst
1544          * case is a few extra mii reads during calibration.
1545          */
1546         mii = device_get_softc(sc->rl_miibus);
1547         mii_tick(mii);
1548         if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1549                 rl_miibus_statchg(sc->rl_dev);
1550         if (sc->rl_twister_enable) {
1551                 if (sc->rl_twister == DONE)
1552                         rl_watchdog(sc);
1553                 else
1554                         rl_twister_update(sc);
1555                 if (sc->rl_twister == DONE)
1556                         ticks = hz;
1557                 else
1558                         ticks = hz / 10;
1559         } else {
1560                 rl_watchdog(sc);
1561                 ticks = hz;
1562         }
1563
1564         callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1565 }
1566
1567 #ifdef DEVICE_POLLING
1568 static int
1569 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1570 {
1571         struct rl_softc *sc = ifp->if_softc;
1572         int rx_npkts = 0;
1573
1574         RL_LOCK(sc);
1575         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1576                 rx_npkts = rl_poll_locked(ifp, cmd, count);
1577         RL_UNLOCK(sc);
1578         return (rx_npkts);
1579 }
1580
1581 static int
1582 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1583 {
1584         struct rl_softc *sc = ifp->if_softc;
1585         int rx_npkts;
1586
1587         RL_LOCK_ASSERT(sc);
1588
1589         sc->rxcycles = count;
1590         rx_npkts = rl_rxeof(sc);
1591         rl_txeof(sc);
1592
1593         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1594                 rl_start_locked(ifp);
1595
1596         if (cmd == POLL_AND_CHECK_STATUS) {
1597                 uint16_t        status;
1598
1599                 /* We should also check the status register. */
1600                 status = CSR_READ_2(sc, RL_ISR);
1601                 if (status == 0xffff)
1602                         return (rx_npkts);
1603                 if (status != 0)
1604                         CSR_WRITE_2(sc, RL_ISR, status);
1605
1606                 /* XXX We should check behaviour on receiver stalls. */
1607
1608                 if (status & RL_ISR_SYSTEM_ERR) {
1609                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1610                         rl_init_locked(sc);
1611                 }
1612         }
1613         return (rx_npkts);
1614 }
1615 #endif /* DEVICE_POLLING */
1616
1617 static void
1618 rl_intr(void *arg)
1619 {
1620         struct rl_softc         *sc = arg;
1621         struct ifnet            *ifp = sc->rl_ifp;
1622         uint16_t                status;
1623
1624         RL_LOCK(sc);
1625
1626         if (sc->suspended)
1627                 goto done_locked;
1628
1629 #ifdef DEVICE_POLLING
1630         if  (ifp->if_capenable & IFCAP_POLLING)
1631                 goto done_locked;
1632 #endif
1633
1634         for (;;) {
1635                 status = CSR_READ_2(sc, RL_ISR);
1636                 /* If the card has gone away, the read returns 0xffff. */
1637                 if (status == 0xffff)
1638                         break;
1639                 if (status != 0)
1640                         CSR_WRITE_2(sc, RL_ISR, status);
1641                 if ((status & RL_INTRS) == 0)
1642                         break;
1643                 if (status & RL_ISR_RX_OK)
1644                         rl_rxeof(sc);
1645                 if (status & RL_ISR_RX_ERR)
1646                         rl_rxeof(sc);
1647                 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1648                         rl_txeof(sc);
1649                 if (status & RL_ISR_SYSTEM_ERR) {
1650                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1651                         rl_init_locked(sc);
1652                 }
1653         }
1654
1655         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1656                 rl_start_locked(ifp);
1657
1658 done_locked:
1659         RL_UNLOCK(sc);
1660 }
1661
1662 /*
1663  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1664  * pointers to the fragment pointers.
1665  */
1666 static int
1667 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1668 {
1669         struct mbuf             *m;
1670         bus_dma_segment_t       txsegs[1];
1671         int                     error, nsegs, padlen;
1672
1673         RL_LOCK_ASSERT(sc);
1674
1675         m = *m_head;
1676         padlen = 0;
1677         /*
1678          * Hardware doesn't auto-pad, so we have to make sure
1679          * pad short frames out to the minimum frame length.
1680          */
1681         if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1682                 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1683         /*
1684          * The RealTek is brain damaged and wants longword-aligned
1685          * TX buffers, plus we can only have one fragment buffer
1686          * per packet. We have to copy pretty much all the time.
1687          */
1688         if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1689             (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1690                 m = m_defrag(*m_head, M_DONTWAIT);
1691                 if (m == NULL) {
1692                         m_freem(*m_head);
1693                         *m_head = NULL;
1694                         return (ENOMEM);
1695                 }
1696         }
1697         *m_head = m;
1698
1699         if (padlen > 0) {
1700                 /*
1701                  * Make security-conscious people happy: zero out the
1702                  * bytes in the pad area, since we don't know what
1703                  * this mbuf cluster buffer's previous user might
1704                  * have left in it.
1705                  */
1706                 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1707                 m->m_pkthdr.len += padlen;
1708                 m->m_len = m->m_pkthdr.len;
1709         }
1710
1711         error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1712             RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1713         if (error != 0)
1714                 return (error);
1715         if (nsegs == 0) {
1716                 m_freem(*m_head);
1717                 *m_head = NULL;
1718                 return (EIO);
1719         }
1720
1721         RL_CUR_TXMBUF(sc) = m;
1722         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1723             BUS_DMASYNC_PREWRITE);
1724         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1725
1726         return (0);
1727 }
1728
1729 /*
1730  * Main transmit routine.
1731  */
1732 static void
1733 rl_start(struct ifnet *ifp)
1734 {
1735         struct rl_softc         *sc = ifp->if_softc;
1736
1737         RL_LOCK(sc);
1738         rl_start_locked(ifp);
1739         RL_UNLOCK(sc);
1740 }
1741
1742 static void
1743 rl_start_locked(struct ifnet *ifp)
1744 {
1745         struct rl_softc         *sc = ifp->if_softc;
1746         struct mbuf             *m_head = NULL;
1747
1748         RL_LOCK_ASSERT(sc);
1749
1750         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1751             IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1752                 return;
1753
1754         while (RL_CUR_TXMBUF(sc) == NULL) {
1755
1756                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1757
1758                 if (m_head == NULL)
1759                         break;
1760
1761                 if (rl_encap(sc, &m_head)) {
1762                         if (m_head == NULL)
1763                                 break;
1764                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1765                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1766                         break;
1767                 }
1768
1769                 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1770                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1771
1772                 /* Transmit the frame. */
1773                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1774                     RL_TXTHRESH(sc->rl_txthresh) |
1775                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1776
1777                 RL_INC(sc->rl_cdata.cur_tx);
1778
1779                 /* Set a timeout in case the chip goes out to lunch. */
1780                 sc->rl_watchdog_timer = 5;
1781         }
1782
1783         /*
1784          * We broke out of the loop because all our TX slots are
1785          * full. Mark the NIC as busy until it drains some of the
1786          * packets from the queue.
1787          */
1788         if (RL_CUR_TXMBUF(sc) != NULL)
1789                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1790 }
1791
1792 static void
1793 rl_init(void *xsc)
1794 {
1795         struct rl_softc         *sc = xsc;
1796
1797         RL_LOCK(sc);
1798         rl_init_locked(sc);
1799         RL_UNLOCK(sc);
1800 }
1801
1802 static void
1803 rl_init_locked(struct rl_softc *sc)
1804 {
1805         struct ifnet            *ifp = sc->rl_ifp;
1806         struct mii_data         *mii;
1807         uint32_t                eaddr[2];
1808
1809         RL_LOCK_ASSERT(sc);
1810
1811         mii = device_get_softc(sc->rl_miibus);
1812
1813         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1814                 return;
1815
1816         /*
1817          * Cancel pending I/O and free all RX/TX buffers.
1818          */
1819         rl_stop(sc);
1820
1821         rl_reset(sc);
1822         if (sc->rl_twister_enable) {
1823                 /*
1824                  * Reset twister register tuning state.  The twister
1825                  * registers and their tuning are undocumented, but
1826                  * are necessary to cope with bad links.  rl_twister =
1827                  * DONE here will disable this entirely.
1828                  */
1829                 sc->rl_twister = CHK_LINK;
1830         }
1831
1832         /*
1833          * Init our MAC address.  Even though the chipset
1834          * documentation doesn't mention it, we need to enter "Config
1835          * register write enable" mode to modify the ID registers.
1836          */
1837         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1838         bzero(eaddr, sizeof(eaddr));
1839         bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1840         CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1841         CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1842         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1843
1844         /* Init the RX memory block pointer register. */
1845         CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1846             RL_RX_8139_BUF_RESERVE);
1847         /* Init TX descriptors. */
1848         rl_list_tx_init(sc);
1849         /* Init Rx memory block. */
1850         rl_list_rx_init(sc);
1851
1852         /*
1853          * Enable transmit and receive.
1854          */
1855         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1856
1857         /*
1858          * Set the initial TX and RX configuration.
1859          */
1860         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1861         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1862
1863         /* Set RX filter. */
1864         rl_rxfilter(sc);
1865
1866 #ifdef DEVICE_POLLING
1867         /* Disable interrupts if we are polling. */
1868         if (ifp->if_capenable & IFCAP_POLLING)
1869                 CSR_WRITE_2(sc, RL_IMR, 0);
1870         else
1871 #endif
1872         /* Enable interrupts. */
1873         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1874
1875         /* Set initial TX threshold */
1876         sc->rl_txthresh = RL_TX_THRESH_INIT;
1877
1878         /* Start RX/TX process. */
1879         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1880
1881         /* Enable receiver and transmitter. */
1882         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1883
1884         sc->rl_flags &= ~RL_FLAG_LINK;
1885         mii_mediachg(mii);
1886
1887         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1888
1889         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1890         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1891
1892         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1893 }
1894
1895 /*
1896  * Set media options.
1897  */
1898 static int
1899 rl_ifmedia_upd(struct ifnet *ifp)
1900 {
1901         struct rl_softc         *sc = ifp->if_softc;
1902         struct mii_data         *mii;
1903
1904         mii = device_get_softc(sc->rl_miibus);
1905
1906         RL_LOCK(sc);
1907         mii_mediachg(mii);
1908         RL_UNLOCK(sc);
1909
1910         return (0);
1911 }
1912
1913 /*
1914  * Report current media status.
1915  */
1916 static void
1917 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1918 {
1919         struct rl_softc         *sc = ifp->if_softc;
1920         struct mii_data         *mii;
1921
1922         mii = device_get_softc(sc->rl_miibus);
1923
1924         RL_LOCK(sc);
1925         mii_pollstat(mii);
1926         RL_UNLOCK(sc);
1927         ifmr->ifm_active = mii->mii_media_active;
1928         ifmr->ifm_status = mii->mii_media_status;
1929 }
1930
1931 static int
1932 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1933 {
1934         struct ifreq            *ifr = (struct ifreq *)data;
1935         struct mii_data         *mii;
1936         struct rl_softc         *sc = ifp->if_softc;
1937         int                     error = 0, mask;
1938
1939         switch (command) {
1940         case SIOCSIFFLAGS:
1941                 RL_LOCK(sc);
1942                 if (ifp->if_flags & IFF_UP) {
1943                         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1944                             ((ifp->if_flags ^ sc->rl_if_flags) &
1945                             (IFF_PROMISC | IFF_ALLMULTI)))
1946                                 rl_rxfilter(sc);
1947                         else
1948                                 rl_init_locked(sc);
1949                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1950                         rl_stop(sc);
1951                 sc->rl_if_flags = ifp->if_flags;
1952                 RL_UNLOCK(sc);
1953                 break;
1954         case SIOCADDMULTI:
1955         case SIOCDELMULTI:
1956                 RL_LOCK(sc);
1957                 rl_rxfilter(sc);
1958                 RL_UNLOCK(sc);
1959                 break;
1960         case SIOCGIFMEDIA:
1961         case SIOCSIFMEDIA:
1962                 mii = device_get_softc(sc->rl_miibus);
1963                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1964                 break;
1965         case SIOCSIFCAP:
1966                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1967 #ifdef DEVICE_POLLING
1968                 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1969                     !(ifp->if_capenable & IFCAP_POLLING)) {
1970                         error = ether_poll_register(rl_poll, ifp);
1971                         if (error)
1972                                 return(error);
1973                         RL_LOCK(sc);
1974                         /* Disable interrupts */
1975                         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1976                         ifp->if_capenable |= IFCAP_POLLING;
1977                         RL_UNLOCK(sc);
1978                         return (error);
1979
1980                 }
1981                 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1982                     ifp->if_capenable & IFCAP_POLLING) {
1983                         error = ether_poll_deregister(ifp);
1984                         /* Enable interrupts. */
1985                         RL_LOCK(sc);
1986                         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1987                         ifp->if_capenable &= ~IFCAP_POLLING;
1988                         RL_UNLOCK(sc);
1989                         return (error);
1990                 }
1991 #endif /* DEVICE_POLLING */
1992                 if ((mask & IFCAP_WOL) != 0 &&
1993                     (ifp->if_capabilities & IFCAP_WOL) != 0) {
1994                         if ((mask & IFCAP_WOL_UCAST) != 0)
1995                                 ifp->if_capenable ^= IFCAP_WOL_UCAST;
1996                         if ((mask & IFCAP_WOL_MCAST) != 0)
1997                                 ifp->if_capenable ^= IFCAP_WOL_MCAST;
1998                         if ((mask & IFCAP_WOL_MAGIC) != 0)
1999                                 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2000                 }
2001                 break;
2002         default:
2003                 error = ether_ioctl(ifp, command, data);
2004                 break;
2005         }
2006
2007         return (error);
2008 }
2009
2010 static void
2011 rl_watchdog(struct rl_softc *sc)
2012 {
2013
2014         RL_LOCK_ASSERT(sc);
2015
2016         if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
2017                 return;
2018
2019         device_printf(sc->rl_dev, "watchdog timeout\n");
2020         sc->rl_ifp->if_oerrors++;
2021
2022         rl_txeof(sc);
2023         rl_rxeof(sc);
2024         sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2025         rl_init_locked(sc);
2026 }
2027
2028 /*
2029  * Stop the adapter and free any mbufs allocated to the
2030  * RX and TX lists.
2031  */
2032 static void
2033 rl_stop(struct rl_softc *sc)
2034 {
2035         register int            i;
2036         struct ifnet            *ifp = sc->rl_ifp;
2037
2038         RL_LOCK_ASSERT(sc);
2039
2040         sc->rl_watchdog_timer = 0;
2041         callout_stop(&sc->rl_stat_callout);
2042         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2043         sc->rl_flags &= ~RL_FLAG_LINK;
2044
2045         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2046         CSR_WRITE_2(sc, RL_IMR, 0x0000);
2047         for (i = 0; i < RL_TIMEOUT; i++) {
2048                 DELAY(10);
2049                 if ((CSR_READ_1(sc, RL_COMMAND) &
2050                     (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
2051                         break;
2052         }
2053         if (i == RL_TIMEOUT)
2054                 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
2055
2056         /*
2057          * Free the TX list buffers.
2058          */
2059         for (i = 0; i < RL_TX_LIST_CNT; i++) {
2060                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2061                         if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2062                                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
2063                                     sc->rl_cdata.rl_tx_dmamap[i],
2064                                     BUS_DMASYNC_POSTWRITE);
2065                                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
2066                                     sc->rl_cdata.rl_tx_dmamap[i]);
2067                                 m_freem(sc->rl_cdata.rl_tx_chain[i]);
2068                                 sc->rl_cdata.rl_tx_chain[i] = NULL;
2069                         }
2070                         CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
2071                             0x0000000);
2072                 }
2073         }
2074 }
2075
2076 /*
2077  * Device suspend routine.  Stop the interface and save some PCI
2078  * settings in case the BIOS doesn't restore them properly on
2079  * resume.
2080  */
2081 static int
2082 rl_suspend(device_t dev)
2083 {
2084         struct rl_softc         *sc;
2085
2086         sc = device_get_softc(dev);
2087
2088         RL_LOCK(sc);
2089         rl_stop(sc);
2090         rl_setwol(sc);
2091         sc->suspended = 1;
2092         RL_UNLOCK(sc);
2093
2094         return (0);
2095 }
2096
2097 /*
2098  * Device resume routine.  Restore some PCI settings in case the BIOS
2099  * doesn't, re-enable busmastering, and restart the interface if
2100  * appropriate.
2101  */
2102 static int
2103 rl_resume(device_t dev)
2104 {
2105         struct rl_softc         *sc;
2106         struct ifnet            *ifp;
2107         int                     pmc;
2108         uint16_t                pmstat;
2109
2110         sc = device_get_softc(dev);
2111         ifp = sc->rl_ifp;
2112
2113         RL_LOCK(sc);
2114
2115         if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
2116             pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
2117                 /* Disable PME and clear PME status. */
2118                 pmstat = pci_read_config(sc->rl_dev,
2119                     pmc + PCIR_POWER_STATUS, 2);
2120                 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2121                         pmstat &= ~PCIM_PSTAT_PMEENABLE;
2122                         pci_write_config(sc->rl_dev,
2123                             pmc + PCIR_POWER_STATUS, pmstat, 2);
2124                 }
2125                 /*
2126                  * Clear WOL matching such that normal Rx filtering
2127                  * wouldn't interfere with WOL patterns.
2128                  */
2129                 rl_clrwol(sc);
2130         }
2131
2132         /* reinitialize interface if necessary */
2133         if (ifp->if_flags & IFF_UP)
2134                 rl_init_locked(sc);
2135
2136         sc->suspended = 0;
2137
2138         RL_UNLOCK(sc);
2139
2140         return (0);
2141 }
2142
2143 /*
2144  * Stop all chip I/O so that the kernel's probe routines don't
2145  * get confused by errant DMAs when rebooting.
2146  */
2147 static int
2148 rl_shutdown(device_t dev)
2149 {
2150         struct rl_softc         *sc;
2151
2152         sc = device_get_softc(dev);
2153
2154         RL_LOCK(sc);
2155         rl_stop(sc);
2156         /*
2157          * Mark interface as down since otherwise we will panic if
2158          * interrupt comes in later on, which can happen in some
2159          * cases.
2160          */
2161         sc->rl_ifp->if_flags &= ~IFF_UP;
2162         rl_setwol(sc);
2163         RL_UNLOCK(sc);
2164
2165         return (0);
2166 }
2167
2168 static void
2169 rl_setwol(struct rl_softc *sc)
2170 {
2171         struct ifnet            *ifp;
2172         int                     pmc;
2173         uint16_t                pmstat;
2174         uint8_t                 v;
2175
2176         RL_LOCK_ASSERT(sc);
2177
2178         ifp = sc->rl_ifp;
2179         if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2180                 return;
2181         if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2182                 return;
2183
2184         /* Enable config register write. */
2185         CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2186
2187         /* Enable PME. */
2188         v = CSR_READ_1(sc, RL_CFG1);
2189         v &= ~RL_CFG1_PME;
2190         if ((ifp->if_capenable & IFCAP_WOL) != 0)
2191                 v |= RL_CFG1_PME;
2192         CSR_WRITE_1(sc, RL_CFG1, v);
2193
2194         v = CSR_READ_1(sc, RL_CFG3);
2195         v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2196         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2197                 v |= RL_CFG3_WOL_MAGIC;
2198         CSR_WRITE_1(sc, RL_CFG3, v);
2199
2200         /* Config register write done. */
2201         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2202
2203         v = CSR_READ_1(sc, RL_CFG5);
2204         v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2205         v &= ~RL_CFG5_WOL_LANWAKE;
2206         if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2207                 v |= RL_CFG5_WOL_UCAST;
2208         if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2209                 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2210         if ((ifp->if_capenable & IFCAP_WOL) != 0)
2211                 v |= RL_CFG5_WOL_LANWAKE;
2212         CSR_WRITE_1(sc, RL_CFG5, v);
2213         /* Request PME if WOL is requested. */
2214         pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2215         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2216         if ((ifp->if_capenable & IFCAP_WOL) != 0)
2217                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2218         pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2219 }
2220
2221 static void
2222 rl_clrwol(struct rl_softc *sc)
2223 {
2224         struct ifnet            *ifp;
2225         uint8_t                 v;
2226
2227         ifp = sc->rl_ifp;
2228         if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2229                 return;
2230
2231         /* Enable config register write. */
2232         CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2233
2234         v = CSR_READ_1(sc, RL_CFG3);
2235         v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2236         CSR_WRITE_1(sc, RL_CFG3, v);
2237
2238         /* Config register write done. */
2239         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2240
2241         v = CSR_READ_1(sc, RL_CFG5);
2242         v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2243         v &= ~RL_CFG5_WOL_LANWAKE;
2244         CSR_WRITE_1(sc, RL_CFG5, v);
2245 }