2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * RealTek 8129/8139 register offsets
38 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40 #define RL_IDR2 0x0002
41 #define RL_IDR3 0x0003
42 #define RL_IDR4 0x0004
43 #define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45 #define RL_MAR0 0x0008 /* Multicast hash table */
46 #define RL_MAR1 0x0009
47 #define RL_MAR2 0x000A
48 #define RL_MAR3 0x000B
49 #define RL_MAR4 0x000C
50 #define RL_MAR5 0x000D
51 #define RL_MAR6 0x000E
52 #define RL_MAR7 0x000F
54 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
59 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
64 #define RL_RXADDR 0x0030 /* RX ring start address */
65 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67 #define RL_COMMAND 0x0037 /* command register */
68 #define RL_CURRXADDR 0x0038 /* current address of packet read */
69 #define RL_CURRXBUF 0x003A /* current RX buffer address */
70 #define RL_IMR 0x003C /* interrupt mask register */
71 #define RL_ISR 0x003E /* interrupt status register */
72 #define RL_TXCFG 0x0040 /* transmit config */
73 #define RL_RXCFG 0x0044 /* receive config */
74 #define RL_TIMERCNT 0x0048 /* timer count register */
75 #define RL_MISSEDPKT 0x004C /* missed packet counter */
76 #define RL_EECMD 0x0050 /* EEPROM command register */
77 #define RL_CFG0 0x0051 /* config register #0 */
78 #define RL_CFG1 0x0052 /* config register #1 */
79 #define RL_CFG2 0x0053 /* config register #2 */
80 #define RL_CFG3 0x0054 /* config register #3 */
81 #define RL_CFG4 0x0055 /* config register #4 */
82 #define RL_CFG5 0x0056 /* config register #5 */
84 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */
85 /* 0059-005A reserved */
86 #define RL_MII 0x005A /* 8129 chip only */
87 #define RL_HALTCLK 0x005B
88 #define RL_MULTIINTR 0x005C /* multiple interrupt */
89 #define RL_PCIREV 0x005E /* PCI revision value */
91 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
93 /* Direct PHY access registers only available on 8139 */
94 #define RL_BMCR 0x0062 /* PHY basic mode control */
95 #define RL_BMSR 0x0064 /* PHY basic mode status */
96 #define RL_ANAR 0x0066 /* PHY autoneg advert */
97 #define RL_LPAR 0x0068 /* PHY link partner ability */
98 #define RL_ANER 0x006A /* PHY autoneg expansion */
100 #define RL_DISCCNT 0x006C /* disconnect counter */
101 #define RL_FALSECAR 0x006E /* false carrier counter */
102 #define RL_NWAYTST 0x0070 /* NWAY test register */
103 #define RL_RX_ER 0x0072 /* RX_ER counter */
104 #define RL_CSCFG 0x0074 /* CS configuration register */
107 * When operating in special C+ mode, some of the registers in an
108 * 8139C+ chip have different definitions. These are also used for
109 * the 8169 gigE chip.
111 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
112 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
113 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
114 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
115 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
116 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
117 #define RL_CFG2 0x0053
118 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */
119 #define RL_TXSTART 0x00D9 /* 8 bits */
120 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */
121 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
122 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
123 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
126 * Registers specific to the 8169 gigE chip
128 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
129 #define RL_PHYAR 0x0060
130 #define RL_TBICSR 0x0064
131 #define RL_TBI_ANAR 0x0068
132 #define RL_TBI_LPAR 0x006A
133 #define RL_GMEDIASTAT 0x006C /* 8 bits */
134 #define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
135 #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
136 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
137 #define RL_GTXSTART 0x0038 /* 8 bits */
140 * TX config register bits
142 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
143 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
144 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
145 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
146 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
147 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */
148 #define RL_TXCFG_HWREV 0x7CC00000
150 #define RL_LOOPTEST_OFF 0x00000000
151 #define RL_LOOPTEST_ON 0x00020000
152 #define RL_LOOPTEST_ON_CPLUS 0x00060000
154 /* Known revision codes. */
156 #define RL_HWREV_8169 0x00000000
157 #define RL_HWREV_8169S 0x00800000
158 #define RL_HWREV_8110S 0x04000000
159 #define RL_HWREV_8169_8110SB 0x10000000
160 #define RL_HWREV_8169_8110SC 0x18000000
161 #define RL_HWREV_8102EL 0x24800000
162 #define RL_HWREV_8102EL_SPIN1 0x24c00000
163 #define RL_HWREV_8168D 0x28000000
164 #define RL_HWREV_8168DP 0x28800000
165 #define RL_HWREV_8168_SPIN1 0x30000000
166 #define RL_HWREV_8100E 0x30800000
167 #define RL_HWREV_8101E 0x34000000
168 #define RL_HWREV_8102E 0x34800000
169 #define RL_HWREV_8103E 0x34C00000
170 #define RL_HWREV_8168_SPIN2 0x38000000
171 #define RL_HWREV_8168_SPIN3 0x38400000
172 #define RL_HWREV_8168C 0x3C000000
173 #define RL_HWREV_8168C_SPIN2 0x3C400000
174 #define RL_HWREV_8168CP 0x3C800000
175 #define RL_HWREV_8139 0x60000000
176 #define RL_HWREV_8139A 0x70000000
177 #define RL_HWREV_8139AG 0x70800000
178 #define RL_HWREV_8139B 0x78000000
179 #define RL_HWREV_8130 0x7C000000
180 #define RL_HWREV_8139C 0x74000000
181 #define RL_HWREV_8139D 0x74400000
182 #define RL_HWREV_8139CPLUS 0x74800000
183 #define RL_HWREV_8101 0x74c00000
184 #define RL_HWREV_8100 0x78800000
185 #define RL_HWREV_8169_8110SBL 0x7CC00000
186 #define RL_HWREV_8169_8110SCE 0x98000000
188 #define RL_TXDMA_16BYTES 0x00000000
189 #define RL_TXDMA_32BYTES 0x00000100
190 #define RL_TXDMA_64BYTES 0x00000200
191 #define RL_TXDMA_128BYTES 0x00000300
192 #define RL_TXDMA_256BYTES 0x00000400
193 #define RL_TXDMA_512BYTES 0x00000500
194 #define RL_TXDMA_1024BYTES 0x00000600
195 #define RL_TXDMA_2048BYTES 0x00000700
198 * Transmit descriptor status register bits.
200 #define RL_TXSTAT_LENMASK 0x00001FFF
201 #define RL_TXSTAT_OWN 0x00002000
202 #define RL_TXSTAT_TX_UNDERRUN 0x00004000
203 #define RL_TXSTAT_TX_OK 0x00008000
204 #define RL_TXSTAT_EARLY_THRESH 0x003F0000
205 #define RL_TXSTAT_COLLCNT 0x0F000000
206 #define RL_TXSTAT_CARR_HBEAT 0x10000000
207 #define RL_TXSTAT_OUTOFWIN 0x20000000
208 #define RL_TXSTAT_TXABRT 0x40000000
209 #define RL_TXSTAT_CARRLOSS 0x80000000
212 * Interrupt status register bits.
214 #define RL_ISR_RX_OK 0x0001
215 #define RL_ISR_RX_ERR 0x0002
216 #define RL_ISR_TX_OK 0x0004
217 #define RL_ISR_TX_ERR 0x0008
218 #define RL_ISR_RX_OVERRUN 0x0010
219 #define RL_ISR_PKT_UNDERRUN 0x0020
220 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */
221 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
222 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
223 #define RL_ISR_SWI 0x0100 /* C+ only */
224 #define RL_ISR_CABLE_LEN_CHGD 0x2000
225 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
226 #define RL_ISR_TIMEOUT_EXPIRED 0x4000
227 #define RL_ISR_SYSTEM_ERR 0x8000
230 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
231 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
232 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
234 #ifdef RE_TX_MODERATION
235 #define RL_INTRS_CPLUS \
236 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
237 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
238 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
240 #define RL_INTRS_CPLUS \
241 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
242 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
243 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
247 * Media status register. (8139 only)
249 #define RL_MEDIASTAT_RXPAUSE 0x01
250 #define RL_MEDIASTAT_TXPAUSE 0x02
251 #define RL_MEDIASTAT_LINK 0x04
252 #define RL_MEDIASTAT_SPEED10 0x08
253 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
254 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
257 * Receive config register.
259 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
260 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
261 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
262 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
263 #define RL_RXCFG_RX_RUNT 0x00000010
264 #define RL_RXCFG_RX_ERRPKT 0x00000020
265 #define RL_RXCFG_WRAP 0x00000080
266 #define RL_RXCFG_MAXDMA 0x00000700
267 #define RL_RXCFG_BUFSZ 0x00001800
268 #define RL_RXCFG_FIFOTHRESH 0x0000E000
269 #define RL_RXCFG_EARLYTHRESH 0x07000000
271 #define RL_RXDMA_16BYTES 0x00000000
272 #define RL_RXDMA_32BYTES 0x00000100
273 #define RL_RXDMA_64BYTES 0x00000200
274 #define RL_RXDMA_128BYTES 0x00000300
275 #define RL_RXDMA_256BYTES 0x00000400
276 #define RL_RXDMA_512BYTES 0x00000500
277 #define RL_RXDMA_1024BYTES 0x00000600
278 #define RL_RXDMA_UNLIMITED 0x00000700
280 #define RL_RXBUF_8 0x00000000
281 #define RL_RXBUF_16 0x00000800
282 #define RL_RXBUF_32 0x00001000
283 #define RL_RXBUF_64 0x00001800
285 #define RL_RXFIFO_16BYTES 0x00000000
286 #define RL_RXFIFO_32BYTES 0x00002000
287 #define RL_RXFIFO_64BYTES 0x00004000
288 #define RL_RXFIFO_128BYTES 0x00006000
289 #define RL_RXFIFO_256BYTES 0x00008000
290 #define RL_RXFIFO_512BYTES 0x0000A000
291 #define RL_RXFIFO_1024BYTES 0x0000C000
292 #define RL_RXFIFO_NOTHRESH 0x0000E000
295 * Bits in RX status header (included with RX'ed packet
298 #define RL_RXSTAT_RXOK 0x00000001
299 #define RL_RXSTAT_ALIGNERR 0x00000002
300 #define RL_RXSTAT_CRCERR 0x00000004
301 #define RL_RXSTAT_GIANT 0x00000008
302 #define RL_RXSTAT_RUNT 0x00000010
303 #define RL_RXSTAT_BADSYM 0x00000020
304 #define RL_RXSTAT_BROAD 0x00002000
305 #define RL_RXSTAT_INDIV 0x00004000
306 #define RL_RXSTAT_MULTI 0x00008000
307 #define RL_RXSTAT_LENMASK 0xFFFF0000
309 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
313 #define RL_CMD_EMPTY_RXBUF 0x0001
314 #define RL_CMD_TX_ENB 0x0004
315 #define RL_CMD_RX_ENB 0x0008
316 #define RL_CMD_RESET 0x0010
317 #define RL_CMD_STOPREQ 0x0080
320 * Twister register values. These are completely undocumented and derived
321 * from public sources.
323 #define RL_CSCFG_LINK_OK 0x0400
324 #define RL_CSCFG_CHANGE 0x0800
325 #define RL_CSCFG_STATUS 0xf000
326 #define RL_CSCFG_ROW3 0x7000
327 #define RL_CSCFG_ROW2 0x3000
328 #define RL_CSCFG_ROW1 0x1000
329 #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
330 #define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
332 #define RL_NWAYTST_RESET 0
333 #define RL_NWAYTST_CBL_TEST 0x20
335 #define RL_PARA78 0x78
336 #define RL_PARA78_DEF 0x78fa8388
337 #define RL_PARA7C 0x7C
338 #define RL_PARA7C_DEF 0xcb38de43
339 #define RL_PARA7C_RETUNE 0xfb38de03
341 * EEPROM control register
343 #define RL_EE_DATAOUT 0x01 /* Data out */
344 #define RL_EE_DATAIN 0x02 /* Data in */
345 #define RL_EE_CLK 0x04 /* clock */
346 #define RL_EE_SEL 0x08 /* chip select */
347 #define RL_EE_MODE (0x40|0x80)
349 #define RL_EEMODE_OFF 0x00
350 #define RL_EEMODE_AUTOLOAD 0x40
351 #define RL_EEMODE_PROGRAM 0x80
352 #define RL_EEMODE_WRITECFG (0x80|0x40)
354 /* 9346 EEPROM commands */
355 #define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
356 #define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
358 #define RL_9346_WRITE 0x5
359 #define RL_9346_READ 0x6
360 #define RL_9346_ERASE 0x7
361 #define RL_9346_EWEN 0x4
362 #define RL_9346_EWEN_ADDR 0x30
363 #define RL_9456_EWDS 0x4
364 #define RL_9346_EWDS_ADDR 0x00
366 #define RL_EECMD_WRITE 0x140
367 #define RL_EECMD_READ_6BIT 0x180
368 #define RL_EECMD_READ_8BIT 0x600
369 #define RL_EECMD_ERASE 0x1c0
371 #define RL_EE_ID 0x00
372 #define RL_EE_PCI_VID 0x01
373 #define RL_EE_PCI_DID 0x02
374 /* Location of station address inside EEPROM */
375 #define RL_EE_EADDR 0x07
378 * MII register (8129 only)
380 #define RL_MII_CLK 0x01
381 #define RL_MII_DATAIN 0x02
382 #define RL_MII_DATAOUT 0x04
383 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
388 #define RL_CFG0_ROM0 0x01
389 #define RL_CFG0_ROM1 0x02
390 #define RL_CFG0_ROM2 0x04
391 #define RL_CFG0_PL0 0x08
392 #define RL_CFG0_PL1 0x10
393 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
394 #define RL_CFG0_PCS 0x40
395 #define RL_CFG0_SCR 0x80
400 #define RL_CFG1_PWRDWN 0x01
401 #define RL_CFG1_PME 0x01
402 #define RL_CFG1_SLEEP 0x02
403 #define RL_CFG1_VPDEN 0x02
404 #define RL_CFG1_IOMAP 0x04
405 #define RL_CFG1_MEMMAP 0x08
406 #define RL_CFG1_RSVD 0x10
407 #define RL_CFG1_LWACT 0x10
408 #define RL_CFG1_DRVLOAD 0x20
409 #define RL_CFG1_LED0 0x40
410 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
411 #define RL_CFG1_LED1 0x80
416 #define RL_CFG2_PCI33MHZ 0x00
417 #define RL_CFG2_PCI66MHZ 0x01
418 #define RL_CFG2_PCI64BIT 0x08
419 #define RL_CFG2_AUXPWR 0x10
420 #define RL_CFG2_MSI 0x20
425 #define RL_CFG3_GRANTSEL 0x80
426 #define RL_CFG3_WOL_MAGIC 0x20
427 #define RL_CFG3_WOL_LINK 0x10
428 #define RL_CFG3_FAST_B2B 0x01
433 #define RL_CFG4_LWPTN 0x04
434 #define RL_CFG4_LWPME 0x10
439 #define RL_CFG5_WOL_BCAST 0x40
440 #define RL_CFG5_WOL_MCAST 0x20
441 #define RL_CFG5_WOL_UCAST 0x10
442 #define RL_CFG5_WOL_LANWAKE 0x02
443 #define RL_CFG5_PME_STS 0x01
446 * 8139C+ register definitions
449 /* RL_DUMPSTATS_LO register */
451 #define RL_DUMPSTATS_START 0x00000008
453 /* Transmit start register */
455 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
456 #define RL_TXSTART_START 0x40 /* start normal queue transmit */
457 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
460 * Config 2 register, 8139C+/8169/8169S/8110S only
462 #define RL_CFG2_BUSFREQ 0x07
463 #define RL_CFG2_BUSWIDTH 0x08
464 #define RL_CFG2_AUXPWRSTS 0x10
466 #define RL_BUSFREQ_33MHZ 0x00
467 #define RL_BUSFREQ_66MHZ 0x01
469 #define RL_BUSWIDTH_32BITS 0x00
470 #define RL_BUSWIDTH_64BITS 0x08
472 /* C+ mode command register */
474 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
475 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
476 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
477 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
478 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
479 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
480 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
481 #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
482 #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
483 #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
484 #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
485 #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
486 #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
487 #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
488 #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
490 /* C+ early transmit threshold */
492 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
495 * Gigabit PHY access register (8169 only)
498 #define RL_PHYAR_PHYDATA 0x0000FFFF
499 #define RL_PHYAR_PHYREG 0x001F0000
500 #define RL_PHYAR_BUSY 0x80000000
503 * Gigabit media status (8169 only)
505 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
506 #define RL_GMEDIASTAT_LINK 0x02 /* link up */
507 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
508 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
509 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
510 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
511 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
512 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
515 * The RealTek doesn't use a fragment-based descriptor mechanism.
516 * Instead, there are only four register sets, each or which represents
517 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
518 * packet buffer (32-bit aligned!) and we place the buffer addresses in
519 * the registers so the chip knows where they are.
521 * We can sort of kludge together the same kind of buffer management
522 * used in previous drivers, but we have to do buffer copies almost all
523 * the time, so it doesn't really buy us much.
525 * For reception, there's just one large buffer where the chip stores
526 * all received packets.
529 #define RL_RX_BUF_SZ RL_RXBUF_64
530 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
531 #define RL_TX_LIST_CNT 4
532 #define RL_MIN_FRAMELEN 60
533 #define RL_TX_8139_BUF_ALIGN 4
534 #define RL_RX_8139_BUF_ALIGN 8
535 #define RL_RX_8139_BUF_RESERVE sizeof(int64_t)
536 #define RL_RX_8139_BUF_GUARD_SZ \
537 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
538 #define RL_TXTHRESH(x) ((x) << 11)
539 #define RL_TX_THRESH_INIT 96
540 #define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
541 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
542 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES
544 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
545 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
547 #define RL_ETHER_ALIGN 2
550 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
552 #define RL_IP4CSUMTX_MINLEN 28
553 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
555 struct rl_chain_data {
558 uint8_t *rl_rx_buf_ptr;
560 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
561 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
562 bus_dma_tag_t rl_tx_tag;
563 bus_dma_tag_t rl_rx_tag;
564 bus_dmamap_t rl_rx_dmamap;
565 bus_addr_t rl_rx_buf_paddr;
570 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
571 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
572 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
573 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
574 #define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
575 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
576 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
577 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
578 #define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
593 struct rl_mii_frame {
598 uint8_t mii_turnaround;
605 #define RL_MII_STARTDELIM 0x01
606 #define RL_MII_READOP 0x02
607 #define RL_MII_WRITEOP 0x01
608 #define RL_MII_TURNAROUND 0x02
612 #define RL_8139CPLUS 3
615 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
616 (x)->rl_type == RL_8169)
619 * The 8139C+ and 8160 gigE chips support descriptor-based TX
620 * and RX. In fact, they even support TCP large send. Descriptors
621 * must be allocated in contiguous blocks that are aligned on a
622 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
626 * RX/TX descriptor definition. When large send mode is enabled, the
627 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
628 * the checksum offload bits are disabled. The structure layout is
629 * the same for RX and TX descriptors
635 uint32_t rl_bufaddr_lo;
636 uint32_t rl_bufaddr_hi;
639 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
640 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
641 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
642 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
643 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
644 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
645 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
646 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
647 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
648 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
649 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
651 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
652 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
653 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
654 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000
655 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000
656 #define RL_TDESC_CMD_IPCSUMV2 0x20000000
659 * Error bits are valid only on the last descriptor of a frame
660 * (i.e. RL_TDESC_CMD_EOF == 1)
663 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
664 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
665 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
666 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
667 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
668 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
669 #define RL_TDESC_STAT_OWN 0x80000000
672 * RX descriptor cmd/vlan definitions
675 #define RL_RDESC_CMD_EOR 0x40000000
676 #define RL_RDESC_CMD_OWN 0x80000000
677 #define RL_RDESC_CMD_BUFLEN 0x00001FFF
679 #define RL_RDESC_STAT_OWN 0x80000000
680 #define RL_RDESC_STAT_EOR 0x40000000
681 #define RL_RDESC_STAT_SOF 0x20000000
682 #define RL_RDESC_STAT_EOF 0x10000000
683 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
684 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
685 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
686 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
687 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
688 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
689 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
690 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
691 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
692 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
693 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
694 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
695 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
696 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
697 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
698 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
699 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
700 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
701 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
702 RL_RDESC_STAT_CRCERR)
704 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
705 (rl_vlandata valid)*/
706 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
707 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
708 #define RL_RDESC_IPV6 0x80000000
709 #define RL_RDESC_IPV4 0x40000000
711 #define RL_PROTOID_NONIP 0x00000000
712 #define RL_PROTOID_TCPIP 0x00010000
713 #define RL_PROTOID_UDPIP 0x00020000
714 #define RL_PROTOID_IP 0x00030000
715 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
717 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
721 * Statistics counter structure (8139C+ and 8169 only)
724 uint32_t rl_tx_pkts_lo;
725 uint32_t rl_tx_pkts_hi;
726 uint32_t rl_tx_errs_lo;
727 uint32_t rl_tx_errs_hi;
729 uint16_t rl_missed_pkts;
730 uint16_t rl_rx_framealign_errs;
731 uint32_t rl_tx_onecoll;
732 uint32_t rl_tx_multicolls;
733 uint32_t rl_rx_ucasts_hi;
734 uint32_t rl_rx_ucasts_lo;
735 uint32_t rl_rx_bcasts_lo;
736 uint32_t rl_rx_bcasts_hi;
737 uint32_t rl_rx_mcasts;
738 uint16_t rl_tx_aborts;
739 uint16_t rl_rx_underruns;
743 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
746 * Number of descriptors supported : up to 64
747 * Descriptor alignment : 256 bytes
748 * Tx buffer : At least 4 bytes in length.
749 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
752 * Number of descriptors supported : up to 1024
753 * Descriptor alignment : 256 bytes
754 * Tx buffer : At least 4 bytes in length.
755 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
757 #ifndef __NO_STRICT_ALIGNMENT
758 #define RE_FIXUP_RX 1
761 #define RL_8169_TX_DESC_CNT 256
762 #define RL_8169_RX_DESC_CNT 256
763 #define RL_8139_TX_DESC_CNT 64
764 #define RL_8139_RX_DESC_CNT 64
765 #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
766 #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
767 #define RL_NTXSEGS 32
769 #define RL_RING_ALIGN 256
770 #define RL_IFQ_MAXLEN 512
771 #define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
772 #define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
773 #define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
774 #define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
775 #define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
776 #define RL_PKTSZ(x) ((x)/* >> 3*/)
778 #define RE_ETHER_ALIGN sizeof(uint64_t)
779 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
781 #define RE_ETHER_ALIGN 0
782 #define RE_RX_DESC_BUFLEN MCLBYTES
785 #define RL_MSI_MESSAGES 1
787 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
788 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
791 * The number of bits reserved for MSS in RealTek controllers is
792 * 11bits. This limits the maximum interface MTU size in TSO case
793 * as upper stack should not generate TCP segments with MSS greater
796 #define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
798 /* see comment in dev/re/if_re.c */
799 #define RL_JUMBO_FRAMELEN 7440
800 #define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
801 #define RL_MAX_FRAMELEN \
802 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
806 bus_dmamap_t tx_dmamap;
811 bus_dmamap_t rx_dmamap;
815 struct rl_list_data {
816 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
817 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
824 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
825 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
826 bus_dmamap_t rl_rx_sparemap;
827 bus_dma_tag_t rl_stag; /* stats mapping tag */
828 bus_dmamap_t rl_smap; /* stats map */
829 struct rl_stats *rl_stats;
830 bus_addr_t rl_stats_addr;
831 bus_dma_tag_t rl_rx_list_tag;
832 bus_dmamap_t rl_rx_list_map;
833 struct rl_desc *rl_rx_list;
834 bus_addr_t rl_rx_list_addr;
835 bus_dma_tag_t rl_tx_list_tag;
836 bus_dmamap_t rl_tx_list_map;
837 struct rl_desc *rl_tx_list;
838 bus_addr_t rl_tx_list_addr;
841 enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
844 struct ifnet *rl_ifp; /* interface info */
845 bus_space_handle_t rl_bhandle; /* bus space handle */
846 bus_space_tag_t rl_btag; /* bus space tag */
848 struct resource *rl_res;
851 struct resource *rl_irq[RL_MSI_MESSAGES];
852 void *rl_intrhand[RL_MSI_MESSAGES];
854 bus_dma_tag_t rl_parent_tag;
858 uint8_t rl_stats_no_timeout;
860 struct rl_chain_data rl_cdata;
861 struct rl_list_data rl_ldata;
862 struct callout rl_stat_callout;
863 int rl_watchdog_timer;
865 struct mbuf *rl_head;
866 struct mbuf *rl_tail;
868 uint32_t rl_rxlenmask;
871 int rl_twister_enable;
872 enum rl_twist rl_twister;
875 int suspended; /* 0 = normal 1 = suspended */
876 #ifdef DEVICE_POLLING
880 struct task rl_txtask;
881 struct task rl_inttask;
885 #define RL_FLAG_MSI 0x0001
886 #define RL_FLAG_AUTOPAD 0x0002
887 #define RL_FLAG_PHYWAKE 0x0008
888 #define RL_FLAG_NOJUMBO 0x0010
889 #define RL_FLAG_PAR 0x0020
890 #define RL_FLAG_DESCV2 0x0040
891 #define RL_FLAG_MACSTAT 0x0080
892 #define RL_FLAG_FASTETHER 0x0100
893 #define RL_FLAG_CMDSTOP 0x0200
894 #define RL_FLAG_MACRESET 0x0400
895 #define RL_FLAG_WOLRXENB 0x1000
896 #define RL_FLAG_MACSLEEP 0x2000
897 #define RL_FLAG_PCIE 0x4000
898 #define RL_FLAG_LINK 0x8000
901 #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
902 #define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
903 #define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
906 * register space access macros
908 #define CSR_WRITE_STREAM_4(sc, reg, val) \
909 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
910 #define CSR_WRITE_4(sc, reg, val) \
911 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
912 #define CSR_WRITE_2(sc, reg, val) \
913 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
914 #define CSR_WRITE_1(sc, reg, val) \
915 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
917 #define CSR_READ_4(sc, reg) \
918 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
919 #define CSR_READ_2(sc, reg) \
920 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
921 #define CSR_READ_1(sc, reg) \
922 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
924 #define CSR_SETBIT_1(sc, offset, val) \
925 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
927 #define CSR_CLRBIT_1(sc, offset, val) \
928 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
930 #define CSR_SETBIT_2(sc, offset, val) \
931 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
933 #define CSR_CLRBIT_2(sc, offset, val) \
934 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
936 #define CSR_SETBIT_4(sc, offset, val) \
937 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
939 #define CSR_CLRBIT_4(sc, offset, val) \
940 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
942 #define RL_TIMEOUT 1000
943 #define RL_PHY_TIMEOUT 2000
946 * General constants that are fun to know.
948 * RealTek PCI vendor ID
950 #define RT_VENDORID 0x10EC
953 * RealTek chip device IDs.
955 #define RT_DEVICEID_8139D 0x8039
956 #define RT_DEVICEID_8129 0x8129
957 #define RT_DEVICEID_8101E 0x8136
958 #define RT_DEVICEID_8138 0x8138
959 #define RT_DEVICEID_8139 0x8139
960 #define RT_DEVICEID_8169SC 0x8167
961 #define RT_DEVICEID_8168 0x8168
962 #define RT_DEVICEID_8169 0x8169
963 #define RT_DEVICEID_8100 0x8100
965 #define RT_REVID_8139CPLUS 0x20
968 * Accton PCI vendor ID
970 #define ACCTON_VENDORID 0x1113
973 * Accton MPX 5030/5038 device ID.
975 #define ACCTON_DEVICEID_5030 0x1211
978 * Nortel PCI vendor ID
980 #define NORTEL_VENDORID 0x126C
983 * Delta Electronics Vendor ID.
985 #define DELTA_VENDORID 0x1500
990 #define DELTA_DEVICEID_8139 0x1360
995 #define ADDTRON_VENDORID 0x4033
998 * Addtron device IDs.
1000 #define ADDTRON_DEVICEID_8139 0x1360
1005 #define DLINK_VENDORID 0x1186
1008 * D-Link DFE-530TX+ device ID
1010 #define DLINK_DEVICEID_530TXPLUS 0x1300
1013 * D-Link DFE-5280T device ID
1015 #define DLINK_DEVICEID_528T 0x4300
1018 * D-Link DFE-690TXD device ID
1020 #define DLINK_DEVICEID_690TXD 0x1340
1023 * Corega K.K vendor ID
1025 #define COREGA_VENDORID 0x1259
1028 * Corega FEther CB-TXD device ID
1030 #define COREGA_DEVICEID_FETHERCBTXD 0xa117
1033 * Corega FEtherII CB-TXD device ID
1035 #define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
1038 * Corega CG-LAPCIGT device ID
1040 #define COREGA_DEVICEID_CGLAPCIGT 0xc107
1045 #define LINKSYS_VENDORID 0x1737
1048 * Linksys EG1032 device ID
1050 #define LINKSYS_DEVICEID_EG1032 0x1032
1053 * Linksys EG1032 rev 3 sub-device ID
1055 #define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024
1058 * Peppercon vendor ID
1060 #define PEPPERCON_VENDORID 0x1743
1063 * Peppercon ROL-F device ID
1065 #define PEPPERCON_DEVICEID_ROLF 0x8139
1068 * Planex Communications, Inc. vendor ID
1070 #define PLANEX_VENDORID 0x14ea
1073 * Planex FNW-3603-TX device ID
1075 #define PLANEX_DEVICEID_FNW3603TX 0xab06
1078 * Planex FNW-3800-TX device ID
1080 #define PLANEX_DEVICEID_FNW3800TX 0xab07
1083 * LevelOne vendor ID
1085 #define LEVEL1_VENDORID 0x018A
1088 * LevelOne FPC-0106TX devide ID
1090 #define LEVEL1_DEVICEID_FPC0106TX 0x0106
1095 #define CP_VENDORID 0x021B
1100 #define EDIMAX_VENDORID 0x13D1
1103 * Edimax EP-4103DL cardbus device ID
1105 #define EDIMAX_DEVICEID_EP4103DL 0xAB06
1107 /* US Robotics vendor ID */
1109 #define USR_VENDORID 0x16EC
1111 /* US Robotics 997902 device ID */
1113 #define USR_DEVICEID_997902 0x0116
1116 * PCI low memory base and low I/O base register, and
1117 * other PCI registers.
1120 #define RL_PCI_VENDOR_ID 0x00
1121 #define RL_PCI_DEVICE_ID 0x02
1122 #define RL_PCI_COMMAND 0x04
1123 #define RL_PCI_STATUS 0x06
1124 #define RL_PCI_CLASSCODE 0x09
1125 #define RL_PCI_LATENCY_TIMER 0x0D
1126 #define RL_PCI_HEADER_TYPE 0x0E
1127 #define RL_PCI_LOIO 0x10
1128 #define RL_PCI_LOMEM 0x14
1129 #define RL_PCI_BIOSROM 0x30
1130 #define RL_PCI_INTLINE 0x3C
1131 #define RL_PCI_INTPIN 0x3D
1132 #define RL_PCI_MINGNT 0x3E
1133 #define RL_PCI_MINLAT 0x0F
1134 #define RL_PCI_RESETOPT 0x48
1135 #define RL_PCI_EEPROM_DATA 0x4C
1137 #define RL_PCI_CAPID 0x50 /* 8 bits */
1138 #define RL_PCI_NEXTPTR 0x51 /* 8 bits */
1139 #define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */
1140 #define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
1142 #define RL_PSTATE_MASK 0x0003
1143 #define RL_PSTATE_D0 0x0000
1144 #define RL_PSTATE_D1 0x0002
1145 #define RL_PSTATE_D2 0x0002
1146 #define RL_PSTATE_D3 0x0003
1147 #define RL_PME_EN 0x0010
1148 #define RL_PME_STATUS 0x8000