2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
36 * RealTek 8129/8139 register offsets
38 #define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39 #define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40 #define RL_IDR2 0x0002
41 #define RL_IDR3 0x0003
42 #define RL_IDR4 0x0004
43 #define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45 #define RL_MAR0 0x0008 /* Multicast hash table */
46 #define RL_MAR1 0x0009
47 #define RL_MAR2 0x000A
48 #define RL_MAR3 0x000B
49 #define RL_MAR4 0x000C
50 #define RL_MAR5 0x000D
51 #define RL_MAR6 0x000E
52 #define RL_MAR7 0x000F
54 #define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55 #define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56 #define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57 #define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
59 #define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60 #define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61 #define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62 #define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
64 #define RL_RXADDR 0x0030 /* RX ring start address */
65 #define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66 #define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67 #define RL_COMMAND 0x0037 /* command register */
68 #define RL_CURRXADDR 0x0038 /* current address of packet read */
69 #define RL_CURRXBUF 0x003A /* current RX buffer address */
70 #define RL_IMR 0x003C /* interrupt mask register */
71 #define RL_ISR 0x003E /* interrupt status register */
72 #define RL_TXCFG 0x0040 /* transmit config */
73 #define RL_RXCFG 0x0044 /* receive config */
74 #define RL_TIMERCNT 0x0048 /* timer count register */
75 #define RL_MISSEDPKT 0x004C /* missed packet counter */
76 #define RL_EECMD 0x0050 /* EEPROM command register */
77 #define RL_CFG0 0x0051 /* config register #0 */
78 #define RL_CFG1 0x0052 /* config register #1 */
79 #define RL_CFG2 0x0053 /* config register #2 */
80 #define RL_CFG3 0x0054 /* config register #3 */
81 #define RL_CFG4 0x0055 /* config register #4 */
82 #define RL_CFG5 0x0056 /* config register #5 */
84 #define RL_MEDIASTAT 0x0058 /* media status register (8139) */
85 /* 0059-005A reserved */
86 #define RL_MII 0x005A /* 8129 chip only */
87 #define RL_HALTCLK 0x005B
88 #define RL_MULTIINTR 0x005C /* multiple interrupt */
89 #define RL_PCIREV 0x005E /* PCI revision value */
91 #define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
93 /* Direct PHY access registers only available on 8139 */
94 #define RL_BMCR 0x0062 /* PHY basic mode control */
95 #define RL_BMSR 0x0064 /* PHY basic mode status */
96 #define RL_ANAR 0x0066 /* PHY autoneg advert */
97 #define RL_LPAR 0x0068 /* PHY link partner ability */
98 #define RL_ANER 0x006A /* PHY autoneg expansion */
100 #define RL_DISCCNT 0x006C /* disconnect counter */
101 #define RL_FALSECAR 0x006E /* false carrier counter */
102 #define RL_NWAYTST 0x0070 /* NWAY test register */
103 #define RL_RX_ER 0x0072 /* RX_ER counter */
104 #define RL_CSCFG 0x0074 /* CS configuration register */
107 * When operating in special C+ mode, some of the registers in an
108 * 8139C+ chip have different definitions. These are also used for
109 * the 8169 gigE chip.
111 #define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
112 #define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
113 #define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
114 #define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
115 #define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
116 #define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
117 #define RL_CFG2 0x0053
118 #define RL_TIMERINT 0x0054 /* interrupt on timer expire */
119 #define RL_TXSTART 0x00D9 /* 8 bits */
120 #define RL_CPLUS_CMD 0x00E0 /* 16 bits */
121 #define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
122 #define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
123 #define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
126 * Registers specific to the 8169 gigE chip
128 #define RL_GTXSTART 0x0038 /* 8 bits */
129 #define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
130 #define RL_PHYAR 0x0060
131 #define RL_TBICSR 0x0064
132 #define RL_TBI_ANAR 0x0068
133 #define RL_TBI_LPAR 0x006A
134 #define RL_GMEDIASTAT 0x006C /* 8 bits */
135 #define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */
136 #define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */
137 #define RL_PMCH 0x006F /* 8 bits */
138 #define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
139 #define RL_INTRMOD 0x00E2 /* 16 bits */
142 * TX config register bits
144 #define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
145 #define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
146 #define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
147 #define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
148 #define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
149 #define RL_TXCFG_IFG 0x03000000 /* interframe gap */
150 #define RL_TXCFG_HWREV 0x7CC00000
152 #define RL_LOOPTEST_OFF 0x00000000
153 #define RL_LOOPTEST_ON 0x00020000
154 #define RL_LOOPTEST_ON_CPLUS 0x00060000
156 /* Known revision codes. */
158 #define RL_HWREV_8169 0x00000000
159 #define RL_HWREV_8169S 0x00800000
160 #define RL_HWREV_8110S 0x04000000
161 #define RL_HWREV_8169_8110SB 0x10000000
162 #define RL_HWREV_8169_8110SC 0x18000000
163 #define RL_HWREV_8102EL 0x24800000
164 #define RL_HWREV_8102EL_SPIN1 0x24C00000
165 #define RL_HWREV_8168D 0x28000000
166 #define RL_HWREV_8168DP 0x28800000
167 #define RL_HWREV_8168E 0x2C000000
168 #define RL_HWREV_8168E_VL 0x2C800000
169 #define RL_HWREV_8168_SPIN1 0x30000000
170 #define RL_HWREV_8100E 0x30800000
171 #define RL_HWREV_8101E 0x34000000
172 #define RL_HWREV_8102E 0x34800000
173 #define RL_HWREV_8103E 0x34C00000
174 #define RL_HWREV_8168_SPIN2 0x38000000
175 #define RL_HWREV_8168_SPIN3 0x38400000
176 #define RL_HWREV_8168C 0x3C000000
177 #define RL_HWREV_8168C_SPIN2 0x3C400000
178 #define RL_HWREV_8168CP 0x3C800000
179 #define RL_HWREV_8139 0x60000000
180 #define RL_HWREV_8139A 0x70000000
181 #define RL_HWREV_8139AG 0x70800000
182 #define RL_HWREV_8139B 0x78000000
183 #define RL_HWREV_8130 0x7C000000
184 #define RL_HWREV_8139C 0x74000000
185 #define RL_HWREV_8139D 0x74400000
186 #define RL_HWREV_8139CPLUS 0x74800000
187 #define RL_HWREV_8101 0x74C00000
188 #define RL_HWREV_8100 0x78800000
189 #define RL_HWREV_8169_8110SBL 0x7CC00000
190 #define RL_HWREV_8169_8110SCE 0x98000000
192 #define RL_TXDMA_16BYTES 0x00000000
193 #define RL_TXDMA_32BYTES 0x00000100
194 #define RL_TXDMA_64BYTES 0x00000200
195 #define RL_TXDMA_128BYTES 0x00000300
196 #define RL_TXDMA_256BYTES 0x00000400
197 #define RL_TXDMA_512BYTES 0x00000500
198 #define RL_TXDMA_1024BYTES 0x00000600
199 #define RL_TXDMA_2048BYTES 0x00000700
202 * Transmit descriptor status register bits.
204 #define RL_TXSTAT_LENMASK 0x00001FFF
205 #define RL_TXSTAT_OWN 0x00002000
206 #define RL_TXSTAT_TX_UNDERRUN 0x00004000
207 #define RL_TXSTAT_TX_OK 0x00008000
208 #define RL_TXSTAT_EARLY_THRESH 0x003F0000
209 #define RL_TXSTAT_COLLCNT 0x0F000000
210 #define RL_TXSTAT_CARR_HBEAT 0x10000000
211 #define RL_TXSTAT_OUTOFWIN 0x20000000
212 #define RL_TXSTAT_TXABRT 0x40000000
213 #define RL_TXSTAT_CARRLOSS 0x80000000
216 * Interrupt status register bits.
218 #define RL_ISR_RX_OK 0x0001
219 #define RL_ISR_RX_ERR 0x0002
220 #define RL_ISR_TX_OK 0x0004
221 #define RL_ISR_TX_ERR 0x0008
222 #define RL_ISR_RX_OVERRUN 0x0010
223 #define RL_ISR_PKT_UNDERRUN 0x0020
224 #define RL_ISR_LINKCHG 0x0020 /* 8169 only */
225 #define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
226 #define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
227 #define RL_ISR_SWI 0x0100 /* C+ only */
228 #define RL_ISR_CABLE_LEN_CHGD 0x2000
229 #define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
230 #define RL_ISR_TIMEOUT_EXPIRED 0x4000
231 #define RL_ISR_SYSTEM_ERR 0x8000
234 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
235 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
236 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
238 #ifdef RE_TX_MODERATION
239 #define RL_INTRS_CPLUS \
240 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
241 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
242 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
244 #define RL_INTRS_CPLUS \
245 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
246 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
247 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
251 * Media status register. (8139 only)
253 #define RL_MEDIASTAT_RXPAUSE 0x01
254 #define RL_MEDIASTAT_TXPAUSE 0x02
255 #define RL_MEDIASTAT_LINK 0x04
256 #define RL_MEDIASTAT_SPEED10 0x08
257 #define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
258 #define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
261 * Receive config register.
263 #define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
264 #define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
265 #define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
266 #define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
267 #define RL_RXCFG_RX_RUNT 0x00000010
268 #define RL_RXCFG_RX_ERRPKT 0x00000020
269 #define RL_RXCFG_WRAP 0x00000080
270 #define RL_RXCFG_MAXDMA 0x00000700
271 #define RL_RXCFG_BUFSZ 0x00001800
272 #define RL_RXCFG_FIFOTHRESH 0x0000E000
273 #define RL_RXCFG_EARLYTHRESH 0x07000000
275 #define RL_RXDMA_16BYTES 0x00000000
276 #define RL_RXDMA_32BYTES 0x00000100
277 #define RL_RXDMA_64BYTES 0x00000200
278 #define RL_RXDMA_128BYTES 0x00000300
279 #define RL_RXDMA_256BYTES 0x00000400
280 #define RL_RXDMA_512BYTES 0x00000500
281 #define RL_RXDMA_1024BYTES 0x00000600
282 #define RL_RXDMA_UNLIMITED 0x00000700
284 #define RL_RXBUF_8 0x00000000
285 #define RL_RXBUF_16 0x00000800
286 #define RL_RXBUF_32 0x00001000
287 #define RL_RXBUF_64 0x00001800
289 #define RL_RXFIFO_16BYTES 0x00000000
290 #define RL_RXFIFO_32BYTES 0x00002000
291 #define RL_RXFIFO_64BYTES 0x00004000
292 #define RL_RXFIFO_128BYTES 0x00006000
293 #define RL_RXFIFO_256BYTES 0x00008000
294 #define RL_RXFIFO_512BYTES 0x0000A000
295 #define RL_RXFIFO_1024BYTES 0x0000C000
296 #define RL_RXFIFO_NOTHRESH 0x0000E000
299 * Bits in RX status header (included with RX'ed packet
302 #define RL_RXSTAT_RXOK 0x00000001
303 #define RL_RXSTAT_ALIGNERR 0x00000002
304 #define RL_RXSTAT_CRCERR 0x00000004
305 #define RL_RXSTAT_GIANT 0x00000008
306 #define RL_RXSTAT_RUNT 0x00000010
307 #define RL_RXSTAT_BADSYM 0x00000020
308 #define RL_RXSTAT_BROAD 0x00002000
309 #define RL_RXSTAT_INDIV 0x00004000
310 #define RL_RXSTAT_MULTI 0x00008000
311 #define RL_RXSTAT_LENMASK 0xFFFF0000
313 #define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
317 #define RL_CMD_EMPTY_RXBUF 0x0001
318 #define RL_CMD_TX_ENB 0x0004
319 #define RL_CMD_RX_ENB 0x0008
320 #define RL_CMD_RESET 0x0010
321 #define RL_CMD_STOPREQ 0x0080
324 * Twister register values. These are completely undocumented and derived
325 * from public sources.
327 #define RL_CSCFG_LINK_OK 0x0400
328 #define RL_CSCFG_CHANGE 0x0800
329 #define RL_CSCFG_STATUS 0xf000
330 #define RL_CSCFG_ROW3 0x7000
331 #define RL_CSCFG_ROW2 0x3000
332 #define RL_CSCFG_ROW1 0x1000
333 #define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0
334 #define RL_CSCFG_LINK_DOWN_CMD 0xf3c0
336 #define RL_NWAYTST_RESET 0
337 #define RL_NWAYTST_CBL_TEST 0x20
339 #define RL_PARA78 0x78
340 #define RL_PARA78_DEF 0x78fa8388
341 #define RL_PARA7C 0x7C
342 #define RL_PARA7C_DEF 0xcb38de43
343 #define RL_PARA7C_RETUNE 0xfb38de03
345 * EEPROM control register
347 #define RL_EE_DATAOUT 0x01 /* Data out */
348 #define RL_EE_DATAIN 0x02 /* Data in */
349 #define RL_EE_CLK 0x04 /* clock */
350 #define RL_EE_SEL 0x08 /* chip select */
351 #define RL_EE_MODE (0x40|0x80)
353 #define RL_EEMODE_OFF 0x00
354 #define RL_EEMODE_AUTOLOAD 0x40
355 #define RL_EEMODE_PROGRAM 0x80
356 #define RL_EEMODE_WRITECFG (0x80|0x40)
358 /* 9346 EEPROM commands */
359 #define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
360 #define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
362 #define RL_9346_WRITE 0x5
363 #define RL_9346_READ 0x6
364 #define RL_9346_ERASE 0x7
365 #define RL_9346_EWEN 0x4
366 #define RL_9346_EWEN_ADDR 0x30
367 #define RL_9456_EWDS 0x4
368 #define RL_9346_EWDS_ADDR 0x00
370 #define RL_EECMD_WRITE 0x140
371 #define RL_EECMD_READ_6BIT 0x180
372 #define RL_EECMD_READ_8BIT 0x600
373 #define RL_EECMD_ERASE 0x1c0
375 #define RL_EE_ID 0x00
376 #define RL_EE_PCI_VID 0x01
377 #define RL_EE_PCI_DID 0x02
378 /* Location of station address inside EEPROM */
379 #define RL_EE_EADDR 0x07
382 * MII register (8129 only)
384 #define RL_MII_CLK 0x01
385 #define RL_MII_DATAIN 0x02
386 #define RL_MII_DATAOUT 0x04
387 #define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
392 #define RL_CFG0_ROM0 0x01
393 #define RL_CFG0_ROM1 0x02
394 #define RL_CFG0_ROM2 0x04
395 #define RL_CFG0_PL0 0x08
396 #define RL_CFG0_PL1 0x10
397 #define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
398 #define RL_CFG0_PCS 0x40
399 #define RL_CFG0_SCR 0x80
404 #define RL_CFG1_PWRDWN 0x01
405 #define RL_CFG1_PME 0x01
406 #define RL_CFG1_SLEEP 0x02
407 #define RL_CFG1_VPDEN 0x02
408 #define RL_CFG1_IOMAP 0x04
409 #define RL_CFG1_MEMMAP 0x08
410 #define RL_CFG1_RSVD 0x10
411 #define RL_CFG1_LWACT 0x10
412 #define RL_CFG1_DRVLOAD 0x20
413 #define RL_CFG1_LED0 0x40
414 #define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
415 #define RL_CFG1_LED1 0x80
420 #define RL_CFG2_PCI33MHZ 0x00
421 #define RL_CFG2_PCI66MHZ 0x01
422 #define RL_CFG2_PCI64BIT 0x08
423 #define RL_CFG2_AUXPWR 0x10
424 #define RL_CFG2_MSI 0x20
429 #define RL_CFG3_GRANTSEL 0x80
430 #define RL_CFG3_WOL_MAGIC 0x20
431 #define RL_CFG3_WOL_LINK 0x10
432 #define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */
433 #define RL_CFG3_FAST_B2B 0x01
438 #define RL_CFG4_LWPTN 0x04
439 #define RL_CFG4_LWPME 0x10
440 #define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */
445 #define RL_CFG5_WOL_BCAST 0x40
446 #define RL_CFG5_WOL_MCAST 0x20
447 #define RL_CFG5_WOL_UCAST 0x10
448 #define RL_CFG5_WOL_LANWAKE 0x02
449 #define RL_CFG5_PME_STS 0x01
452 * 8139C+ register definitions
455 /* RL_DUMPSTATS_LO register */
457 #define RL_DUMPSTATS_START 0x00000008
459 /* Transmit start register */
461 #define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
462 #define RL_TXSTART_START 0x40 /* start normal queue transmit */
463 #define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
466 * Config 2 register, 8139C+/8169/8169S/8110S only
468 #define RL_CFG2_BUSFREQ 0x07
469 #define RL_CFG2_BUSWIDTH 0x08
470 #define RL_CFG2_AUXPWRSTS 0x10
472 #define RL_BUSFREQ_33MHZ 0x00
473 #define RL_BUSFREQ_66MHZ 0x01
475 #define RL_BUSWIDTH_32BITS 0x00
476 #define RL_BUSWIDTH_64BITS 0x08
478 /* C+ mode command register */
480 #define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
481 #define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
482 #define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
483 #define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
484 #define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
485 #define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
486 #define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
487 #define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
488 #define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
489 #define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
490 #define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
491 #define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
492 #define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
493 #define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
494 #define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
496 /* C+ early transmit threshold */
498 #define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
501 * Gigabit PHY access register (8169 only)
504 #define RL_PHYAR_PHYDATA 0x0000FFFF
505 #define RL_PHYAR_PHYREG 0x001F0000
506 #define RL_PHYAR_BUSY 0x80000000
509 * Gigabit media status (8169 only)
511 #define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
512 #define RL_GMEDIASTAT_LINK 0x02 /* link up */
513 #define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
514 #define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
515 #define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
516 #define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
517 #define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
518 #define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
521 * The RealTek doesn't use a fragment-based descriptor mechanism.
522 * Instead, there are only four register sets, each or which represents
523 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
524 * packet buffer (32-bit aligned!) and we place the buffer addresses in
525 * the registers so the chip knows where they are.
527 * We can sort of kludge together the same kind of buffer management
528 * used in previous drivers, but we have to do buffer copies almost all
529 * the time, so it doesn't really buy us much.
531 * For reception, there's just one large buffer where the chip stores
532 * all received packets.
535 #define RL_RX_BUF_SZ RL_RXBUF_64
536 #define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
537 #define RL_TX_LIST_CNT 4
538 #define RL_MIN_FRAMELEN 60
539 #define RL_TX_8139_BUF_ALIGN 4
540 #define RL_RX_8139_BUF_ALIGN 8
541 #define RL_RX_8139_BUF_RESERVE sizeof(int64_t)
542 #define RL_RX_8139_BUF_GUARD_SZ \
543 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE)
544 #define RL_TXTHRESH(x) ((x) << 11)
545 #define RL_TX_THRESH_INIT 96
546 #define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
547 #define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
548 #define RL_TX_MAXDMA RL_TXDMA_2048BYTES
550 #define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
551 #define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
553 #define RL_ETHER_ALIGN 2
556 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
558 #define RL_IP4CSUMTX_MINLEN 28
559 #define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
561 struct rl_chain_data {
564 uint8_t *rl_rx_buf_ptr;
566 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
567 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
568 bus_dma_tag_t rl_tx_tag;
569 bus_dma_tag_t rl_rx_tag;
570 bus_dmamap_t rl_rx_dmamap;
571 bus_addr_t rl_rx_buf_paddr;
576 #define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
577 #define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
578 #define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
579 #define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
580 #define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
581 #define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
582 #define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
583 #define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
584 #define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
600 struct rl_mii_frame {
605 uint8_t mii_turnaround;
612 #define RL_MII_STARTDELIM 0x01
613 #define RL_MII_READOP 0x02
614 #define RL_MII_WRITEOP 0x01
615 #define RL_MII_TURNAROUND 0x02
619 #define RL_8139CPLUS 3
622 #define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
623 (x)->rl_type == RL_8169)
626 * The 8139C+ and 8160 gigE chips support descriptor-based TX
627 * and RX. In fact, they even support TCP large send. Descriptors
628 * must be allocated in contiguous blocks that are aligned on a
629 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
633 * RX/TX descriptor definition. When large send mode is enabled, the
634 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
635 * the checksum offload bits are disabled. The structure layout is
636 * the same for RX and TX descriptors
642 uint32_t rl_bufaddr_lo;
643 uint32_t rl_bufaddr_hi;
646 #define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
647 #define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
648 #define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
649 #define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
650 #define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
651 #define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
652 #define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
653 #define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
654 #define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
655 #define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
656 #define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
658 #define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
659 #define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
660 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
661 #define RL_TDESC_CMD_UDPCSUMV2 0x80000000
662 #define RL_TDESC_CMD_TCPCSUMV2 0x40000000
663 #define RL_TDESC_CMD_IPCSUMV2 0x20000000
664 #define RL_TDESC_CMD_MSSVALV2 0x1FFC0000
665 #define RL_TDESC_CMD_MSSVALV2_SHIFT 18
668 * Error bits are valid only on the last descriptor of a frame
669 * (i.e. RL_TDESC_CMD_EOF == 1)
672 #define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
673 #define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
674 #define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
675 #define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
676 #define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
677 #define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
678 #define RL_TDESC_STAT_OWN 0x80000000
681 * RX descriptor cmd/vlan definitions
684 #define RL_RDESC_CMD_EOR 0x40000000
685 #define RL_RDESC_CMD_OWN 0x80000000
686 #define RL_RDESC_CMD_BUFLEN 0x00001FFF
688 #define RL_RDESC_STAT_OWN 0x80000000
689 #define RL_RDESC_STAT_EOR 0x40000000
690 #define RL_RDESC_STAT_SOF 0x20000000
691 #define RL_RDESC_STAT_EOF 0x10000000
692 #define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
693 #define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
694 #define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
695 #define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
696 #define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
697 #define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
698 #define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
699 #define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
700 #define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
701 #define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
702 #define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
703 #define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */
704 #define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */
705 #define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
706 #define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
707 #define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
708 #define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
709 #define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
710 #define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
711 RL_RDESC_STAT_CRCERR)
713 #define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
714 (rl_vlandata valid)*/
715 #define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
716 /* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
717 #define RL_RDESC_IPV6 0x80000000
718 #define RL_RDESC_IPV4 0x40000000
720 #define RL_PROTOID_NONIP 0x00000000
721 #define RL_PROTOID_TCPIP 0x00010000
722 #define RL_PROTOID_UDPIP 0x00020000
723 #define RL_PROTOID_IP 0x00030000
724 #define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
726 #define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
730 * Statistics counter structure (8139C+ and 8169 only)
737 uint16_t rl_missed_pkts;
738 uint16_t rl_rx_framealign_errs;
739 uint32_t rl_tx_onecoll;
740 uint32_t rl_tx_multicolls;
741 uint64_t rl_rx_ucasts;
742 uint64_t rl_rx_bcasts;
743 uint32_t rl_rx_mcasts;
744 uint16_t rl_tx_aborts;
745 uint16_t rl_rx_underruns;
749 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
752 * Number of descriptors supported : up to 64
753 * Descriptor alignment : 256 bytes
754 * Tx buffer : At least 4 bytes in length.
755 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
758 * Number of descriptors supported : up to 1024
759 * Descriptor alignment : 256 bytes
760 * Tx buffer : At least 4 bytes in length.
761 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
763 #ifndef __NO_STRICT_ALIGNMENT
764 #define RE_FIXUP_RX 1
767 #define RL_8169_TX_DESC_CNT 256
768 #define RL_8169_RX_DESC_CNT 256
769 #define RL_8139_TX_DESC_CNT 64
770 #define RL_8139_RX_DESC_CNT 64
771 #define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
772 #define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
773 #define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT
774 #define RL_NTXSEGS 32
776 #define RL_RING_ALIGN 256
777 #define RL_DUMP_ALIGN 64
778 #define RL_IFQ_MAXLEN 512
779 #define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
780 #define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
781 #define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
782 #define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
783 #define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
784 #define RL_PKTSZ(x) ((x)/* >> 3*/)
786 #define RE_ETHER_ALIGN sizeof(uint64_t)
787 #define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
789 #define RE_ETHER_ALIGN 0
790 #define RE_RX_DESC_BUFLEN MCLBYTES
793 #define RL_MSI_MESSAGES 1
795 #define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
796 #define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
799 * The number of bits reserved for MSS in RealTek controllers is
800 * 11bits. This limits the maximum interface MTU size in TSO case
801 * as upper stack should not generate TCP segments with MSS greater
804 #define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN)
806 /* see comment in dev/re/if_re.c */
807 #define RL_JUMBO_FRAMELEN 7440
808 #define RL_JUMBO_MTU \
809 (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
810 #define RL_JUMBO_MTU_6K \
811 ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
812 #define RL_JUMBO_MTU_9K \
813 ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
815 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
819 bus_dmamap_t tx_dmamap;
824 bus_dmamap_t rx_dmamap;
828 struct rl_list_data {
829 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
830 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
831 struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT];
838 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
839 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
840 bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */
841 bus_dmamap_t rl_rx_sparemap;
842 bus_dmamap_t rl_jrx_sparemap;
843 bus_dma_tag_t rl_stag; /* stats mapping tag */
844 bus_dmamap_t rl_smap; /* stats map */
845 struct rl_stats *rl_stats;
846 bus_addr_t rl_stats_addr;
847 bus_dma_tag_t rl_rx_list_tag;
848 bus_dmamap_t rl_rx_list_map;
849 struct rl_desc *rl_rx_list;
850 bus_addr_t rl_rx_list_addr;
851 bus_dma_tag_t rl_tx_list_tag;
852 bus_dmamap_t rl_tx_list_map;
853 struct rl_desc *rl_tx_list;
854 bus_addr_t rl_tx_list_addr;
857 enum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE };
860 struct ifnet *rl_ifp; /* interface info */
861 bus_space_handle_t rl_bhandle; /* bus space handle */
862 bus_space_tag_t rl_btag; /* bus space tag */
864 struct resource *rl_res;
867 struct resource *rl_irq[RL_MSI_MESSAGES];
868 void *rl_intrhand[RL_MSI_MESSAGES];
870 bus_dma_tag_t rl_parent_tag;
872 struct rl_hwrev *rl_hwrev;
876 struct rl_chain_data rl_cdata;
877 struct rl_list_data rl_ldata;
878 struct callout rl_stat_callout;
879 int rl_watchdog_timer;
881 struct mbuf *rl_head;
882 struct mbuf *rl_tail;
883 uint32_t rl_rxlenmask;
886 int rl_twister_enable;
887 enum rl_twist rl_twister;
890 int suspended; /* 0 = normal 1 = suspended */
891 #ifdef DEVICE_POLLING
895 struct task rl_txtask;
896 struct task rl_inttask;
900 #define RL_FLAG_MSI 0x0001
901 #define RL_FLAG_AUTOPAD 0x0002
902 #define RL_FLAG_PHYWAKE_PM 0x0004
903 #define RL_FLAG_PHYWAKE 0x0008
904 #define RL_FLAG_JUMBOV2 0x0010
905 #define RL_FLAG_PAR 0x0020
906 #define RL_FLAG_DESCV2 0x0040
907 #define RL_FLAG_MACSTAT 0x0080
908 #define RL_FLAG_FASTETHER 0x0100
909 #define RL_FLAG_CMDSTOP 0x0200
910 #define RL_FLAG_MACRESET 0x0400
911 #define RL_FLAG_WOLRXENB 0x1000
912 #define RL_FLAG_MACSLEEP 0x2000
913 #define RL_FLAG_PCIE 0x4000
914 #define RL_FLAG_LINK 0x8000
917 #define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
918 #define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
919 #define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
922 * register space access macros
924 #define CSR_WRITE_STREAM_4(sc, reg, val) \
925 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
926 #define CSR_WRITE_4(sc, reg, val) \
927 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
928 #define CSR_WRITE_2(sc, reg, val) \
929 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
930 #define CSR_WRITE_1(sc, reg, val) \
931 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
933 #define CSR_READ_4(sc, reg) \
934 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
935 #define CSR_READ_2(sc, reg) \
936 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
937 #define CSR_READ_1(sc, reg) \
938 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
940 #define CSR_SETBIT_1(sc, offset, val) \
941 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
943 #define CSR_CLRBIT_1(sc, offset, val) \
944 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
946 #define CSR_SETBIT_2(sc, offset, val) \
947 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
949 #define CSR_CLRBIT_2(sc, offset, val) \
950 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
952 #define CSR_SETBIT_4(sc, offset, val) \
953 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
955 #define CSR_CLRBIT_4(sc, offset, val) \
956 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
958 #define RL_TIMEOUT 1000
959 #define RL_PHY_TIMEOUT 2000
962 * General constants that are fun to know.
964 * RealTek PCI vendor ID
966 #define RT_VENDORID 0x10EC
969 * RealTek chip device IDs.
971 #define RT_DEVICEID_8139D 0x8039
972 #define RT_DEVICEID_8129 0x8129
973 #define RT_DEVICEID_8101E 0x8136
974 #define RT_DEVICEID_8138 0x8138
975 #define RT_DEVICEID_8139 0x8139
976 #define RT_DEVICEID_8169SC 0x8167
977 #define RT_DEVICEID_8168 0x8168
978 #define RT_DEVICEID_8169 0x8169
979 #define RT_DEVICEID_8100 0x8100
981 #define RT_REVID_8139CPLUS 0x20
984 * Accton PCI vendor ID
986 #define ACCTON_VENDORID 0x1113
989 * Accton MPX 5030/5038 device ID.
991 #define ACCTON_DEVICEID_5030 0x1211
994 * Nortel PCI vendor ID
996 #define NORTEL_VENDORID 0x126C
999 * Delta Electronics Vendor ID.
1001 #define DELTA_VENDORID 0x1500
1006 #define DELTA_DEVICEID_8139 0x1360
1009 * Addtron vendor ID.
1011 #define ADDTRON_VENDORID 0x4033
1014 * Addtron device IDs.
1016 #define ADDTRON_DEVICEID_8139 0x1360
1021 #define DLINK_VENDORID 0x1186
1024 * D-Link DFE-530TX+ device ID
1026 #define DLINK_DEVICEID_530TXPLUS 0x1300
1029 * D-Link DFE-5280T device ID
1031 #define DLINK_DEVICEID_528T 0x4300
1034 * D-Link DFE-690TXD device ID
1036 #define DLINK_DEVICEID_690TXD 0x1340
1039 * Corega K.K vendor ID
1041 #define COREGA_VENDORID 0x1259
1044 * Corega FEther CB-TXD device ID
1046 #define COREGA_DEVICEID_FETHERCBTXD 0xa117
1049 * Corega FEtherII CB-TXD device ID
1051 #define COREGA_DEVICEID_FETHERIICBTXD 0xa11e
1054 * Corega CG-LAPCIGT device ID
1056 #define COREGA_DEVICEID_CGLAPCIGT 0xc107
1061 #define LINKSYS_VENDORID 0x1737
1064 * Linksys EG1032 device ID
1066 #define LINKSYS_DEVICEID_EG1032 0x1032
1069 * Linksys EG1032 rev 3 sub-device ID
1071 #define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024
1074 * Peppercon vendor ID
1076 #define PEPPERCON_VENDORID 0x1743
1079 * Peppercon ROL-F device ID
1081 #define PEPPERCON_DEVICEID_ROLF 0x8139
1084 * Planex Communications, Inc. vendor ID
1086 #define PLANEX_VENDORID 0x14ea
1089 * Planex FNW-3603-TX device ID
1091 #define PLANEX_DEVICEID_FNW3603TX 0xab06
1094 * Planex FNW-3800-TX device ID
1096 #define PLANEX_DEVICEID_FNW3800TX 0xab07
1099 * LevelOne vendor ID
1101 #define LEVEL1_VENDORID 0x018A
1104 * LevelOne FPC-0106TX devide ID
1106 #define LEVEL1_DEVICEID_FPC0106TX 0x0106
1111 #define CP_VENDORID 0x021B
1116 #define EDIMAX_VENDORID 0x13D1
1119 * Edimax EP-4103DL cardbus device ID
1121 #define EDIMAX_DEVICEID_EP4103DL 0xAB06
1123 /* US Robotics vendor ID */
1125 #define USR_VENDORID 0x16EC
1127 /* US Robotics 997902 device ID */
1129 #define USR_DEVICEID_997902 0x0116