2 * Copyright (c) 1998, 1999 Takanori Watanabe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <machine/bus.h>
39 #include <dev/smbus/smbconf.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #include <pci/intpmreg.h>
47 #include "opt_intpm.h"
51 struct resource *io_res;
52 struct resource *irq_res;
61 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock)
62 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock)
63 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED)
65 static int intsmb_probe(device_t);
66 static int intsmb_attach(device_t);
67 static int intsmb_detach(device_t);
68 static int intsmb_intr(struct intsmb_softc *sc);
69 static int intsmb_slvintr(struct intsmb_softc *sc);
70 static void intsmb_alrintr(struct intsmb_softc *sc);
71 static int intsmb_callback(device_t dev, int index, void *data);
72 static int intsmb_quick(device_t dev, u_char slave, int how);
73 static int intsmb_sendb(device_t dev, u_char slave, char byte);
74 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
75 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
76 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
77 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
78 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
79 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
80 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
81 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
82 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr);
83 static int intsmb_stop(struct intsmb_softc *sc);
84 static int intsmb_stop_poll(struct intsmb_softc *sc);
85 static int intsmb_free(struct intsmb_softc *sc);
86 static void intsmb_rawintr(void *arg);
89 intsmb_probe(device_t dev)
92 switch (pci_get_devid(dev)) {
93 case 0x71138086: /* Intel 82371AB */
94 case 0x719b8086: /* Intel 82443MX */
96 /* Not a good idea yet, this stops isab0 functioning */
97 case 0x02001166: /* ServerWorks OSB4 */
99 device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
102 device_set_desc(dev, "AMD SB600/700/710/750 SMBus Controller");
103 /* XXX Maybe force polling right here? */
109 return (BUS_PROBE_DEFAULT);
113 intsmb_attach(device_t dev)
115 struct intsmb_softc *sc = device_get_softc(dev);
116 int error, rid, value;
122 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
125 #ifndef NO_CHANGE_PCICONF
126 switch (pci_get_devid(dev)) {
127 case 0x71138086: /* Intel 82371AB */
128 case 0x719b8086: /* Intel 82443MX */
129 /* Changing configuration is allowed. */
135 rid = PCI_BASE_ADDR_SMB;
136 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
138 if (sc->io_res == NULL) {
139 device_printf(dev, "Could not allocate I/O space\n");
145 pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
146 pci_write_config(dev, PCI_HST_CFG_SMB,
147 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
149 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
150 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
151 intr = value & PCI_INTR_SMB_MASK;
153 case PCI_INTR_SMB_SMI:
156 case PCI_INTR_SMB_IRQ9:
159 case PCI_INTR_SMB_IRQ_PCI:
166 device_printf(dev, "intr %s %s ", str,
167 sc->poll == 0 ? "enabled" : "disabled");
168 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
170 if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
172 "using polling mode when configured interrupt is SMI\n");
179 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
180 device_printf(dev, "Unsupported interrupt mode\n");
188 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
190 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
191 RF_SHAREABLE | RF_ACTIVE);
192 if (sc->irq_res == NULL) {
193 device_printf(dev, "Could not allocate irq\n");
198 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
199 NULL, intsmb_rawintr, sc, &sc->irq_hand);
201 device_printf(dev, "Failed to map intr\n");
207 sc->smbus = device_add_child(dev, "smbus", -1);
208 if (sc->smbus == NULL) {
212 error = device_probe_and_attach(sc->smbus);
218 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
228 intsmb_detach(device_t dev)
230 struct intsmb_softc *sc = device_get_softc(dev);
233 error = bus_generic_detach(dev);
238 device_delete_child(dev, sc->smbus);
240 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
242 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
244 bus_release_resource(dev, SYS_RES_IOPORT, PCI_BASE_ADDR_SMB,
246 mtx_destroy(&sc->lock);
251 intsmb_rawintr(void *arg)
253 struct intsmb_softc *sc = arg;
262 intsmb_callback(device_t dev, int index, void *data)
267 case SMB_REQUEST_BUS:
269 case SMB_RELEASE_BUS:
278 /* Counterpart of smbtx_smb_free(). */
280 intsmb_free(struct intsmb_softc *sc)
283 INTSMB_LOCK_ASSERT(sc);
284 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
286 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
292 /* Disable Interrupt in slave part. */
294 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
296 /* Reset INTR Flag to prepare INTR. */
297 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
298 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
299 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
304 intsmb_intr(struct intsmb_softc *sc)
308 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
309 if (status & PIIX4_SMBHSTSTAT_BUSY)
312 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
313 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
315 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
316 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
317 tmp & ~PIIX4_SMBHSTCNT_INTREN);
324 return (1); /* Not Completed */
328 intsmb_slvintr(struct intsmb_softc *sc)
332 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
333 if (status & PIIX4_SMBSLVSTS_BUSY)
335 if (status & PIIX4_SMBSLVSTS_ALART)
337 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
338 | PIIX4_SMBSLVSTS_SDW1)) {
341 /* Reset Status Register */
342 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
343 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
344 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
349 intsmb_alrintr(struct intsmb_softc *sc)
357 /* Stop generating INTR from ALART. */
358 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
360 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
361 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
365 /* Ask bus who asserted it and then ask it what's the matter. */
367 error = intsmb_free(sc);
371 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
372 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
373 error = intsmb_stop_poll(sc);
375 device_printf(sc->dev, "ALART: ERROR\n");
377 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
378 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
381 /* Re-enable INTR from ALART. */
382 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
383 slvcnt | PIIX4_SMBSLVCNT_ALTEN);
389 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
393 INTSMB_LOCK_ASSERT(sc);
394 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
397 tmp |= PIIX4_SMBHSTCNT_START;
399 /* While not in autoconfiguration enable interrupts. */
400 if (!sc->poll && !cold && !nointr)
401 tmp |= PIIX4_SMBHSTCNT_INTREN;
402 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
406 intsmb_error(device_t dev, int status)
410 if (status & PIIX4_SMBHSTSTAT_ERR)
411 error |= SMB_EBUSERR;
412 if (status & PIIX4_SMBHSTSTAT_BUSC)
414 if (status & PIIX4_SMBHSTSTAT_FAIL)
417 if (error != 0 && bootverbose)
418 device_printf(dev, "error = %d, status = %#x\n", error, status);
426 * Polling is not encouraged because it requires waiting for the
427 * device if it is busy.
428 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
432 intsmb_stop_poll(struct intsmb_softc *sc)
434 int error, i, status, tmp;
436 INTSMB_LOCK_ASSERT(sc);
438 /* First, wait for busy to be set. */
439 for (i = 0; i < 0x7fff; i++)
440 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
441 PIIX4_SMBHSTSTAT_BUSY)
444 /* Wait for busy to clear. */
445 for (i = 0; i < 0x7fff; i++) {
446 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
447 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
449 error = intsmb_error(sc->dev, status);
454 /* Timed out waiting for busy to clear. */
456 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
457 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
458 return (SMB_ETIMEOUT);
462 * Wait for completion and return result.
465 intsmb_stop(struct intsmb_softc *sc)
469 INTSMB_LOCK_ASSERT(sc);
471 if (sc->poll || cold)
472 /* So that it can use device during device probe on SMBus. */
473 return (intsmb_stop_poll(sc));
475 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8);
477 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
478 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
479 error = intsmb_error(sc->dev, status);
480 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
481 device_printf(sc->dev, "unknown cause why?\n");
483 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
484 PIIX4_SMBSLVCNT_ALTEN);
490 /* Timeout Procedure. */
493 /* Re-enable supressed interrupt from slave part. */
494 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
495 if (error == EWOULDBLOCK)
496 return (SMB_ETIMEOUT);
502 intsmb_quick(device_t dev, u_char slave, int how)
504 struct intsmb_softc *sc = device_get_softc(dev);
510 /* Quick command is part of Address, I think. */
523 error = intsmb_free(sc);
528 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
529 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0);
530 error = intsmb_stop(sc);
536 intsmb_sendb(device_t dev, u_char slave, char byte)
538 struct intsmb_softc *sc = device_get_softc(dev);
542 error = intsmb_free(sc);
547 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
548 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
549 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
550 error = intsmb_stop(sc);
556 intsmb_recvb(device_t dev, u_char slave, char *byte)
558 struct intsmb_softc *sc = device_get_softc(dev);
562 error = intsmb_free(sc);
567 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
568 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
569 error = intsmb_stop(sc);
571 #ifdef RECV_IS_IN_CMD
573 * Linux SMBus stuff also troubles
574 * Because Intel's datasheet does not make clear.
576 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
578 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
586 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
588 struct intsmb_softc *sc = device_get_softc(dev);
592 error = intsmb_free(sc);
597 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
598 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
599 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
600 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
601 error = intsmb_stop(sc);
607 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
609 struct intsmb_softc *sc = device_get_softc(dev);
613 error = intsmb_free(sc);
618 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
619 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
620 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
621 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
622 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
623 error = intsmb_stop(sc);
629 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
631 struct intsmb_softc *sc = device_get_softc(dev);
635 error = intsmb_free(sc);
640 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
641 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
642 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
643 error = intsmb_stop(sc);
645 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
651 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
653 struct intsmb_softc *sc = device_get_softc(dev);
657 error = intsmb_free(sc);
662 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
663 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
664 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
665 error = intsmb_stop(sc);
667 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
668 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
675 * Data sheet claims that it implements all function, but also claims
676 * that it implements 7 function and not mention PCALL. So I don't know
677 * whether it will work.
680 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
683 struct intsmb_softc *sc = device_get_softc(dev);
687 error = intsmb_free(sc);
692 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
693 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
694 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, sdata & 0xff);
695 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (sdata & 0xff) >> 8);
696 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
697 error = intsmb_stop(sc);
699 *rdata = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
700 *rdata |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
705 return (SMB_ENOTSUPP);
710 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
712 struct intsmb_softc *sc = device_get_softc(dev);
715 if (count > SMBBLOCKTRANS_MAX || count == 0)
719 error = intsmb_free(sc);
725 /* Reset internal array index. */
726 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
728 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
729 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
730 for (i = 0; i < count; i++)
731 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
732 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
733 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
734 error = intsmb_stop(sc);
740 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
742 struct intsmb_softc *sc = device_get_softc(dev);
746 if (*count > SMBBLOCKTRANS_MAX || *count == 0)
750 error = intsmb_free(sc);
756 /* Reset internal array index. */
757 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
759 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
760 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
761 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, *count);
762 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
763 error = intsmb_stop(sc);
765 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
766 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
767 for (i = 0; i < nread; i++) {
768 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
780 static devclass_t intsmb_devclass;
782 static device_method_t intsmb_methods[] = {
783 /* Device interface */
784 DEVMETHOD(device_probe, intsmb_probe),
785 DEVMETHOD(device_attach, intsmb_attach),
786 DEVMETHOD(device_detach, intsmb_detach),
789 DEVMETHOD(bus_print_child, bus_generic_print_child),
791 /* SMBus interface */
792 DEVMETHOD(smbus_callback, intsmb_callback),
793 DEVMETHOD(smbus_quick, intsmb_quick),
794 DEVMETHOD(smbus_sendb, intsmb_sendb),
795 DEVMETHOD(smbus_recvb, intsmb_recvb),
796 DEVMETHOD(smbus_writeb, intsmb_writeb),
797 DEVMETHOD(smbus_writew, intsmb_writew),
798 DEVMETHOD(smbus_readb, intsmb_readb),
799 DEVMETHOD(smbus_readw, intsmb_readw),
800 DEVMETHOD(smbus_pcall, intsmb_pcall),
801 DEVMETHOD(smbus_bwrite, intsmb_bwrite),
802 DEVMETHOD(smbus_bread, intsmb_bread),
807 static driver_t intsmb_driver = {
810 sizeof(struct intsmb_softc),
813 DRIVER_MODULE(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0);
814 DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0);
815 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
816 MODULE_VERSION(intsmb, 1);