2 * Copyright (c) 1998, 1999 Takanori Watanabe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/mutex.h>
38 #include <machine/bus.h>
39 #include <dev/smbus/smbconf.h>
43 #include <dev/pci/pcireg.h>
44 #include <dev/pci/pcivar.h>
45 #include <pci/intpmreg.h>
46 #include <dev/amdsbwd/amd_chipset.h>
48 #include "opt_intpm.h"
52 struct resource *io_res;
53 struct resource *irq_res;
64 #define INTSMB_LOCK(sc) mtx_lock(&(sc)->lock)
65 #define INTSMB_UNLOCK(sc) mtx_unlock(&(sc)->lock)
66 #define INTSMB_LOCK_ASSERT(sc) mtx_assert(&(sc)->lock, MA_OWNED)
68 static int intsmb_probe(device_t);
69 static int intsmb_attach(device_t);
70 static int intsmb_detach(device_t);
71 static int intsmb_intr(struct intsmb_softc *sc);
72 static int intsmb_slvintr(struct intsmb_softc *sc);
73 static void intsmb_alrintr(struct intsmb_softc *sc);
74 static int intsmb_callback(device_t dev, int index, void *data);
75 static int intsmb_quick(device_t dev, u_char slave, int how);
76 static int intsmb_sendb(device_t dev, u_char slave, char byte);
77 static int intsmb_recvb(device_t dev, u_char slave, char *byte);
78 static int intsmb_writeb(device_t dev, u_char slave, char cmd, char byte);
79 static int intsmb_writew(device_t dev, u_char slave, char cmd, short word);
80 static int intsmb_readb(device_t dev, u_char slave, char cmd, char *byte);
81 static int intsmb_readw(device_t dev, u_char slave, char cmd, short *word);
82 static int intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata);
83 static int intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf);
84 static int intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf);
85 static void intsmb_start(struct intsmb_softc *sc, u_char cmd, int nointr);
86 static int intsmb_stop(struct intsmb_softc *sc);
87 static int intsmb_stop_poll(struct intsmb_softc *sc);
88 static int intsmb_free(struct intsmb_softc *sc);
89 static void intsmb_rawintr(void *arg);
92 intsmb_probe(device_t dev)
95 switch (pci_get_devid(dev)) {
96 case 0x71138086: /* Intel 82371AB */
97 case 0x719b8086: /* Intel 82443MX */
99 /* Not a good idea yet, this stops isab0 functioning */
100 case 0x02001166: /* ServerWorks OSB4 */
102 device_set_desc(dev, "Intel PIIX4 SMBUS Interface");
105 device_set_desc(dev, "ATI IXP400 SMBus Controller");
107 case AMDSB_SMBUS_DEVID:
108 device_set_desc(dev, "AMD SB600/7xx/8xx/9xx SMBus Controller");
110 case AMDFCH_SMBUS_DEVID: /* AMD FCH */
111 case AMDCZ_SMBUS_DEVID: /* AMD Carizzo FCH */
112 device_set_desc(dev, "AMD FCH SMBus Controller");
118 return (BUS_PROBE_DEFAULT);
122 amd_pmio_read(struct resource *res, uint8_t reg)
124 bus_write_1(res, 0, reg); /* Index */
125 return (bus_read_1(res, 1)); /* Data */
129 sb8xx_attach(device_t dev)
131 static const int AMDSB_SMBIO_WIDTH = 0x14;
132 struct intsmb_softc *sc;
133 struct resource *res;
141 sc = device_get_softc(dev);
143 rc = bus_set_resource(dev, SYS_RES_IOPORT, rid, AMDSB_PMIO_INDEX,
146 device_printf(dev, "bus_set_resource for PM IO failed\n");
149 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
152 device_printf(dev, "bus_alloc_resource for PM IO failed\n");
156 devid = pci_get_devid(dev);
157 revid = pci_get_revid(dev);
158 if (devid == AMDSB_SMBUS_DEVID ||
159 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) ||
160 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) {
161 addr = amd_pmio_read(res, AMDSB8_PM_SMBUS_EN + 1);
163 addr |= amd_pmio_read(res, AMDSB8_PM_SMBUS_EN);
164 enabled = (addr & AMDSB8_SMBUS_EN) != 0;
165 addr &= AMDSB8_SMBUS_ADDR_MASK;
167 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN0);
168 enabled = (addr & AMDFCH41_SMBUS_EN) != 0;
169 addr = amd_pmio_read(res, AMDFCH41_PM_DECODE_EN1);
173 bus_release_resource(dev, SYS_RES_IOPORT, rid, res);
174 bus_delete_resource(dev, SYS_RES_IOPORT, rid);
177 device_printf(dev, "SB8xx/SB9xx/FCH SMBus not enabled\n");
182 rc = bus_set_resource(dev, SYS_RES_IOPORT, sc->io_rid, addr,
185 device_printf(dev, "bus_set_resource for SMBus IO failed\n");
189 device_printf(dev, "bus_alloc_resource for SMBus IO failed\n");
192 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
199 intsmb_release_resources(device_t dev)
201 struct intsmb_softc *sc = device_get_softc(dev);
204 device_delete_child(dev, sc->smbus);
206 bus_teardown_intr(dev, sc->irq_res, sc->irq_hand);
208 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
210 bus_release_resource(dev, SYS_RES_IOPORT, sc->io_rid,
212 mtx_destroy(&sc->lock);
216 intsmb_attach(device_t dev)
218 struct intsmb_softc *sc = device_get_softc(dev);
219 int error, rid, value;
225 mtx_init(&sc->lock, device_get_nameunit(dev), "intsmb", MTX_DEF);
228 switch (pci_get_devid(dev)) {
229 #ifndef NO_CHANGE_PCICONF
230 case 0x71138086: /* Intel 82371AB */
231 case 0x719b8086: /* Intel 82443MX */
232 /* Changing configuration is allowed. */
236 case AMDSB_SMBUS_DEVID:
237 if (pci_get_revid(dev) >= AMDSB8_SMBUS_REVID)
240 case AMDFCH_SMBUS_DEVID:
241 case AMDCZ_SMBUS_DEVID:
247 error = sb8xx_attach(dev);
254 sc->io_rid = PCI_BASE_ADDR_SMB;
255 sc->io_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->io_rid,
257 if (sc->io_res == NULL) {
258 device_printf(dev, "Could not allocate I/O space\n");
264 pci_write_config(dev, PCIR_INTLINE, 0x9, 1);
265 pci_write_config(dev, PCI_HST_CFG_SMB,
266 PCI_INTR_SMB_IRQ9 | PCI_INTR_SMB_ENABLE, 1);
268 value = pci_read_config(dev, PCI_HST_CFG_SMB, 1);
269 sc->poll = (value & PCI_INTR_SMB_ENABLE) == 0;
270 intr = value & PCI_INTR_SMB_MASK;
272 case PCI_INTR_SMB_SMI:
275 case PCI_INTR_SMB_IRQ9:
278 case PCI_INTR_SMB_IRQ_PCI:
285 device_printf(dev, "intr %s %s ", str,
286 sc->poll == 0 ? "enabled" : "disabled");
287 printf("revision %d\n", pci_read_config(dev, PCI_REVID_SMB, 1));
289 if (!sc->poll && intr == PCI_INTR_SMB_SMI) {
291 "using polling mode when configured interrupt is SMI\n");
298 if (intr != PCI_INTR_SMB_IRQ9 && intr != PCI_INTR_SMB_IRQ_PCI) {
299 device_printf(dev, "Unsupported interrupt mode\n");
307 bus_set_resource(dev, SYS_RES_IRQ, rid, 9, 1);
309 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
310 RF_SHAREABLE | RF_ACTIVE);
311 if (sc->irq_res == NULL) {
312 device_printf(dev, "Could not allocate irq\n");
317 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
318 NULL, intsmb_rawintr, sc, &sc->irq_hand);
320 device_printf(dev, "Failed to map intr\n");
326 sc->smbus = device_add_child(dev, "smbus", -1);
327 if (sc->smbus == NULL) {
328 device_printf(dev, "failed to add smbus child\n");
332 error = device_probe_and_attach(sc->smbus);
334 device_printf(dev, "failed to probe+attach smbus child\n");
340 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
345 intsmb_release_resources(dev);
350 intsmb_detach(device_t dev)
354 error = bus_generic_detach(dev);
356 device_printf(dev, "bus detach failed\n");
360 intsmb_release_resources(dev);
365 intsmb_rawintr(void *arg)
367 struct intsmb_softc *sc = arg;
376 intsmb_callback(device_t dev, int index, void *data)
381 case SMB_REQUEST_BUS:
383 case SMB_RELEASE_BUS:
392 /* Counterpart of smbtx_smb_free(). */
394 intsmb_free(struct intsmb_softc *sc)
397 INTSMB_LOCK_ASSERT(sc);
398 if ((bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) & PIIX4_SMBHSTSTAT_BUSY) ||
400 (bus_read_1(sc->io_res, PIIX4_SMBSLVSTS) & PIIX4_SMBSLVSTS_BUSY) ||
406 /* Disable Interrupt in slave part. */
408 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, 0);
410 /* Reset INTR Flag to prepare INTR. */
411 bus_write_1(sc->io_res, PIIX4_SMBHSTSTS,
412 PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
413 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL);
418 intsmb_intr(struct intsmb_softc *sc)
422 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
423 if (status & PIIX4_SMBHSTSTAT_BUSY)
426 if (status & (PIIX4_SMBHSTSTAT_INTR | PIIX4_SMBHSTSTAT_ERR |
427 PIIX4_SMBHSTSTAT_BUSC | PIIX4_SMBHSTSTAT_FAIL)) {
429 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
430 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT,
431 tmp & ~PIIX4_SMBHSTCNT_INTREN);
438 return (1); /* Not Completed */
442 intsmb_slvintr(struct intsmb_softc *sc)
446 status = bus_read_1(sc->io_res, PIIX4_SMBSLVSTS);
447 if (status & PIIX4_SMBSLVSTS_BUSY)
449 if (status & PIIX4_SMBSLVSTS_ALART)
451 else if (status & ~(PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2
452 | PIIX4_SMBSLVSTS_SDW1)) {
455 /* Reset Status Register */
456 bus_write_1(sc->io_res, PIIX4_SMBSLVSTS,
457 PIIX4_SMBSLVSTS_ALART | PIIX4_SMBSLVSTS_SDW2 |
458 PIIX4_SMBSLVSTS_SDW1 | PIIX4_SMBSLVSTS_SLV);
463 intsmb_alrintr(struct intsmb_softc *sc)
471 /* Stop generating INTR from ALART. */
472 slvcnt = bus_read_1(sc->io_res, PIIX4_SMBSLVCNT);
474 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
475 slvcnt & ~PIIX4_SMBSLVCNT_ALTEN);
479 /* Ask bus who asserted it and then ask it what's the matter. */
481 error = intsmb_free(sc);
485 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, SMBALTRESP | LSB);
486 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 1);
487 error = intsmb_stop_poll(sc);
489 device_printf(sc->dev, "ALART: ERROR\n");
491 addr = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
492 device_printf(sc->dev, "ALART_RESPONSE: 0x%x\n", addr);
495 /* Re-enable INTR from ALART. */
496 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
497 slvcnt | PIIX4_SMBSLVCNT_ALTEN);
503 intsmb_start(struct intsmb_softc *sc, unsigned char cmd, int nointr)
507 INTSMB_LOCK_ASSERT(sc);
508 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
511 tmp |= PIIX4_SMBHSTCNT_START;
513 /* While not in autoconfiguration enable interrupts. */
514 if (!sc->poll && !cold && !nointr)
515 tmp |= PIIX4_SMBHSTCNT_INTREN;
516 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp);
520 intsmb_error(device_t dev, int status)
524 if (status & PIIX4_SMBHSTSTAT_ERR)
525 error |= SMB_EBUSERR;
526 if (status & PIIX4_SMBHSTSTAT_BUSC)
528 if (status & PIIX4_SMBHSTSTAT_FAIL)
531 if (error != 0 && bootverbose)
532 device_printf(dev, "error = %d, status = %#x\n", error, status);
540 * Polling is not encouraged because it requires waiting for the
541 * device if it is busy.
542 * (29063505.pdf from Intel) But during boot, interrupt cannot be used, so use
546 intsmb_stop_poll(struct intsmb_softc *sc)
548 int error, i, status, tmp;
550 INTSMB_LOCK_ASSERT(sc);
552 /* First, wait for busy to be set. */
553 for (i = 0; i < 0x7fff; i++)
554 if (bus_read_1(sc->io_res, PIIX4_SMBHSTSTS) &
555 PIIX4_SMBHSTSTAT_BUSY)
558 /* Wait for busy to clear. */
559 for (i = 0; i < 0x7fff; i++) {
560 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
561 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
563 error = intsmb_error(sc->dev, status);
568 /* Timed out waiting for busy to clear. */
570 tmp = bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
571 bus_write_1(sc->io_res, PIIX4_SMBHSTCNT, tmp & ~PIIX4_SMBHSTCNT_INTREN);
572 return (SMB_ETIMEOUT);
576 * Wait for completion and return result.
579 intsmb_stop(struct intsmb_softc *sc)
583 INTSMB_LOCK_ASSERT(sc);
585 if (sc->poll || cold)
586 /* So that it can use device during device probe on SMBus. */
587 return (intsmb_stop_poll(sc));
589 error = msleep(sc, &sc->lock, PWAIT | PCATCH, "SMBWAI", hz / 8);
591 status = bus_read_1(sc->io_res, PIIX4_SMBHSTSTS);
592 if (!(status & PIIX4_SMBHSTSTAT_BUSY)) {
593 error = intsmb_error(sc->dev, status);
594 if (error == 0 && !(status & PIIX4_SMBHSTSTAT_INTR))
595 device_printf(sc->dev, "unknown cause why?\n");
597 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT,
598 PIIX4_SMBSLVCNT_ALTEN);
604 /* Timeout Procedure. */
607 /* Re-enable supressed interrupt from slave part. */
608 bus_write_1(sc->io_res, PIIX4_SMBSLVCNT, PIIX4_SMBSLVCNT_ALTEN);
609 if (error == EWOULDBLOCK)
610 return (SMB_ETIMEOUT);
616 intsmb_quick(device_t dev, u_char slave, int how)
618 struct intsmb_softc *sc = device_get_softc(dev);
624 /* Quick command is part of Address, I think. */
637 error = intsmb_free(sc);
642 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, data);
643 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_QUICK, 0);
644 error = intsmb_stop(sc);
650 intsmb_sendb(device_t dev, u_char slave, char byte)
652 struct intsmb_softc *sc = device_get_softc(dev);
656 error = intsmb_free(sc);
661 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
662 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, byte);
663 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
664 error = intsmb_stop(sc);
670 intsmb_recvb(device_t dev, u_char slave, char *byte)
672 struct intsmb_softc *sc = device_get_softc(dev);
676 error = intsmb_free(sc);
681 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
682 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BYTE, 0);
683 error = intsmb_stop(sc);
685 #ifdef RECV_IS_IN_CMD
687 * Linux SMBus stuff also troubles
688 * Because Intel's datasheet does not make clear.
690 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTCMD);
692 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
700 intsmb_writeb(device_t dev, u_char slave, char cmd, char byte)
702 struct intsmb_softc *sc = device_get_softc(dev);
706 error = intsmb_free(sc);
711 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
712 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
713 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, byte);
714 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
715 error = intsmb_stop(sc);
721 intsmb_writew(device_t dev, u_char slave, char cmd, short word)
723 struct intsmb_softc *sc = device_get_softc(dev);
727 error = intsmb_free(sc);
732 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
733 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
734 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, word & 0xff);
735 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT1, (word >> 8) & 0xff);
736 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
737 error = intsmb_stop(sc);
743 intsmb_readb(device_t dev, u_char slave, char cmd, char *byte)
745 struct intsmb_softc *sc = device_get_softc(dev);
749 error = intsmb_free(sc);
754 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
755 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
756 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BDATA, 0);
757 error = intsmb_stop(sc);
759 *byte = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
765 intsmb_readw(device_t dev, u_char slave, char cmd, short *word)
767 struct intsmb_softc *sc = device_get_softc(dev);
771 error = intsmb_free(sc);
776 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
777 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
778 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_WDATA, 0);
779 error = intsmb_stop(sc);
781 *word = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
782 *word |= bus_read_1(sc->io_res, PIIX4_SMBHSTDAT1) << 8;
789 intsmb_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata)
792 return (SMB_ENOTSUPP);
796 intsmb_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
798 struct intsmb_softc *sc = device_get_softc(dev);
801 if (count > SMBBLOCKTRANS_MAX || count == 0)
805 error = intsmb_free(sc);
811 /* Reset internal array index. */
812 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
814 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave & ~LSB);
815 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
816 for (i = 0; i < count; i++)
817 bus_write_1(sc->io_res, PIIX4_SMBBLKDAT, buf[i]);
818 bus_write_1(sc->io_res, PIIX4_SMBHSTDAT0, count);
819 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
820 error = intsmb_stop(sc);
826 intsmb_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf)
828 struct intsmb_softc *sc = device_get_softc(dev);
833 error = intsmb_free(sc);
839 /* Reset internal array index. */
840 bus_read_1(sc->io_res, PIIX4_SMBHSTCNT);
842 bus_write_1(sc->io_res, PIIX4_SMBHSTADD, slave | LSB);
843 bus_write_1(sc->io_res, PIIX4_SMBHSTCMD, cmd);
844 intsmb_start(sc, PIIX4_SMBHSTCNT_PROT_BLOCK, 0);
845 error = intsmb_stop(sc);
847 nread = bus_read_1(sc->io_res, PIIX4_SMBHSTDAT0);
848 if (nread != 0 && nread <= SMBBLOCKTRANS_MAX) {
850 for (i = 0; i < nread; i++)
851 data = bus_read_1(sc->io_res, PIIX4_SMBBLKDAT);
859 static devclass_t intsmb_devclass;
861 static device_method_t intsmb_methods[] = {
862 /* Device interface */
863 DEVMETHOD(device_probe, intsmb_probe),
864 DEVMETHOD(device_attach, intsmb_attach),
865 DEVMETHOD(device_detach, intsmb_detach),
867 /* SMBus interface */
868 DEVMETHOD(smbus_callback, intsmb_callback),
869 DEVMETHOD(smbus_quick, intsmb_quick),
870 DEVMETHOD(smbus_sendb, intsmb_sendb),
871 DEVMETHOD(smbus_recvb, intsmb_recvb),
872 DEVMETHOD(smbus_writeb, intsmb_writeb),
873 DEVMETHOD(smbus_writew, intsmb_writew),
874 DEVMETHOD(smbus_readb, intsmb_readb),
875 DEVMETHOD(smbus_readw, intsmb_readw),
876 DEVMETHOD(smbus_pcall, intsmb_pcall),
877 DEVMETHOD(smbus_bwrite, intsmb_bwrite),
878 DEVMETHOD(smbus_bread, intsmb_bread),
883 static driver_t intsmb_driver = {
886 sizeof(struct intsmb_softc),
889 DRIVER_MODULE_ORDERED(intsmb, pci, intsmb_driver, intsmb_devclass, 0, 0,
891 DRIVER_MODULE(smbus, intsmb, smbus_driver, smbus_devclass, 0, 0);
892 MODULE_DEPEND(intsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
893 MODULE_VERSION(intsmb, 1);