2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * Copyright (C) 2001 Benno Rice
33 * All rights reserved.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
49 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include "opt_compat.h"
62 #include "opt_kstack_pages.h"
63 #include "opt_platform.h"
65 #include <sys/param.h>
67 #include <sys/systm.h>
73 #include <sys/eventhandler.h>
75 #include <sys/imgact.h>
77 #include <sys/kernel.h>
79 #include <sys/linker.h>
81 #include <sys/malloc.h>
83 #include <sys/msgbuf.h>
84 #include <sys/mutex.h>
85 #include <sys/ptrace.h>
86 #include <sys/reboot.h>
87 #include <sys/rwlock.h>
88 #include <sys/signalvar.h>
89 #include <sys/syscallsubr.h>
90 #include <sys/sysctl.h>
91 #include <sys/sysent.h>
92 #include <sys/sysproto.h>
93 #include <sys/ucontext.h>
95 #include <sys/vmmeter.h>
96 #include <sys/vnode.h>
98 #include <net/netisr.h>
101 #include <vm/vm_extern.h>
102 #include <vm/vm_kern.h>
103 #include <vm/vm_page.h>
104 #include <vm/vm_map.h>
105 #include <vm/vm_object.h>
106 #include <vm/vm_pager.h>
108 #include <machine/altivec.h>
109 #ifndef __powerpc64__
110 #include <machine/bat.h>
112 #include <machine/cpu.h>
113 #include <machine/elf.h>
114 #include <machine/fpu.h>
115 #include <machine/hid.h>
116 #include <machine/kdb.h>
117 #include <machine/md_var.h>
118 #include <machine/metadata.h>
119 #include <machine/mmuvar.h>
120 #include <machine/pcb.h>
121 #include <machine/reg.h>
122 #include <machine/sigframe.h>
123 #include <machine/spr.h>
124 #include <machine/trap.h>
125 #include <machine/vmparam.h>
126 #include <machine/ofw_machdep.h>
130 #include <dev/ofw/openfirm.h>
133 extern vm_offset_t ksym_start, ksym_end;
139 int cacheline_size = 128;
141 int cacheline_size = 32;
143 int hw_direct_map = 1;
145 extern void *ap_pcpu;
147 struct pcpu __pcpu[MAXCPU];
149 static struct trapframe frame0;
151 char machine[] = "powerpc";
152 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
154 static void cpu_startup(void *);
155 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
157 SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
158 CTLFLAG_RD, &cacheline_size, 0, "");
160 uintptr_t powerpc_init(vm_offset_t, vm_offset_t, vm_offset_t, void *);
162 int setfault(faultbuf); /* defined in locore.S */
167 #ifndef __powerpc64__
168 struct bat battable[16];
171 struct kva_md_info kmi;
174 cpu_startup(void *dummy)
178 * Initialise the decrementer-based clock.
183 * Good {morning,afternoon,evening,night}.
185 cpu_setup(PCPU_GET(cpuid));
190 printf("real memory = %ld (%ld MB)\n", ptoa(physmem),
191 ptoa(physmem) / 1048576);
195 printf("available KVA = %zd (%zd MB)\n",
196 virtual_end - virtual_avail,
197 (virtual_end - virtual_avail) / 1048576);
200 * Display any holes after the first chunk of extended memory.
205 printf("Physical memory chunk(s):\n");
206 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
208 phys_avail[indx + 1] - phys_avail[indx];
211 printf("0x%016lx - 0x%016lx, %ld bytes (%ld pages)\n",
213 printf("0x%08x - 0x%08x, %d bytes (%ld pages)\n",
215 phys_avail[indx], phys_avail[indx + 1] - 1, size1,
220 vm_ksubmap_init(&kmi);
222 printf("avail memory = %ld (%ld MB)\n", ptoa(cnt.v_free_count),
223 ptoa(cnt.v_free_count) / 1048576);
226 * Set up buffers, so they can be used to read disk labels.
229 vm_pager_bufferinit();
232 extern char kernel_text[], _end[];
234 #ifndef __powerpc64__
235 /* Bits for running on 64-bit systems in 32-bit mode. */
236 extern void *testppc64, *testppc64size;
237 extern void *restorebridge, *restorebridgesize;
238 extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
239 extern void *trapcode64;
242 extern void *rstcode, *rstsize;
243 extern void *trapcode, *trapsize;
244 extern void *slbtrap, *slbtrapsize;
245 extern void *alitrap, *alisize;
246 extern void *dsitrap, *dsisize;
247 extern void *decrint, *decrsize;
248 extern void *extint, *extsize;
249 extern void *dblow, *dbsize;
250 extern void *imisstrap, *imisssize;
251 extern void *dlmisstrap, *dlmisssize;
252 extern void *dsmisstrap, *dsmisssize;
253 char save_trap_init[0x2f00]; /* EXC_LAST */
256 powerpc_init(vm_offset_t startkernel, vm_offset_t endkernel,
257 vm_offset_t basekernel, void *mdp)
264 register_t msr, scratch;
268 uint8_t *cache_check;
270 #ifndef __powerpc64__
278 /* Save trap vectors. */
279 ofw_save_trap_vec(save_trap_init);
283 * The Wii loader doesn't pass us any environment so, mdp
284 * points to garbage at this point. The Wii CPU is a 750CL.
287 if ((vers & 0xfffff0e0) == (MPC750 << 16 | MPC750CL))
292 * Parse metadata if present and fetch parameters. Must be done
293 * before console is inited so cninit gets the right value of
297 preload_metadata = mdp;
298 kmdp = preload_search_by_type("elf kernel");
300 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
301 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
302 endkernel = ulmax(endkernel, MD_FETCH(kmdp,
303 MODINFOMD_KERNEND, vm_offset_t));
305 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
306 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
312 * Init params/tunables that can be overridden by the loader
317 * Start initializing proc0 and thread0.
319 proc_linkup0(&proc0, &thread0);
320 thread0.td_frame = &frame0;
323 * Set up per-cpu data.
326 pcpu_init(pc, 0, sizeof(struct pcpu));
327 pc->pc_curthread = &thread0;
329 __asm __volatile("mr 13,%0" :: "r"(pc->pc_curthread));
331 __asm __volatile("mr 2,%0" :: "r"(pc->pc_curthread));
335 __asm __volatile("mtsprg 0, %0" :: "r"(pc));
338 * Init mutexes, which we use heavily in PMAP
344 * Install the OF client interface
350 * Initialize the console before printing anything.
355 * Complain if there is no metadata.
357 if (mdp == NULL || kmdp == NULL) {
358 printf("powerpc_init: no loader metadata.\n");
367 /* Various very early CPU fix ups */
368 switch (mfpvr() >> 16) {
370 * PowerPC 970 CPUs have a misfeature requested by Apple that
371 * makes them pretend they have a 32-byte cacheline. Turn this
372 * off before we measure the cacheline size.
378 scratch = mfspr(SPR_HID5);
379 scratch &= ~HID5_970_DCBZ_SIZE_HI;
380 mtspr(SPR_HID5, scratch);
384 /* XXX: get from ibm,slb-size in device tree */
391 * Initialize the interrupt tables and figure out our cache line
392 * size and whether or not we need the 64-bit bridge code.
396 * Disable translation in case the vector area hasn't been
397 * mapped (G5). Note that no OFW calls can be made until
398 * translation is re-enabled.
402 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI);
405 * Measure the cacheline size using dcbz
407 * Use EXC_PGM as a playground. We are about to overwrite it
408 * anyway, we know it exists, and we know it is cache-aligned.
411 cache_check = (void *)EXC_PGM;
413 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++)
414 cache_check[cacheline_size] = 0xff;
416 __asm __volatile("dcbz 0,%0":: "r" (cache_check) : "memory");
418 /* Find the first byte dcbz did not zero to get the cache line size */
419 for (cacheline_size = 0; cacheline_size < 0x100 &&
420 cache_check[cacheline_size] == 0; cacheline_size++);
422 /* Work around psim bug */
423 if (cacheline_size == 0) {
428 /* Make sure the kernel icache is valid before we go too much further */
429 __syncicache((caddr_t)startkernel, endkernel - startkernel);
431 #ifndef __powerpc64__
433 * Figure out whether we need to use the 64 bit PMAP. This works by
434 * executing an instruction that is only legal on 64-bit PPC (mtmsrd),
435 * and setting ppc64 = 0 if that causes a trap.
440 bcopy(&testppc64, (void *)EXC_PGM, (size_t)&testppc64size);
441 __syncicache((void *)EXC_PGM, (size_t)&testppc64size);
449 : "=r"(scratch), "=r"(ppc64));
452 cpu_features |= PPC_FEATURE_64;
455 * Now copy restorebridge into all the handlers, if necessary,
456 * and set up the trap tables.
459 if (cpu_features & PPC_FEATURE_64) {
460 /* Patch the two instances of rfi -> rfid */
461 bcopy(&rfid_patch,&rfi_patch1,4);
463 /* rfi_patch2 is at the end of dbleave */
464 bcopy(&rfid_patch,&rfi_patch2,4);
468 * Copy a code snippet to restore 32-bit bridge mode
469 * to the top of every non-generic trap handler
472 trap_offset += (size_t)&restorebridgesize;
473 bcopy(&restorebridge, (void *)EXC_RST, trap_offset);
474 bcopy(&restorebridge, (void *)EXC_DSI, trap_offset);
475 bcopy(&restorebridge, (void *)EXC_ALI, trap_offset);
476 bcopy(&restorebridge, (void *)EXC_PGM, trap_offset);
477 bcopy(&restorebridge, (void *)EXC_MCHK, trap_offset);
478 bcopy(&restorebridge, (void *)EXC_TRC, trap_offset);
479 bcopy(&restorebridge, (void *)EXC_BPT, trap_offset);
482 * Set the common trap entry point to the one that
483 * knows to restore 32-bit operation on execution.
486 generictrap = &trapcode64;
488 generictrap = &trapcode;
491 #else /* powerpc64 */
492 cpu_features |= PPC_FEATURE_64;
493 generictrap = &trapcode;
496 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstsize);
499 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbsize);
500 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbsize);
501 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbsize);
502 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbsize);
504 bcopy(generictrap, (void *)EXC_MCHK, (size_t)&trapsize);
505 bcopy(generictrap, (void *)EXC_PGM, (size_t)&trapsize);
506 bcopy(generictrap, (void *)EXC_TRC, (size_t)&trapsize);
507 bcopy(generictrap, (void *)EXC_BPT, (size_t)&trapsize);
509 bcopy(&alitrap, (void *)(EXC_ALI + trap_offset), (size_t)&alisize);
510 bcopy(&dsitrap, (void *)(EXC_DSI + trap_offset), (size_t)&dsisize);
511 bcopy(generictrap, (void *)EXC_ISI, (size_t)&trapsize);
513 bcopy(&slbtrap, (void *)EXC_DSE, (size_t)&slbtrapsize);
514 bcopy(&slbtrap, (void *)EXC_ISE, (size_t)&slbtrapsize);
516 bcopy(generictrap, (void *)EXC_EXI, (size_t)&trapsize);
517 bcopy(generictrap, (void *)EXC_FPU, (size_t)&trapsize);
518 bcopy(generictrap, (void *)EXC_DECR, (size_t)&trapsize);
519 bcopy(generictrap, (void *)EXC_SC, (size_t)&trapsize);
520 bcopy(generictrap, (void *)EXC_FPA, (size_t)&trapsize);
521 bcopy(generictrap, (void *)EXC_VEC, (size_t)&trapsize);
522 bcopy(generictrap, (void *)EXC_PERF, (size_t)&trapsize);
523 bcopy(generictrap, (void *)EXC_VECAST_G4, (size_t)&trapsize);
524 bcopy(generictrap, (void *)EXC_VECAST_G5, (size_t)&trapsize);
525 #ifndef __powerpc64__
526 /* G2-specific TLB miss helper handlers */
527 bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
528 bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
529 bcopy(&dsmisstrap, (void *)EXC_DSMISS, (size_t)&dsmisssize);
531 __syncicache(EXC_RSVD, EXC_LAST - EXC_RSVD);
538 /* Warn if cachline size was not determined */
539 if (cacheline_warn == 1) {
540 printf("WARNING: cacheline size undetermined, setting to 32\n");
544 * Choose a platform module so we can get the physical memory map.
547 platform_probe_and_attach();
550 * Initialise virtual memory. Use BUS_PROBE_GENERIC priority
551 * in case the platform module had a better idea of what we
554 if (cpu_features & PPC_FEATURE_64)
555 pmap_mmu_install(MMU_TYPE_G5, BUS_PROBE_GENERIC);
557 pmap_mmu_install(MMU_TYPE_OEA, BUS_PROBE_GENERIC);
559 pmap_bootstrap(startkernel, endkernel);
560 mtmsr(PSL_KERNSET & ~PSL_EE);
563 * Initialize params/tunables that are derived from memsize
565 init_param2(physmem);
568 * Grab booted kernel's name
570 env = getenv("kernelname");
572 strlcpy(kernelname, env, sizeof(kernelname));
577 * Finish setting up thread0.
579 thread0.td_pcb = (struct pcb *)
580 ((thread0.td_kstack + thread0.td_kstack_pages * PAGE_SIZE -
581 sizeof(struct pcb)) & ~15UL);
582 bzero((void *)thread0.td_pcb, sizeof(struct pcb));
583 pc->pc_curpcb = thread0.td_pcb;
585 /* Initialise the message buffer. */
586 msgbufinit(msgbufp, msgbufsize);
589 if (boothowto & RB_KDB)
590 kdb_enter(KDB_WHY_BOOTFLAGS,
591 "Boot flags requested debugger");
594 return (((uintptr_t)thread0.td_pcb -
595 (sizeof(struct callframe) - 3*sizeof(register_t))) & ~15UL);
599 bzero(void *buf, size_t len)
605 while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) {
610 while (len >= sizeof(u_long) * 8) {
612 *((u_long*) p + 1) = 0;
613 *((u_long*) p + 2) = 0;
614 *((u_long*) p + 3) = 0;
615 len -= sizeof(u_long) * 8;
616 *((u_long*) p + 4) = 0;
617 *((u_long*) p + 5) = 0;
618 *((u_long*) p + 6) = 0;
619 *((u_long*) p + 7) = 0;
620 p += sizeof(u_long) * 8;
623 while (len >= sizeof(u_long)) {
625 len -= sizeof(u_long);
641 * Flush the D-cache for non-DMA I/O so that the I-cache can
642 * be made coherent later.
645 cpu_flush_dcache(void *ptr, size_t len)
651 * Shutdown the CPU as much as possible.
661 ptrace_set_pc(struct thread *td, unsigned long addr)
663 struct trapframe *tf;
666 tf->srr0 = (register_t)addr;
672 ptrace_single_step(struct thread *td)
674 struct trapframe *tf;
683 ptrace_clear_single_step(struct thread *td)
685 struct trapframe *tf;
694 kdb_cpu_clear_singlestep(void)
697 kdb_frame->srr1 &= ~PSL_SE;
701 kdb_cpu_set_singlestep(void)
704 kdb_frame->srr1 |= PSL_SE;
708 * Initialise a struct pcpu.
711 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
714 /* Copy the SLB contents from the current CPU */
715 memcpy(pcpu->pc_slb, PCPU_GET(slb), sizeof(pcpu->pc_slb));
726 if (td->td_md.md_spinlock_count == 0) {
727 msr = intr_disable();
728 td->td_md.md_spinlock_count = 1;
729 td->td_md.md_saved_msr = msr;
731 td->td_md.md_spinlock_count++;
743 msr = td->td_md.md_saved_msr;
744 td->td_md.md_spinlock_count--;
745 if (td->td_md.md_spinlock_count == 0)
749 int db_trap_glue(struct trapframe *); /* Called from trap_subr.S */
752 db_trap_glue(struct trapframe *frame)
754 if (!(frame->srr1 & PSL_PR)
755 && (frame->exc == EXC_TRC || frame->exc == EXC_RUNMODETRC
756 || (frame->exc == EXC_PGM
757 && (frame->srr1 & 0x20000))
758 || frame->exc == EXC_BPT
759 || frame->exc == EXC_DSI)) {
760 int type = frame->exc;
761 if (type == EXC_PGM && (frame->srr1 & 0x20000)) {
764 return (kdb_trap(type, 0, frame));
770 #ifndef __powerpc64__
773 va_to_vsid(pmap_t pm, vm_offset_t va)
775 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
781 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
787 /* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
789 flush_disable_caches(void)
793 register_t cache_reg;
794 volatile uint32_t *memp;
801 mtmsr(msr & ~(PSL_EE | PSL_DR));
802 msscr0 = mfspr(SPR_MSSCR0);
803 msscr0 &= ~MSSCR0_L2PFE;
804 mtspr(SPR_MSSCR0, msscr0);
807 __asm__ __volatile__("dssall; sync");
810 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
811 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
812 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
814 /* Lock the L1 Data cache. */
815 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
819 mtspr(SPR_LDSTCR, 0);
822 * Perform this in two stages: Flush the cache starting in RAM, then do it
825 memp = (volatile uint32_t *)0x00000000;
826 for (i = 0; i < 128 * 1024; i++) {
828 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
829 memp += 32/sizeof(*memp);
832 memp = (volatile uint32_t *)0xfff00000;
836 mtspr(SPR_LDSTCR, x);
837 for (i = 0; i < 128; i++) {
839 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
840 memp += 32/sizeof(*memp);
842 x = ((x << 1) | 1) & 0xff;
844 mtspr(SPR_LDSTCR, 0);
846 cache_reg = mfspr(SPR_L2CR);
847 if (cache_reg & L2CR_L2E) {
848 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
849 mtspr(SPR_L2CR, cache_reg);
851 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
852 while (mfspr(SPR_L2CR) & L2CR_L2HWF)
853 ; /* Busy wait for cache to flush */
855 cache_reg &= ~L2CR_L2E;
856 mtspr(SPR_L2CR, cache_reg);
858 mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
860 while (mfspr(SPR_L2CR) & L2CR_L2I)
861 ; /* Busy wait for L2 cache invalidate */
865 cache_reg = mfspr(SPR_L3CR);
866 if (cache_reg & L3CR_L3E) {
867 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
868 mtspr(SPR_L3CR, cache_reg);
870 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
871 while (mfspr(SPR_L3CR) & L3CR_L3HWF)
872 ; /* Busy wait for cache to flush */
874 cache_reg &= ~L3CR_L3E;
875 mtspr(SPR_L3CR, cache_reg);
877 mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
879 while (mfspr(SPR_L3CR) & L3CR_L3I)
880 ; /* Busy wait for L3 cache invalidate */
884 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
894 static u_quad_t timebase = 0;
895 static register_t sprgs[4];
896 static register_t srrs[2];
899 struct thread *fputd;
900 struct thread *vectd;
903 register_t saved_msr;
907 PCPU_SET(restore, &resetjb);
910 fputd = PCPU_GET(fputhread);
911 vectd = PCPU_GET(vecthread);
916 if (setjmp(resetjb) == 0) {
917 sprgs[0] = mfspr(SPR_SPRG0);
918 sprgs[1] = mfspr(SPR_SPRG1);
919 sprgs[2] = mfspr(SPR_SPRG2);
920 sprgs[3] = mfspr(SPR_SPRG3);
921 srrs[0] = mfspr(SPR_SRR0);
922 srrs[1] = mfspr(SPR_SRR1);
925 flush_disable_caches();
926 hid0 = mfspr(SPR_HID0);
927 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
930 msr = mfmsr() | PSL_POW;
931 mtspr(SPR_HID0, hid0);
938 PCPU_SET(curthread, curthread);
939 PCPU_SET(curpcb, curthread->td_pcb);
940 pmap_activate(curthread);
942 mtspr(SPR_SPRG0, sprgs[0]);
943 mtspr(SPR_SPRG1, sprgs[1]);
944 mtspr(SPR_SPRG2, sprgs[2]);
945 mtspr(SPR_SPRG3, sprgs[3]);
946 mtspr(SPR_SRR0, srrs[0]);
947 mtspr(SPR_SRR1, srrs[1]);
949 if (fputd == curthread)
950 enable_fpu(curthread);
951 if (vectd == curthread)
952 enable_vec(curthread);