2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
31 * Copyright (C) 1995, 1996 TooLs GmbH.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by TooLs GmbH.
45 * 4. The name of TooLs GmbH may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62 * Copyright (C) 2001 Benno Rice.
63 * All rights reserved.
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * In addition to hardware address maps, this module is called upon to
93 * provide software-use-only maps which may or may not be stored in the
94 * same form as hardware maps. These pseudo-maps are used to store
95 * intermediate results from copy operations to and from address spaces.
97 * Since the information managed by this module is also stored by the
98 * logical address mapping module, this module may throw away valid virtual
99 * to physical mappings at almost any time. However, invalidations of
100 * mappings must be done as requested.
102 * In order to cope with hardware architectures which make virtual to
103 * physical map invalidates expensive, this module may delay invalidate
104 * reduced protection operations until such time as they are actually
105 * necessary. This module is given full information as to which processors
106 * are currently using which maps, and to when physical maps must be made
110 #include "opt_kstack_pages.h"
112 #include <sys/param.h>
113 #include <sys/kernel.h>
114 #include <sys/queue.h>
115 #include <sys/cpuset.h>
117 #include <sys/lock.h>
118 #include <sys/msgbuf.h>
119 #include <sys/mutex.h>
120 #include <sys/proc.h>
121 #include <sys/sched.h>
122 #include <sys/sysctl.h>
123 #include <sys/systm.h>
124 #include <sys/vmmeter.h>
126 #include <dev/ofw/openfirm.h>
129 #include <vm/vm_param.h>
130 #include <vm/vm_kern.h>
131 #include <vm/vm_page.h>
132 #include <vm/vm_map.h>
133 #include <vm/vm_object.h>
134 #include <vm/vm_extern.h>
135 #include <vm/vm_pageout.h>
136 #include <vm/vm_pager.h>
139 #include <machine/cpu.h>
140 #include <machine/platform.h>
141 #include <machine/bat.h>
142 #include <machine/frame.h>
143 #include <machine/md_var.h>
144 #include <machine/psl.h>
145 #include <machine/pte.h>
146 #include <machine/smp.h>
147 #include <machine/sr.h>
148 #include <machine/mmuvar.h>
154 #define TODO panic("%s: not implemented", __func__);
156 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
157 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
158 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
167 extern unsigned char _etext[];
168 extern unsigned char _end[];
170 extern int dumpsys_minidump;
173 * Map of physical memory regions.
175 static struct mem_region *regions;
176 static struct mem_region *pregions;
177 static u_int phys_avail_count;
178 static int regions_sz, pregions_sz;
179 static struct ofw_map *translations;
182 * Lock for the pteg and pvo tables.
184 struct mtx moea_table_mutex;
185 struct mtx moea_vsid_mutex;
187 /* tlbie instruction synchronization */
188 static struct mtx tlbie_mtx;
193 static struct pteg *moea_pteg_table;
194 u_int moea_pteg_count;
195 u_int moea_pteg_mask;
200 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
201 struct pvo_head moea_pvo_kunmanaged =
202 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
204 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
205 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
207 #define BPVO_POOL_SIZE 32768
208 static struct pvo_entry *moea_bpvo_pool;
209 static int moea_bpvo_pool_index = 0;
211 #define VSID_NBPW (sizeof(u_int32_t) * 8)
212 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
214 static boolean_t moea_initialized = FALSE;
219 u_int moea_pte_valid = 0;
220 u_int moea_pte_overflow = 0;
221 u_int moea_pte_replacements = 0;
222 u_int moea_pvo_entries = 0;
223 u_int moea_pvo_enter_calls = 0;
224 u_int moea_pvo_remove_calls = 0;
225 u_int moea_pte_spills = 0;
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
229 &moea_pte_overflow, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
231 &moea_pte_replacements, 0, "");
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
235 &moea_pvo_enter_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
237 &moea_pvo_remove_calls, 0, "");
238 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
239 &moea_pte_spills, 0, "");
242 * Allocate physical memory for use in moea_bootstrap.
244 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
249 static int moea_pte_insert(u_int, struct pte *);
254 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
255 vm_offset_t, vm_offset_t, u_int, int);
256 static void moea_pvo_remove(struct pvo_entry *, int);
257 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
258 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
263 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
264 vm_prot_t, boolean_t);
265 static void moea_syncicache(vm_offset_t, vm_size_t);
266 static boolean_t moea_query_bit(vm_page_t, int);
267 static u_int moea_clear_bit(vm_page_t, int);
268 static void moea_kremove(mmu_t, vm_offset_t);
269 int moea_pte_spill(vm_offset_t);
272 * Kernel MMU interface
274 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
275 void moea_clear_modify(mmu_t, vm_page_t);
276 void moea_clear_reference(mmu_t, vm_page_t);
277 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
278 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
279 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
280 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
281 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
283 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
284 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
285 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
286 void moea_init(mmu_t);
287 boolean_t moea_is_modified(mmu_t, vm_page_t);
288 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
289 boolean_t moea_is_referenced(mmu_t, vm_page_t);
290 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
291 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
292 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
293 int moea_page_wired_mappings(mmu_t, vm_page_t);
294 void moea_pinit(mmu_t, pmap_t);
295 void moea_pinit0(mmu_t, pmap_t);
296 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
297 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
298 void moea_qremove(mmu_t, vm_offset_t, int);
299 void moea_release(mmu_t, pmap_t);
300 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_remove_all(mmu_t, vm_page_t);
302 void moea_remove_write(mmu_t, vm_page_t);
303 void moea_zero_page(mmu_t, vm_page_t);
304 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
305 void moea_zero_page_idle(mmu_t, vm_page_t);
306 void moea_activate(mmu_t, struct thread *);
307 void moea_deactivate(mmu_t, struct thread *);
308 void moea_cpu_bootstrap(mmu_t, int);
309 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
310 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
311 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
312 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
313 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
314 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
315 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
316 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
317 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
318 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
319 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
321 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev);
323 static mmu_method_t moea_methods[] = {
324 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
325 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
326 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
327 MMUMETHOD(mmu_copy_page, moea_copy_page),
328 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
329 MMUMETHOD(mmu_enter, moea_enter),
330 MMUMETHOD(mmu_enter_object, moea_enter_object),
331 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
332 MMUMETHOD(mmu_extract, moea_extract),
333 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
334 MMUMETHOD(mmu_init, moea_init),
335 MMUMETHOD(mmu_is_modified, moea_is_modified),
336 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
337 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
338 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
339 MMUMETHOD(mmu_map, moea_map),
340 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
341 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
342 MMUMETHOD(mmu_pinit, moea_pinit),
343 MMUMETHOD(mmu_pinit0, moea_pinit0),
344 MMUMETHOD(mmu_protect, moea_protect),
345 MMUMETHOD(mmu_qenter, moea_qenter),
346 MMUMETHOD(mmu_qremove, moea_qremove),
347 MMUMETHOD(mmu_release, moea_release),
348 MMUMETHOD(mmu_remove, moea_remove),
349 MMUMETHOD(mmu_remove_all, moea_remove_all),
350 MMUMETHOD(mmu_remove_write, moea_remove_write),
351 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
352 MMUMETHOD(mmu_zero_page, moea_zero_page),
353 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
354 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
355 MMUMETHOD(mmu_activate, moea_activate),
356 MMUMETHOD(mmu_deactivate, moea_deactivate),
357 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
359 /* Internal interfaces */
360 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
361 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
362 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
363 MMUMETHOD(mmu_mapdev, moea_mapdev),
364 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
365 MMUMETHOD(mmu_kextract, moea_kextract),
366 MMUMETHOD(mmu_kenter, moea_kenter),
367 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
368 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
369 MMUMETHOD(mmu_scan_md, moea_scan_md),
370 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
375 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
377 static __inline uint32_t
378 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
383 if (ma != VM_MEMATTR_DEFAULT) {
385 case VM_MEMATTR_UNCACHEABLE:
386 return (PTE_I | PTE_G);
387 case VM_MEMATTR_WRITE_COMBINING:
388 case VM_MEMATTR_WRITE_BACK:
389 case VM_MEMATTR_PREFETCHABLE:
391 case VM_MEMATTR_WRITE_THROUGH:
392 return (PTE_W | PTE_M);
397 * Assume the page is cache inhibited and access is guarded unless
398 * it's in our available memory array.
400 pte_lo = PTE_I | PTE_G;
401 for (i = 0; i < pregions_sz; i++) {
402 if ((pa >= pregions[i].mr_start) &&
403 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
413 tlbie(vm_offset_t va)
416 mtx_lock_spin(&tlbie_mtx);
417 __asm __volatile("ptesync");
418 __asm __volatile("tlbie %0" :: "r"(va));
419 __asm __volatile("eieio; tlbsync; ptesync");
420 mtx_unlock_spin(&tlbie_mtx);
428 for (va = 0; va < 0x00040000; va += 0x00001000) {
429 __asm __volatile("tlbie %0" :: "r"(va));
432 __asm __volatile("tlbsync");
437 va_to_sr(u_int *sr, vm_offset_t va)
439 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
442 static __inline u_int
443 va_to_pteg(u_int sr, vm_offset_t addr)
447 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
449 return (hash & moea_pteg_mask);
452 static __inline struct pvo_head *
453 vm_page_to_pvoh(vm_page_t m)
456 return (&m->md.mdpg_pvoh);
460 moea_attr_clear(vm_page_t m, int ptebit)
463 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
464 m->md.mdpg_attrs &= ~ptebit;
468 moea_attr_fetch(vm_page_t m)
471 return (m->md.mdpg_attrs);
475 moea_attr_save(vm_page_t m, int ptebit)
478 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
479 m->md.mdpg_attrs |= ptebit;
483 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
485 if (pt->pte_hi == pvo_pt->pte_hi)
492 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
494 return (pt->pte_hi & ~PTE_VALID) ==
495 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
496 ((va >> ADDR_API_SHFT) & PTE_API) | which);
500 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
503 mtx_assert(&moea_table_mutex, MA_OWNED);
506 * Construct a PTE. Default to IMB initially. Valid bit only gets
507 * set when the real pte is set in memory.
509 * Note: Don't set the valid bit for correct operation of tlb update.
511 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
512 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
517 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
520 mtx_assert(&moea_table_mutex, MA_OWNED);
521 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
525 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
528 mtx_assert(&moea_table_mutex, MA_OWNED);
531 * As shown in Section 7.6.3.2.3
533 pt->pte_lo &= ~ptebit;
538 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
541 mtx_assert(&moea_table_mutex, MA_OWNED);
542 pvo_pt->pte_hi |= PTE_VALID;
545 * Update the PTE as defined in section 7.6.3.1.
546 * Note that the REF/CHG bits are from pvo_pt and thus should havce
547 * been saved so this routine can restore them (if desired).
549 pt->pte_lo = pvo_pt->pte_lo;
551 pt->pte_hi = pvo_pt->pte_hi;
557 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
560 mtx_assert(&moea_table_mutex, MA_OWNED);
561 pvo_pt->pte_hi &= ~PTE_VALID;
564 * Force the reg & chg bits back into the PTEs.
569 * Invalidate the pte.
571 pt->pte_hi &= ~PTE_VALID;
576 * Save the reg & chg bits.
578 moea_pte_synch(pt, pvo_pt);
583 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
589 moea_pte_unset(pt, pvo_pt, va);
590 moea_pte_set(pt, pvo_pt);
594 * Quick sort callout for comparing memory regions.
596 static int om_cmp(const void *a, const void *b);
599 om_cmp(const void *a, const void *b)
601 const struct ofw_map *mapa;
602 const struct ofw_map *mapb;
606 if (mapa->om_pa < mapb->om_pa)
608 else if (mapa->om_pa > mapb->om_pa)
615 moea_cpu_bootstrap(mmu_t mmup, int ap)
622 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
623 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
625 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
626 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
630 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
631 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
634 __asm __volatile("mtibatu 1,%0" :: "r"(0));
635 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
636 __asm __volatile("mtibatu 2,%0" :: "r"(0));
637 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
638 __asm __volatile("mtibatu 3,%0" :: "r"(0));
641 for (i = 0; i < 16; i++)
642 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
645 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
646 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
653 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
656 phandle_t chosen, mmu;
659 vm_size_t size, physsz, hwphyssz;
660 vm_offset_t pa, va, off;
665 * Set up BAT0 to map the lowest 256 MB area
667 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
668 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
671 * Map PCI memory space.
673 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
674 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
676 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
677 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
679 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
680 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
682 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
683 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
688 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
689 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
692 * Use an IBAT and a DBAT to map the bottom segment of memory
693 * where we are. Turn off instruction relocation temporarily
694 * to prevent faults while reprogramming the IBAT.
697 mtmsr(msr & ~PSL_IR);
698 __asm (".balign 32; \n"
699 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
700 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
701 :: "r"(battable[0].batu), "r"(battable[0].batl));
705 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
706 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
709 /* set global direct map flag */
712 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
713 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
715 for (i = 0; i < pregions_sz; i++) {
719 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
720 pregions[i].mr_start,
721 pregions[i].mr_start + pregions[i].mr_size,
722 pregions[i].mr_size);
724 * Install entries into the BAT table to allow all
725 * of physmem to be convered by on-demand BAT entries.
726 * The loop will sometimes set the same battable element
727 * twice, but that's fine since they won't be used for
730 pa = pregions[i].mr_start & 0xf0000000;
731 end = pregions[i].mr_start + pregions[i].mr_size;
733 u_int n = pa >> ADDR_SR_SHFT;
735 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
736 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
737 pa += SEGMENT_LENGTH;
741 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
742 panic("moea_bootstrap: phys_avail too small");
744 phys_avail_count = 0;
747 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
748 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
749 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
750 regions[i].mr_start + regions[i].mr_size,
753 (physsz + regions[i].mr_size) >= hwphyssz) {
754 if (physsz < hwphyssz) {
755 phys_avail[j] = regions[i].mr_start;
756 phys_avail[j + 1] = regions[i].mr_start +
763 phys_avail[j] = regions[i].mr_start;
764 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
766 physsz += regions[i].mr_size;
768 physmem = btoc(physsz);
771 * Allocate PTEG table.
774 moea_pteg_count = PTEGCOUNT;
776 moea_pteg_count = 0x1000;
778 while (moea_pteg_count < physmem)
779 moea_pteg_count <<= 1;
781 moea_pteg_count >>= 1;
782 #endif /* PTEGCOUNT */
784 size = moea_pteg_count * sizeof(struct pteg);
785 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
787 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
788 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
789 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
790 moea_pteg_mask = moea_pteg_count - 1;
793 * Allocate pv/overflow lists.
795 size = sizeof(struct pvo_head) * moea_pteg_count;
796 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
798 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
799 for (i = 0; i < moea_pteg_count; i++)
800 LIST_INIT(&moea_pvo_table[i]);
803 * Initialize the lock that synchronizes access to the pteg and pvo
806 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
808 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
810 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
813 * Initialise the unmanaged pvo pool.
815 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
816 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
817 moea_bpvo_pool_index = 0;
820 * Make sure kernel vsid is allocated as well as VSID 0.
822 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
823 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
824 moea_vsid_bitmap[0] |= 1;
827 * Initialize the kernel pmap (which is statically allocated).
829 PMAP_LOCK_INIT(kernel_pmap);
830 for (i = 0; i < 16; i++)
831 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
832 CPU_FILL(&kernel_pmap->pm_active);
833 LIST_INIT(&kernel_pmap->pmap_pvo);
836 * Set up the Open Firmware mappings
838 if ((chosen = OF_finddevice("/chosen")) == -1)
839 panic("moea_bootstrap: can't find /chosen");
840 OF_getprop(chosen, "mmu", &mmui, 4);
841 if ((mmu = OF_instance_to_package(mmui)) == -1)
842 panic("moea_bootstrap: can't get mmu package");
843 if ((sz = OF_getproplen(mmu, "translations")) == -1)
844 panic("moea_bootstrap: can't get ofw translation count");
846 for (i = 0; phys_avail[i] != 0; i += 2) {
847 if (phys_avail[i + 1] >= sz) {
848 translations = (struct ofw_map *)phys_avail[i];
852 if (translations == NULL)
853 panic("moea_bootstrap: no space to copy translations");
854 bzero(translations, sz);
855 if (OF_getprop(mmu, "translations", translations, sz) == -1)
856 panic("moea_bootstrap: can't get ofw translations");
857 CTR0(KTR_PMAP, "moea_bootstrap: translations");
858 sz /= sizeof(*translations);
859 qsort(translations, sz, sizeof (*translations), om_cmp);
860 for (i = 0; i < sz; i++) {
861 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
862 translations[i].om_pa, translations[i].om_va,
863 translations[i].om_len);
866 * If the mapping is 1:1, let the RAM and device on-demand
867 * BAT tables take care of the translation.
869 if (translations[i].om_va == translations[i].om_pa)
872 /* Enter the pages */
873 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE)
874 moea_kenter(mmup, translations[i].om_va + off,
875 translations[i].om_pa + off);
879 * Calculate the last available physical address.
881 for (i = 0; phys_avail[i + 2] != 0; i += 2)
883 Maxmem = powerpc_btop(phys_avail[i + 1]);
885 moea_cpu_bootstrap(mmup,0);
890 * Set the start and end of kva.
892 virtual_avail = VM_MIN_KERNEL_ADDRESS;
893 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
896 * Allocate a kernel stack with a guard page for thread0 and map it
897 * into the kernel page map.
899 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
900 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
901 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
902 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
903 thread0.td_kstack = va;
904 thread0.td_kstack_pages = KSTACK_PAGES;
905 for (i = 0; i < KSTACK_PAGES; i++) {
906 moea_kenter(mmup, va, pa);
912 * Allocate virtual address space for the message buffer.
914 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
915 msgbufp = (struct msgbuf *)virtual_avail;
917 virtual_avail += round_page(msgbufsize);
918 while (va < virtual_avail) {
919 moea_kenter(mmup, va, pa);
925 * Allocate virtual address space for the dynamic percpu area.
927 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
928 dpcpu = (void *)virtual_avail;
930 virtual_avail += DPCPU_SIZE;
931 while (va < virtual_avail) {
932 moea_kenter(mmup, va, pa);
936 dpcpu_init(dpcpu, 0);
940 * Activate a user pmap. The pmap must be activated before it's address
941 * space can be accessed in any way.
944 moea_activate(mmu_t mmu, struct thread *td)
949 * Load all the data we need up front to encourage the compiler to
950 * not issue any loads while we have interrupts disabled below.
952 pm = &td->td_proc->p_vmspace->vm_pmap;
955 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
956 PCPU_SET(curpmap, pmr);
960 moea_deactivate(mmu_t mmu, struct thread *td)
964 pm = &td->td_proc->p_vmspace->vm_pmap;
965 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
966 PCPU_SET(curpmap, NULL);
970 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
972 struct pvo_entry *pvo;
975 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
979 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
980 pm->pm_stats.wired_count++;
981 pvo->pvo_vaddr |= PVO_WIRED;
983 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
984 pm->pm_stats.wired_count--;
985 pvo->pvo_vaddr &= ~PVO_WIRED;
992 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
997 dst = VM_PAGE_TO_PHYS(mdst);
998 src = VM_PAGE_TO_PHYS(msrc);
1000 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1004 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1005 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1008 vm_offset_t a_pg_offset, b_pg_offset;
1011 while (xfersize > 0) {
1012 a_pg_offset = a_offset & PAGE_MASK;
1013 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1014 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1016 b_pg_offset = b_offset & PAGE_MASK;
1017 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1018 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1020 bcopy(a_cp, b_cp, cnt);
1028 * Zero a page of physical memory by temporarily mapping it into the tlb.
1031 moea_zero_page(mmu_t mmu, vm_page_t m)
1033 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1034 void *va = (void *)pa;
1036 bzero(va, PAGE_SIZE);
1040 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1042 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1043 void *va = (void *)(pa + off);
1049 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1051 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1052 void *va = (void *)pa;
1054 bzero(va, PAGE_SIZE);
1058 * Map the given physical page at the specified virtual address in the
1059 * target pmap with the protection requested. If specified the page
1060 * will be wired down.
1063 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1067 vm_page_lock_queues();
1069 moea_enter_locked(pmap, va, m, prot, wired);
1070 vm_page_unlock_queues();
1075 * Map the given physical page at the specified virtual address in the
1076 * target pmap with the protection requested. If specified the page
1077 * will be wired down.
1079 * The page queues and pmap must be locked.
1082 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1085 struct pvo_head *pvo_head;
1088 u_int pte_lo, pvo_flags;
1091 if (!moea_initialized) {
1092 pvo_head = &moea_pvo_kunmanaged;
1093 zone = moea_upvo_zone;
1097 pvo_head = vm_page_to_pvoh(m);
1099 zone = moea_mpvo_zone;
1100 pvo_flags = PVO_MANAGED;
1102 if (pmap_bootstrapped)
1103 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1104 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1105 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0 ||
1106 VM_OBJECT_LOCKED(m->object),
1107 ("moea_enter_locked: page %p is not busy", m));
1109 /* XXX change the pvo head for fake pages */
1110 if ((m->oflags & VPO_UNMANAGED) != 0) {
1111 pvo_flags &= ~PVO_MANAGED;
1112 pvo_head = &moea_pvo_kunmanaged;
1113 zone = moea_upvo_zone;
1116 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1118 if (prot & VM_PROT_WRITE) {
1120 if (pmap_bootstrapped &&
1121 (m->oflags & VPO_UNMANAGED) == 0)
1122 vm_page_aflag_set(m, PGA_WRITEABLE);
1126 if (prot & VM_PROT_EXECUTE)
1127 pvo_flags |= PVO_EXECUTABLE;
1130 pvo_flags |= PVO_WIRED;
1132 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1136 * Flush the real page from the instruction cache. This has be done
1137 * for all user mappings to prevent information leakage via the
1138 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1139 * mapping for a page.
1141 if (pmap != kernel_pmap && error == ENOENT &&
1142 (pte_lo & (PTE_I | PTE_G)) == 0)
1143 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1147 * Maps a sequence of resident pages belonging to the same object.
1148 * The sequence begins with the given page m_start. This page is
1149 * mapped at the given virtual address start. Each subsequent page is
1150 * mapped at a virtual address that is offset from start by the same
1151 * amount as the page is offset from m_start within the object. The
1152 * last page in the sequence is the page with the largest offset from
1153 * m_start that can be mapped at a virtual address less than the given
1154 * virtual address end. Not every virtual page between start and end
1155 * is mapped; only those for which a resident page exists with the
1156 * corresponding offset from m_start are mapped.
1159 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1160 vm_page_t m_start, vm_prot_t prot)
1163 vm_pindex_t diff, psize;
1165 psize = atop(end - start);
1167 vm_page_lock_queues();
1169 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1170 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1171 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1172 m = TAILQ_NEXT(m, listq);
1174 vm_page_unlock_queues();
1179 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1183 vm_page_lock_queues();
1185 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1187 vm_page_unlock_queues();
1192 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1194 struct pvo_entry *pvo;
1198 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1202 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1208 * Atomically extract and hold the physical page with the given
1209 * pmap and virtual address pair if that mapping permits the given
1213 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1215 struct pvo_entry *pvo;
1223 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1224 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1225 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1226 (prot & VM_PROT_WRITE) == 0)) {
1227 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1229 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1238 moea_init(mmu_t mmu)
1241 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1242 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1243 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1244 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1245 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1246 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1247 moea_initialized = TRUE;
1251 moea_is_referenced(mmu_t mmu, vm_page_t m)
1254 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1255 ("moea_is_referenced: page %p is not managed", m));
1256 return (moea_query_bit(m, PTE_REF));
1260 moea_is_modified(mmu_t mmu, vm_page_t m)
1263 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1264 ("moea_is_modified: page %p is not managed", m));
1267 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
1268 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1269 * is clear, no PTEs can have PTE_CHG set.
1271 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1272 if ((m->oflags & VPO_BUSY) == 0 &&
1273 (m->aflags & PGA_WRITEABLE) == 0)
1275 return (moea_query_bit(m, PTE_CHG));
1279 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1281 struct pvo_entry *pvo;
1285 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1286 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1292 moea_clear_reference(mmu_t mmu, vm_page_t m)
1295 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1296 ("moea_clear_reference: page %p is not managed", m));
1297 moea_clear_bit(m, PTE_REF);
1301 moea_clear_modify(mmu_t mmu, vm_page_t m)
1304 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1305 ("moea_clear_modify: page %p is not managed", m));
1306 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1307 KASSERT((m->oflags & VPO_BUSY) == 0,
1308 ("moea_clear_modify: page %p is busy", m));
1311 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1312 * set. If the object containing the page is locked and the page is
1313 * not VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
1315 if ((m->aflags & PGA_WRITEABLE) == 0)
1317 moea_clear_bit(m, PTE_CHG);
1321 * Clear the write and modified bits in each of the given page's mappings.
1324 moea_remove_write(mmu_t mmu, vm_page_t m)
1326 struct pvo_entry *pvo;
1331 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1332 ("moea_remove_write: page %p is not managed", m));
1335 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
1336 * another thread while the object is locked. Thus, if PGA_WRITEABLE
1337 * is clear, no page table entries need updating.
1339 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED);
1340 if ((m->oflags & VPO_BUSY) == 0 &&
1341 (m->aflags & PGA_WRITEABLE) == 0)
1343 vm_page_lock_queues();
1344 lo = moea_attr_fetch(m);
1346 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1347 pmap = pvo->pvo_pmap;
1349 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1350 pt = moea_pvo_to_pte(pvo, -1);
1351 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1352 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1354 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1355 lo |= pvo->pvo_pte.pte.pte_lo;
1356 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1357 moea_pte_change(pt, &pvo->pvo_pte.pte,
1359 mtx_unlock(&moea_table_mutex);
1364 if ((lo & PTE_CHG) != 0) {
1365 moea_attr_clear(m, PTE_CHG);
1368 vm_page_aflag_clear(m, PGA_WRITEABLE);
1369 vm_page_unlock_queues();
1373 * moea_ts_referenced:
1375 * Return a count of reference bits for a page, clearing those bits.
1376 * It is not necessary for every reference bit to be cleared, but it
1377 * is necessary that 0 only be returned when there are truly no
1378 * reference bits set.
1380 * XXX: The exact number of bits to check and clear is a matter that
1381 * should be tested and standardized at some point in the future for
1382 * optimal aging of shared pages.
1385 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1388 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1389 ("moea_ts_referenced: page %p is not managed", m));
1390 return (moea_clear_bit(m, PTE_REF));
1394 * Modify the WIMG settings of all mappings for a page.
1397 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1399 struct pvo_entry *pvo;
1400 struct pvo_head *pvo_head;
1405 if ((m->oflags & VPO_UNMANAGED) != 0) {
1406 m->md.mdpg_cache_attrs = ma;
1410 vm_page_lock_queues();
1411 pvo_head = vm_page_to_pvoh(m);
1412 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1414 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1415 pmap = pvo->pvo_pmap;
1417 pt = moea_pvo_to_pte(pvo, -1);
1418 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1419 pvo->pvo_pte.pte.pte_lo |= lo;
1421 moea_pte_change(pt, &pvo->pvo_pte.pte,
1423 if (pvo->pvo_pmap == kernel_pmap)
1426 mtx_unlock(&moea_table_mutex);
1429 m->md.mdpg_cache_attrs = ma;
1430 vm_page_unlock_queues();
1434 * Map a wired page into kernel virtual address space.
1437 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1440 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1444 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1450 if (va < VM_MIN_KERNEL_ADDRESS)
1451 panic("moea_kenter: attempt to enter non-kernel address %#x",
1455 pte_lo = moea_calc_wimg(pa, ma);
1457 PMAP_LOCK(kernel_pmap);
1458 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1459 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1461 if (error != 0 && error != ENOENT)
1462 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1465 PMAP_UNLOCK(kernel_pmap);
1469 * Extract the physical page address associated with the given kernel virtual
1473 moea_kextract(mmu_t mmu, vm_offset_t va)
1475 struct pvo_entry *pvo;
1479 * Allow direct mappings on 32-bit OEA
1481 if (va < VM_MIN_KERNEL_ADDRESS) {
1485 PMAP_LOCK(kernel_pmap);
1486 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1487 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1488 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1489 PMAP_UNLOCK(kernel_pmap);
1494 * Remove a wired page from kernel virtual address space.
1497 moea_kremove(mmu_t mmu, vm_offset_t va)
1500 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1504 * Map a range of physical addresses into kernel virtual address space.
1506 * The value passed in *virt is a suggested virtual address for the mapping.
1507 * Architectures which can support a direct-mapped physical to virtual region
1508 * can return the appropriate address within that region, leaving '*virt'
1509 * unchanged. We cannot and therefore do not; *virt is updated with the
1510 * first usable address after the mapped region.
1513 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1514 vm_offset_t pa_end, int prot)
1516 vm_offset_t sva, va;
1520 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1521 moea_kenter(mmu, va, pa_start);
1527 * Returns true if the pmap's pv is one of the first
1528 * 16 pvs linked to from this page. This count may
1529 * be changed upwards or downwards in the future; it
1530 * is only necessary that true be returned for a small
1531 * subset of pmaps for proper page aging.
1534 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1537 struct pvo_entry *pvo;
1540 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1541 ("moea_page_exists_quick: page %p is not managed", m));
1544 vm_page_lock_queues();
1545 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1546 if (pvo->pvo_pmap == pmap) {
1553 vm_page_unlock_queues();
1558 * Return the number of managed mappings to the given physical page
1562 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1564 struct pvo_entry *pvo;
1568 if ((m->oflags & VPO_UNMANAGED) != 0)
1570 vm_page_lock_queues();
1571 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1572 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1574 vm_page_unlock_queues();
1578 static u_int moea_vsidcontext;
1581 moea_pinit(mmu_t mmu, pmap_t pmap)
1586 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1587 PMAP_LOCK_INIT(pmap);
1588 LIST_INIT(&pmap->pmap_pvo);
1591 __asm __volatile("mftb %0" : "=r"(entropy));
1593 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1595 pmap->pmap_phys = pmap;
1599 mtx_lock(&moea_vsid_mutex);
1601 * Allocate some segment registers for this pmap.
1603 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1607 * Create a new value by mutiplying by a prime and adding in
1608 * entropy from the timebase register. This is to make the
1609 * VSID more random so that the PT hash function collides
1610 * less often. (Note that the prime casues gcc to do shifts
1611 * instead of a multiply.)
1613 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1614 hash = moea_vsidcontext & (NPMAPS - 1);
1615 if (hash == 0) /* 0 is special, avoid it */
1618 mask = 1 << (hash & (VSID_NBPW - 1));
1619 hash = (moea_vsidcontext & 0xfffff);
1620 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1621 /* anything free in this bucket? */
1622 if (moea_vsid_bitmap[n] == 0xffffffff) {
1623 entropy = (moea_vsidcontext >> 20);
1626 i = ffs(~moea_vsid_bitmap[n]) - 1;
1628 hash &= 0xfffff & ~(VSID_NBPW - 1);
1631 moea_vsid_bitmap[n] |= mask;
1632 for (i = 0; i < 16; i++)
1633 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1634 mtx_unlock(&moea_vsid_mutex);
1638 mtx_unlock(&moea_vsid_mutex);
1639 panic("moea_pinit: out of segments");
1643 * Initialize the pmap associated with process 0.
1646 moea_pinit0(mmu_t mmu, pmap_t pm)
1649 moea_pinit(mmu, pm);
1650 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1654 * Set the physical protection on the specified range of this map as requested.
1657 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1660 struct pvo_entry *pvo;
1664 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1665 ("moea_protect: non current pmap"));
1667 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1668 moea_remove(mmu, pm, sva, eva);
1672 vm_page_lock_queues();
1674 for (; sva < eva; sva += PAGE_SIZE) {
1675 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1679 if ((prot & VM_PROT_EXECUTE) == 0)
1680 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1683 * Grab the PTE pointer before we diddle with the cached PTE
1686 pt = moea_pvo_to_pte(pvo, pteidx);
1688 * Change the protection of the page.
1690 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1691 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1694 * If the PVO is in the page table, update that pte as well.
1697 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1698 mtx_unlock(&moea_table_mutex);
1701 vm_page_unlock_queues();
1706 * Map a list of wired pages into kernel virtual address space. This is
1707 * intended for temporary mappings which do not need page modification or
1708 * references recorded. Existing mappings in the region are overwritten.
1711 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1716 while (count-- > 0) {
1717 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1724 * Remove page mappings from kernel virtual address space. Intended for
1725 * temporary mappings entered by moea_qenter.
1728 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1733 while (count-- > 0) {
1734 moea_kremove(mmu, va);
1740 moea_release(mmu_t mmu, pmap_t pmap)
1745 * Free segment register's VSID
1747 if (pmap->pm_sr[0] == 0)
1748 panic("moea_release");
1750 mtx_lock(&moea_vsid_mutex);
1751 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1752 mask = 1 << (idx % VSID_NBPW);
1754 moea_vsid_bitmap[idx] &= ~mask;
1755 mtx_unlock(&moea_vsid_mutex);
1756 PMAP_LOCK_DESTROY(pmap);
1760 * Remove the given range of addresses from the specified map.
1763 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1765 struct pvo_entry *pvo, *tpvo;
1768 vm_page_lock_queues();
1770 if ((eva - sva)/PAGE_SIZE < 10) {
1771 for (; sva < eva; sva += PAGE_SIZE) {
1772 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1774 moea_pvo_remove(pvo, pteidx);
1777 LIST_FOREACH_SAFE(pvo, &pm->pmap_pvo, pvo_plink, tpvo) {
1778 if (PVO_VADDR(pvo) < sva || PVO_VADDR(pvo) >= eva)
1780 moea_pvo_remove(pvo, -1);
1784 vm_page_unlock_queues();
1788 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1789 * will reflect changes in pte's back to the vm_page.
1792 moea_remove_all(mmu_t mmu, vm_page_t m)
1794 struct pvo_head *pvo_head;
1795 struct pvo_entry *pvo, *next_pvo;
1798 vm_page_lock_queues();
1799 pvo_head = vm_page_to_pvoh(m);
1800 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1801 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1803 pmap = pvo->pvo_pmap;
1805 moea_pvo_remove(pvo, -1);
1808 if ((m->aflags & PGA_WRITEABLE) && moea_is_modified(mmu, m)) {
1809 moea_attr_clear(m, PTE_CHG);
1812 vm_page_aflag_clear(m, PGA_WRITEABLE);
1813 vm_page_unlock_queues();
1817 * Allocate a physical page of memory directly from the phys_avail map.
1818 * Can only be called from moea_bootstrap before avail start and end are
1822 moea_bootstrap_alloc(vm_size_t size, u_int align)
1827 size = round_page(size);
1828 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1830 s = (phys_avail[i] + align - 1) & ~(align - 1);
1835 if (s < phys_avail[i] || e > phys_avail[i + 1])
1838 if (s == phys_avail[i]) {
1839 phys_avail[i] += size;
1840 } else if (e == phys_avail[i + 1]) {
1841 phys_avail[i + 1] -= size;
1843 for (j = phys_avail_count * 2; j > i; j -= 2) {
1844 phys_avail[j] = phys_avail[j - 2];
1845 phys_avail[j + 1] = phys_avail[j - 1];
1848 phys_avail[i + 3] = phys_avail[i + 1];
1849 phys_avail[i + 1] = s;
1850 phys_avail[i + 2] = e;
1856 panic("moea_bootstrap_alloc: could not allocate memory");
1860 moea_syncicache(vm_offset_t pa, vm_size_t len)
1862 __syncicache((void *)pa, len);
1866 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1867 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1869 struct pvo_entry *pvo;
1876 moea_pvo_enter_calls++;
1881 * Compute the PTE Group index.
1884 sr = va_to_sr(pm->pm_sr, va);
1885 ptegidx = va_to_pteg(sr, va);
1888 * Remove any existing mapping for this page. Reuse the pvo entry if
1889 * there is a mapping.
1891 mtx_lock(&moea_table_mutex);
1892 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1893 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1894 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1895 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1896 (pte_lo & PTE_PP)) {
1897 mtx_unlock(&moea_table_mutex);
1900 moea_pvo_remove(pvo, -1);
1906 * If we aren't overwriting a mapping, try to allocate.
1908 if (moea_initialized) {
1909 pvo = uma_zalloc(zone, M_NOWAIT);
1911 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1912 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1913 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1914 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1916 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1917 moea_bpvo_pool_index++;
1922 mtx_unlock(&moea_table_mutex);
1927 pvo->pvo_vaddr = va;
1929 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1930 pvo->pvo_vaddr &= ~ADDR_POFF;
1931 if (flags & VM_PROT_EXECUTE)
1932 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1933 if (flags & PVO_WIRED)
1934 pvo->pvo_vaddr |= PVO_WIRED;
1935 if (pvo_head != &moea_pvo_kunmanaged)
1936 pvo->pvo_vaddr |= PVO_MANAGED;
1938 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1940 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1945 LIST_INSERT_HEAD(&pm->pmap_pvo, pvo, pvo_plink);
1948 * Remember if the list was empty and therefore will be the first
1951 if (LIST_FIRST(pvo_head) == NULL)
1953 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1955 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1956 pm->pm_stats.wired_count++;
1957 pm->pm_stats.resident_count++;
1960 * We hope this succeeds but it isn't required.
1962 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1964 PVO_PTEGIDX_SET(pvo, i);
1966 panic("moea_pvo_enter: overflow");
1967 moea_pte_overflow++;
1969 mtx_unlock(&moea_table_mutex);
1971 return (first ? ENOENT : 0);
1975 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1980 * If there is an active pte entry, we need to deactivate it (and
1981 * save the ref & cfg bits).
1983 pt = moea_pvo_to_pte(pvo, pteidx);
1985 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1986 mtx_unlock(&moea_table_mutex);
1987 PVO_PTEGIDX_CLR(pvo);
1989 moea_pte_overflow--;
1993 * Update our statistics.
1995 pvo->pvo_pmap->pm_stats.resident_count--;
1996 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1997 pvo->pvo_pmap->pm_stats.wired_count--;
2000 * Save the REF/CHG bits into their cache if the page is managed.
2002 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2005 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2007 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2008 (PTE_REF | PTE_CHG));
2013 * Remove this PVO from the PV and pmap lists.
2015 LIST_REMOVE(pvo, pvo_vlink);
2016 LIST_REMOVE(pvo, pvo_plink);
2019 * Remove this from the overflow list and return it to the pool
2020 * if we aren't going to reuse it.
2022 LIST_REMOVE(pvo, pvo_olink);
2023 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2024 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2025 moea_upvo_zone, pvo);
2027 moea_pvo_remove_calls++;
2031 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2036 * We can find the actual pte entry without searching by grabbing
2037 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2038 * noticing the HID bit.
2040 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2041 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2042 pteidx ^= moea_pteg_mask * 8;
2047 static struct pvo_entry *
2048 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2050 struct pvo_entry *pvo;
2055 sr = va_to_sr(pm->pm_sr, va);
2056 ptegidx = va_to_pteg(sr, va);
2058 mtx_lock(&moea_table_mutex);
2059 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2060 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2062 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2066 mtx_unlock(&moea_table_mutex);
2072 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2077 * If we haven't been supplied the ptegidx, calculate it.
2083 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2084 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2085 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2088 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2089 mtx_lock(&moea_table_mutex);
2091 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2092 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2093 "valid pte index", pvo);
2096 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2097 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2098 "pvo but no valid pte", pvo);
2101 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2102 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2103 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2104 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2107 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2109 panic("moea_pvo_to_pte: pvo %p pte does not match "
2110 "pte %p in moea_pteg_table", pvo, pt);
2113 mtx_assert(&moea_table_mutex, MA_OWNED);
2117 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2118 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2119 "moea_pteg_table but valid in pvo", pvo, pt);
2122 mtx_unlock(&moea_table_mutex);
2127 * XXX: THIS STUFF SHOULD BE IN pte.c?
2130 moea_pte_spill(vm_offset_t addr)
2132 struct pvo_entry *source_pvo, *victim_pvo;
2133 struct pvo_entry *pvo;
2142 ptegidx = va_to_pteg(sr, addr);
2145 * Have to substitute some entry. Use the primary hash for this.
2146 * Use low bits of timebase as random generator.
2148 pteg = &moea_pteg_table[ptegidx];
2149 mtx_lock(&moea_table_mutex);
2150 __asm __volatile("mftb %0" : "=r"(i));
2156 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2158 * We need to find a pvo entry for this address.
2160 if (source_pvo == NULL &&
2161 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2162 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2164 * Now found an entry to be spilled into the pteg.
2165 * The PTE is now valid, so we know it's active.
2167 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2170 PVO_PTEGIDX_SET(pvo, j);
2171 moea_pte_overflow--;
2172 mtx_unlock(&moea_table_mutex);
2178 if (victim_pvo != NULL)
2183 * We also need the pvo entry of the victim we are replacing
2184 * so save the R & C bits of the PTE.
2186 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2187 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2189 if (source_pvo != NULL)
2194 if (source_pvo == NULL) {
2195 mtx_unlock(&moea_table_mutex);
2199 if (victim_pvo == NULL) {
2200 if ((pt->pte_hi & PTE_HID) == 0)
2201 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2205 * If this is a secondary PTE, we need to search it's primary
2206 * pvo bucket for the matching PVO.
2208 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2211 * We also need the pvo entry of the victim we are
2212 * replacing so save the R & C bits of the PTE.
2214 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2220 if (victim_pvo == NULL)
2221 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2226 * We are invalidating the TLB entry for the EA we are replacing even
2227 * though it's valid. If we don't, we lose any ref/chg bit changes
2228 * contained in the TLB entry.
2230 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2232 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2233 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2235 PVO_PTEGIDX_CLR(victim_pvo);
2236 PVO_PTEGIDX_SET(source_pvo, i);
2237 moea_pte_replacements++;
2239 mtx_unlock(&moea_table_mutex);
2244 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2249 mtx_assert(&moea_table_mutex, MA_OWNED);
2252 * First try primary hash.
2254 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2255 if ((pt->pte_hi & PTE_VALID) == 0) {
2256 pvo_pt->pte_hi &= ~PTE_HID;
2257 moea_pte_set(pt, pvo_pt);
2263 * Now try secondary hash.
2265 ptegidx ^= moea_pteg_mask;
2267 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2268 if ((pt->pte_hi & PTE_VALID) == 0) {
2269 pvo_pt->pte_hi |= PTE_HID;
2270 moea_pte_set(pt, pvo_pt);
2275 panic("moea_pte_insert: overflow");
2280 moea_query_bit(vm_page_t m, int ptebit)
2282 struct pvo_entry *pvo;
2285 if (moea_attr_fetch(m) & ptebit)
2288 vm_page_lock_queues();
2289 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2292 * See if we saved the bit off. If so, cache it and return
2295 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2296 moea_attr_save(m, ptebit);
2297 vm_page_unlock_queues();
2303 * No luck, now go through the hard part of looking at the PTEs
2304 * themselves. Sync so that any pending REF/CHG bits are flushed to
2308 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2311 * See if this pvo has a valid PTE. if so, fetch the
2312 * REF/CHG bits from the valid PTE. If the appropriate
2313 * ptebit is set, cache it and return success.
2315 pt = moea_pvo_to_pte(pvo, -1);
2317 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2318 mtx_unlock(&moea_table_mutex);
2319 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2320 moea_attr_save(m, ptebit);
2321 vm_page_unlock_queues();
2327 vm_page_unlock_queues();
2332 moea_clear_bit(vm_page_t m, int ptebit)
2335 struct pvo_entry *pvo;
2338 vm_page_lock_queues();
2341 * Clear the cached value.
2343 moea_attr_clear(m, ptebit);
2346 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2347 * we can reset the right ones). note that since the pvo entries and
2348 * list heads are accessed via BAT0 and are never placed in the page
2349 * table, we don't have to worry about further accesses setting the
2355 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2356 * valid pte clear the ptebit from the valid pte.
2359 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2360 pt = moea_pvo_to_pte(pvo, -1);
2362 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2363 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2365 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2367 mtx_unlock(&moea_table_mutex);
2369 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2372 vm_page_unlock_queues();
2377 * Return true if the physical range is encompassed by the battable[idx]
2380 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2388 * Return immediately if not a valid mapping
2390 if (!(battable[idx].batu & BAT_Vs))
2394 * The BAT entry must be cache-inhibited, guarded, and r/w
2395 * so it can function as an i/o page
2397 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2398 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2402 * The address should be within the BAT range. Assume that the
2403 * start address in the BAT has the correct alignment (thus
2404 * not requiring masking)
2406 start = battable[idx].batl & BAT_PBS;
2407 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2408 end = start | (bat_ble << 15) | 0x7fff;
2410 if ((pa < start) || ((pa + size) > end))
2417 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2422 * This currently does not work for entries that
2423 * overlap 256M BAT segments.
2426 for(i = 0; i < 16; i++)
2427 if (moea_bat_mapped(i, pa, size) == 0)
2434 * Map a set of physical memory pages into the kernel virtual
2435 * address space. Return a pointer to where it is mapped. This
2436 * routine is intended to be used for mapping device memory,
2440 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2443 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2447 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2449 vm_offset_t va, tmpva, ppa, offset;
2452 ppa = trunc_page(pa);
2453 offset = pa & PAGE_MASK;
2454 size = roundup(offset + size, PAGE_SIZE);
2457 * If the physical address lies within a valid BAT table entry,
2458 * return the 1:1 mapping. This currently doesn't work
2459 * for regions that overlap 256M BAT segments.
2461 for (i = 0; i < 16; i++) {
2462 if (moea_bat_mapped(i, pa, size) == 0)
2463 return ((void *) pa);
2466 va = kmem_alloc_nofault(kernel_map, size);
2468 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2470 for (tmpva = va; size > 0;) {
2471 moea_kenter_attr(mmu, tmpva, ppa, ma);
2478 return ((void *)(va + offset));
2482 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2484 vm_offset_t base, offset;
2487 * If this is outside kernel virtual space, then it's a
2488 * battable entry and doesn't require unmapping
2490 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2491 base = trunc_page(va);
2492 offset = va & PAGE_MASK;
2493 size = roundup(offset + size, PAGE_SIZE);
2494 kmem_free(kernel_map, base, size);
2499 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2501 struct pvo_entry *pvo;
2508 lim = round_page(va);
2509 len = MIN(lim - va, sz);
2510 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2512 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2514 moea_syncicache(pa, len);
2523 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2526 if (md->md_vaddr == ~0UL)
2527 return (md->md_paddr + ofs);
2529 return (md->md_vaddr + ofs);
2533 moea_scan_md(mmu_t mmu, struct pmap_md *prev)
2535 static struct pmap_md md;
2536 struct pvo_entry *pvo;
2539 if (dumpsys_minidump) {
2540 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2542 /* 1st: kernel .data and .bss. */
2544 md.md_vaddr = trunc_page((uintptr_t)_etext);
2545 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2548 switch (prev->md_index) {
2550 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2552 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2553 md.md_size = round_page(msgbufp->msg_size);
2556 /* 3rd: kernel VM. */
2557 va = prev->md_vaddr + prev->md_size;
2558 /* Find start of next chunk (from va). */
2559 while (va < virtual_end) {
2560 /* Don't dump the buffer cache. */
2561 if (va >= kmi.buffer_sva &&
2562 va < kmi.buffer_eva) {
2563 va = kmi.buffer_eva;
2566 pvo = moea_pvo_find_va(kernel_pmap,
2567 va & ~ADDR_POFF, NULL);
2569 (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2573 if (va < virtual_end) {
2576 /* Find last page in chunk. */
2577 while (va < virtual_end) {
2578 /* Don't run into the buffer cache. */
2579 if (va == kmi.buffer_sva)
2581 pvo = moea_pvo_find_va(kernel_pmap,
2582 va & ~ADDR_POFF, NULL);
2584 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2588 md.md_size = va - md.md_vaddr;
2596 } else { /* minidumps */
2597 mem_regions(&pregions, &pregions_sz,
2598 ®ions, ®ions_sz);
2601 /* first physical chunk. */
2602 md.md_paddr = pregions[0].mr_start;
2603 md.md_size = pregions[0].mr_size;
2606 } else if (md.md_index < pregions_sz) {
2607 md.md_paddr = pregions[md.md_index].mr_start;
2608 md.md_size = pregions[md.md_index].mr_size;
2612 /* There's no next physical chunk. */