2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/msgbuf.h>
124 #include <sys/mutex.h>
125 #include <sys/proc.h>
126 #include <sys/sysctl.h>
127 #include <sys/systm.h>
128 #include <sys/vmmeter.h>
130 #include <dev/ofw/openfirm.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
143 #include <machine/cpu.h>
144 #include <machine/platform.h>
145 #include <machine/bat.h>
146 #include <machine/frame.h>
147 #include <machine/md_var.h>
148 #include <machine/psl.h>
149 #include <machine/pte.h>
150 #include <machine/smp.h>
151 #include <machine/sr.h>
152 #include <machine/mmuvar.h>
158 #define TODO panic("%s: not implemented", __func__);
160 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
161 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
162 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
164 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */
165 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */
166 #define PVO_WIRED 0x010 /* PVO entry is wired */
167 #define PVO_MANAGED 0x020 /* PVO entry is managed */
168 #define PVO_EXECUTABLE 0x040 /* PVO entry is executable */
169 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during
171 #define PVO_FAKE 0x100 /* fictitious phys page */
172 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
173 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
174 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
175 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
176 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
177 #define PVO_PTEGIDX_CLR(pvo) \
178 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
179 #define PVO_PTEGIDX_SET(pvo, i) \
180 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
182 #define MOEA_PVO_CHECK(pvo)
192 * Map of physical memory regions.
194 static struct mem_region *regions;
195 static struct mem_region *pregions;
196 u_int phys_avail_count;
197 int regions_sz, pregions_sz;
198 static struct ofw_map *translations;
200 extern struct pmap ofw_pmap;
203 * Lock for the pteg and pvo tables.
205 struct mtx moea_table_mutex;
206 struct mtx moea_vsid_mutex;
208 /* tlbie instruction synchronization */
209 static struct mtx tlbie_mtx;
214 static struct pteg *moea_pteg_table;
215 u_int moea_pteg_count;
216 u_int moea_pteg_mask;
221 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
222 struct pvo_head moea_pvo_kunmanaged =
223 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
225 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
226 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
228 #define BPVO_POOL_SIZE 32768
229 static struct pvo_entry *moea_bpvo_pool;
230 static int moea_bpvo_pool_index = 0;
232 #define VSID_NBPW (sizeof(u_int32_t) * 8)
233 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
235 static boolean_t moea_initialized = FALSE;
240 u_int moea_pte_valid = 0;
241 u_int moea_pte_overflow = 0;
242 u_int moea_pte_replacements = 0;
243 u_int moea_pvo_entries = 0;
244 u_int moea_pvo_enter_calls = 0;
245 u_int moea_pvo_remove_calls = 0;
246 u_int moea_pte_spills = 0;
247 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
249 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
250 &moea_pte_overflow, 0, "");
251 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
252 &moea_pte_replacements, 0, "");
253 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
255 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
256 &moea_pvo_enter_calls, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
258 &moea_pvo_remove_calls, 0, "");
259 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
260 &moea_pte_spills, 0, "");
263 * Allocate physical memory for use in moea_bootstrap.
265 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
270 static int moea_pte_insert(u_int, struct pte *);
275 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
276 vm_offset_t, vm_offset_t, u_int, int);
277 static void moea_pvo_remove(struct pvo_entry *, int);
278 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
279 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
284 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
285 vm_prot_t, boolean_t);
286 static void moea_syncicache(vm_offset_t, vm_size_t);
287 static boolean_t moea_query_bit(vm_page_t, int);
288 static u_int moea_clear_bit(vm_page_t, int, int *);
289 static void moea_kremove(mmu_t, vm_offset_t);
290 int moea_pte_spill(vm_offset_t);
293 * Kernel MMU interface
295 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
296 void moea_clear_modify(mmu_t, vm_page_t);
297 void moea_clear_reference(mmu_t, vm_page_t);
298 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
299 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
300 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
302 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
303 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
304 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
305 void moea_init(mmu_t);
306 boolean_t moea_is_modified(mmu_t, vm_page_t);
307 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
308 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
309 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
310 int moea_page_wired_mappings(mmu_t, vm_page_t);
311 void moea_pinit(mmu_t, pmap_t);
312 void moea_pinit0(mmu_t, pmap_t);
313 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
314 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
315 void moea_qremove(mmu_t, vm_offset_t, int);
316 void moea_release(mmu_t, pmap_t);
317 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
318 void moea_remove_all(mmu_t, vm_page_t);
319 void moea_remove_write(mmu_t, vm_page_t);
320 void moea_zero_page(mmu_t, vm_page_t);
321 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
322 void moea_zero_page_idle(mmu_t, vm_page_t);
323 void moea_activate(mmu_t, struct thread *);
324 void moea_deactivate(mmu_t, struct thread *);
325 void moea_cpu_bootstrap(mmu_t, int);
326 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
327 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
328 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
329 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
330 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
331 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
332 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
333 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
334 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
335 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
337 static mmu_method_t moea_methods[] = {
338 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
339 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
340 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
341 MMUMETHOD(mmu_copy_page, moea_copy_page),
342 MMUMETHOD(mmu_enter, moea_enter),
343 MMUMETHOD(mmu_enter_object, moea_enter_object),
344 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
345 MMUMETHOD(mmu_extract, moea_extract),
346 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
347 MMUMETHOD(mmu_init, moea_init),
348 MMUMETHOD(mmu_is_modified, moea_is_modified),
349 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
350 MMUMETHOD(mmu_map, moea_map),
351 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
352 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
353 MMUMETHOD(mmu_pinit, moea_pinit),
354 MMUMETHOD(mmu_pinit0, moea_pinit0),
355 MMUMETHOD(mmu_protect, moea_protect),
356 MMUMETHOD(mmu_qenter, moea_qenter),
357 MMUMETHOD(mmu_qremove, moea_qremove),
358 MMUMETHOD(mmu_release, moea_release),
359 MMUMETHOD(mmu_remove, moea_remove),
360 MMUMETHOD(mmu_remove_all, moea_remove_all),
361 MMUMETHOD(mmu_remove_write, moea_remove_write),
362 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
363 MMUMETHOD(mmu_zero_page, moea_zero_page),
364 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
365 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
366 MMUMETHOD(mmu_activate, moea_activate),
367 MMUMETHOD(mmu_deactivate, moea_deactivate),
368 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
370 /* Internal interfaces */
371 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
372 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
373 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
374 MMUMETHOD(mmu_mapdev, moea_mapdev),
375 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
376 MMUMETHOD(mmu_kextract, moea_kextract),
377 MMUMETHOD(mmu_kenter, moea_kenter),
378 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
379 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
384 static mmu_def_t oea_mmu = {
391 static __inline uint32_t
392 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
397 if (ma != VM_MEMATTR_DEFAULT) {
399 case VM_MEMATTR_UNCACHEABLE:
400 return (PTE_I | PTE_G);
401 case VM_MEMATTR_WRITE_COMBINING:
402 case VM_MEMATTR_WRITE_BACK:
403 case VM_MEMATTR_PREFETCHABLE:
405 case VM_MEMATTR_WRITE_THROUGH:
406 return (PTE_W | PTE_M);
411 * Assume the page is cache inhibited and access is guarded unless
412 * it's in our available memory array.
414 pte_lo = PTE_I | PTE_G;
415 for (i = 0; i < pregions_sz; i++) {
416 if ((pa >= pregions[i].mr_start) &&
417 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
427 tlbie(vm_offset_t va)
430 mtx_lock_spin(&tlbie_mtx);
431 __asm __volatile("tlbie %0" :: "r"(va));
432 __asm __volatile("tlbsync");
434 mtx_unlock_spin(&tlbie_mtx);
442 for (va = 0; va < 0x00040000; va += 0x00001000) {
443 __asm __volatile("tlbie %0" :: "r"(va));
446 __asm __volatile("tlbsync");
451 va_to_sr(u_int *sr, vm_offset_t va)
453 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
456 static __inline u_int
457 va_to_pteg(u_int sr, vm_offset_t addr)
461 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
463 return (hash & moea_pteg_mask);
466 static __inline struct pvo_head *
467 vm_page_to_pvoh(vm_page_t m)
470 return (&m->md.mdpg_pvoh);
474 moea_attr_clear(vm_page_t m, int ptebit)
477 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
478 m->md.mdpg_attrs &= ~ptebit;
482 moea_attr_fetch(vm_page_t m)
485 return (m->md.mdpg_attrs);
489 moea_attr_save(vm_page_t m, int ptebit)
492 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
493 m->md.mdpg_attrs |= ptebit;
497 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
499 if (pt->pte_hi == pvo_pt->pte_hi)
506 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
508 return (pt->pte_hi & ~PTE_VALID) ==
509 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
510 ((va >> ADDR_API_SHFT) & PTE_API) | which);
514 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
517 mtx_assert(&moea_table_mutex, MA_OWNED);
520 * Construct a PTE. Default to IMB initially. Valid bit only gets
521 * set when the real pte is set in memory.
523 * Note: Don't set the valid bit for correct operation of tlb update.
525 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
526 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
531 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
534 mtx_assert(&moea_table_mutex, MA_OWNED);
535 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
539 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
542 mtx_assert(&moea_table_mutex, MA_OWNED);
545 * As shown in Section 7.6.3.2.3
547 pt->pte_lo &= ~ptebit;
552 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
555 mtx_assert(&moea_table_mutex, MA_OWNED);
556 pvo_pt->pte_hi |= PTE_VALID;
559 * Update the PTE as defined in section 7.6.3.1.
560 * Note that the REF/CHG bits are from pvo_pt and thus should havce
561 * been saved so this routine can restore them (if desired).
563 pt->pte_lo = pvo_pt->pte_lo;
565 pt->pte_hi = pvo_pt->pte_hi;
571 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
574 mtx_assert(&moea_table_mutex, MA_OWNED);
575 pvo_pt->pte_hi &= ~PTE_VALID;
578 * Force the reg & chg bits back into the PTEs.
583 * Invalidate the pte.
585 pt->pte_hi &= ~PTE_VALID;
590 * Save the reg & chg bits.
592 moea_pte_synch(pt, pvo_pt);
597 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
603 moea_pte_unset(pt, pvo_pt, va);
604 moea_pte_set(pt, pvo_pt);
608 * Quick sort callout for comparing memory regions.
610 static int mr_cmp(const void *a, const void *b);
611 static int om_cmp(const void *a, const void *b);
614 mr_cmp(const void *a, const void *b)
616 const struct mem_region *regiona;
617 const struct mem_region *regionb;
621 if (regiona->mr_start < regionb->mr_start)
623 else if (regiona->mr_start > regionb->mr_start)
630 om_cmp(const void *a, const void *b)
632 const struct ofw_map *mapa;
633 const struct ofw_map *mapb;
637 if (mapa->om_pa < mapb->om_pa)
639 else if (mapa->om_pa > mapb->om_pa)
646 moea_cpu_bootstrap(mmu_t mmup, int ap)
653 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
654 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
656 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
657 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
661 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
662 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
665 __asm __volatile("mtibatu 1,%0" :: "r"(0));
666 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
667 __asm __volatile("mtibatu 2,%0" :: "r"(0));
668 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
669 __asm __volatile("mtibatu 3,%0" :: "r"(0));
672 for (i = 0; i < 16; i++)
673 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
675 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
676 __asm __volatile("mtsr %0,%1" :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
679 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
680 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
687 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
690 phandle_t chosen, mmu;
694 vm_size_t size, physsz, hwphyssz;
695 vm_offset_t pa, va, off;
700 * Set up BAT0 to map the lowest 256 MB area
702 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
703 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
706 * Map PCI memory space.
708 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
709 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
711 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
712 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
714 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
715 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
717 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
718 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
723 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
724 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
727 * Use an IBAT and a DBAT to map the bottom segment of memory
728 * where we are. Turn off instruction relocation temporarily
729 * to prevent faults while reprogramming the IBAT.
732 mtmsr(msr & ~PSL_IR);
733 __asm (".balign 32; \n"
734 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
735 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
736 :: "r"(battable[0].batu), "r"(battable[0].batl));
740 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
741 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
744 /* set global direct map flag */
747 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
748 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
750 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
751 for (i = 0; i < pregions_sz; i++) {
755 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
756 pregions[i].mr_start,
757 pregions[i].mr_start + pregions[i].mr_size,
758 pregions[i].mr_size);
760 * Install entries into the BAT table to allow all
761 * of physmem to be convered by on-demand BAT entries.
762 * The loop will sometimes set the same battable element
763 * twice, but that's fine since they won't be used for
766 pa = pregions[i].mr_start & 0xf0000000;
767 end = pregions[i].mr_start + pregions[i].mr_size;
769 u_int n = pa >> ADDR_SR_SHFT;
771 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
772 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
773 pa += SEGMENT_LENGTH;
777 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
778 panic("moea_bootstrap: phys_avail too small");
779 qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
780 phys_avail_count = 0;
783 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
784 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
785 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
786 regions[i].mr_start + regions[i].mr_size,
789 (physsz + regions[i].mr_size) >= hwphyssz) {
790 if (physsz < hwphyssz) {
791 phys_avail[j] = regions[i].mr_start;
792 phys_avail[j + 1] = regions[i].mr_start +
799 phys_avail[j] = regions[i].mr_start;
800 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
802 physsz += regions[i].mr_size;
804 physmem = btoc(physsz);
807 * Allocate PTEG table.
810 moea_pteg_count = PTEGCOUNT;
812 moea_pteg_count = 0x1000;
814 while (moea_pteg_count < physmem)
815 moea_pteg_count <<= 1;
817 moea_pteg_count >>= 1;
818 #endif /* PTEGCOUNT */
820 size = moea_pteg_count * sizeof(struct pteg);
821 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
823 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
824 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
825 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
826 moea_pteg_mask = moea_pteg_count - 1;
829 * Allocate pv/overflow lists.
831 size = sizeof(struct pvo_head) * moea_pteg_count;
832 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
834 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
835 for (i = 0; i < moea_pteg_count; i++)
836 LIST_INIT(&moea_pvo_table[i]);
839 * Initialize the lock that synchronizes access to the pteg and pvo
842 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
844 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
846 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
849 * Initialise the unmanaged pvo pool.
851 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
852 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
853 moea_bpvo_pool_index = 0;
856 * Make sure kernel vsid is allocated as well as VSID 0.
858 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
859 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
860 moea_vsid_bitmap[0] |= 1;
863 * Set up the Open Firmware pmap and add it's mappings.
865 moea_pinit(mmup, &ofw_pmap);
866 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
867 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
868 if ((chosen = OF_finddevice("/chosen")) == -1)
869 panic("moea_bootstrap: can't find /chosen");
870 OF_getprop(chosen, "mmu", &mmui, 4);
871 if ((mmu = OF_instance_to_package(mmui)) == -1)
872 panic("moea_bootstrap: can't get mmu package");
873 if ((sz = OF_getproplen(mmu, "translations")) == -1)
874 panic("moea_bootstrap: can't get ofw translation count");
876 for (i = 0; phys_avail[i] != 0; i += 2) {
877 if (phys_avail[i + 1] >= sz) {
878 translations = (struct ofw_map *)phys_avail[i];
882 if (translations == NULL)
883 panic("moea_bootstrap: no space to copy translations");
884 bzero(translations, sz);
885 if (OF_getprop(mmu, "translations", translations, sz) == -1)
886 panic("moea_bootstrap: can't get ofw translations");
887 CTR0(KTR_PMAP, "moea_bootstrap: translations");
888 sz /= sizeof(*translations);
889 qsort(translations, sz, sizeof (*translations), om_cmp);
890 for (i = 0, ofw_mappings = 0; i < sz; i++) {
891 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
892 translations[i].om_pa, translations[i].om_va,
893 translations[i].om_len);
896 * If the mapping is 1:1, let the RAM and device on-demand
897 * BAT tables take care of the translation.
899 if (translations[i].om_va == translations[i].om_pa)
902 /* Enter the pages */
903 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
906 m.phys_addr = translations[i].om_pa + off;
907 m.md.mdpg_cache_attrs = VM_MEMATTR_DEFAULT;
908 PMAP_LOCK(&ofw_pmap);
909 moea_enter_locked(&ofw_pmap,
910 translations[i].om_va + off, &m,
912 PMAP_UNLOCK(&ofw_pmap);
918 * Calculate the last available physical address.
920 for (i = 0; phys_avail[i + 2] != 0; i += 2)
922 Maxmem = powerpc_btop(phys_avail[i + 1]);
925 * Initialize the kernel pmap (which is statically allocated).
927 PMAP_LOCK_INIT(kernel_pmap);
928 for (i = 0; i < 16; i++) {
929 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
931 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
932 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
933 kernel_pmap->pm_active = ~0;
935 moea_cpu_bootstrap(mmup,0);
940 * Set the start and end of kva.
942 virtual_avail = VM_MIN_KERNEL_ADDRESS;
943 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
946 * Allocate a kernel stack with a guard page for thread0 and map it
947 * into the kernel page map.
949 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
950 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
951 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
952 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
953 thread0.td_kstack = va;
954 thread0.td_kstack_pages = KSTACK_PAGES;
955 for (i = 0; i < KSTACK_PAGES; i++) {
956 moea_kenter(mmup, va, pa);
962 * Allocate virtual address space for the message buffer.
964 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
965 msgbufp = (struct msgbuf *)virtual_avail;
967 virtual_avail += round_page(msgbufsize);
968 while (va < virtual_avail) {
969 moea_kenter(mmup, va, pa);
975 * Allocate virtual address space for the dynamic percpu area.
977 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
978 dpcpu = (void *)virtual_avail;
980 virtual_avail += DPCPU_SIZE;
981 while (va < virtual_avail) {
982 moea_kenter(mmup, va, pa);
986 dpcpu_init(dpcpu, 0);
990 * Activate a user pmap. The pmap must be activated before it's address
991 * space can be accessed in any way.
994 moea_activate(mmu_t mmu, struct thread *td)
999 * Load all the data we need up front to encourage the compiler to
1000 * not issue any loads while we have interrupts disabled below.
1002 pm = &td->td_proc->p_vmspace->vm_pmap;
1003 pmr = pm->pmap_phys;
1005 pm->pm_active |= PCPU_GET(cpumask);
1006 PCPU_SET(curpmap, pmr);
1010 moea_deactivate(mmu_t mmu, struct thread *td)
1014 pm = &td->td_proc->p_vmspace->vm_pmap;
1015 pm->pm_active &= ~PCPU_GET(cpumask);
1016 PCPU_SET(curpmap, NULL);
1020 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1022 struct pvo_entry *pvo;
1025 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1029 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1030 pm->pm_stats.wired_count++;
1031 pvo->pvo_vaddr |= PVO_WIRED;
1033 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1034 pm->pm_stats.wired_count--;
1035 pvo->pvo_vaddr &= ~PVO_WIRED;
1042 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1047 dst = VM_PAGE_TO_PHYS(mdst);
1048 src = VM_PAGE_TO_PHYS(msrc);
1050 kcopy((void *)src, (void *)dst, PAGE_SIZE);
1054 * Zero a page of physical memory by temporarily mapping it into the tlb.
1057 moea_zero_page(mmu_t mmu, vm_page_t m)
1059 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1060 void *va = (void *)pa;
1062 bzero(va, PAGE_SIZE);
1066 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1068 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1069 void *va = (void *)(pa + off);
1075 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1077 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1078 void *va = (void *)pa;
1080 bzero(va, PAGE_SIZE);
1084 * Map the given physical page at the specified virtual address in the
1085 * target pmap with the protection requested. If specified the page
1086 * will be wired down.
1089 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1093 vm_page_lock_queues();
1095 moea_enter_locked(pmap, va, m, prot, wired);
1096 vm_page_unlock_queues();
1101 * Map the given physical page at the specified virtual address in the
1102 * target pmap with the protection requested. If specified the page
1103 * will be wired down.
1105 * The page queues and pmap must be locked.
1108 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1111 struct pvo_head *pvo_head;
1114 u_int pte_lo, pvo_flags, was_exec;
1117 if (!moea_initialized) {
1118 pvo_head = &moea_pvo_kunmanaged;
1119 zone = moea_upvo_zone;
1122 was_exec = PTE_EXEC;
1124 pvo_head = vm_page_to_pvoh(m);
1126 zone = moea_mpvo_zone;
1127 pvo_flags = PVO_MANAGED;
1130 if (pmap_bootstrapped)
1131 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1132 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1134 /* XXX change the pvo head for fake pages */
1135 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) {
1136 pvo_flags &= ~PVO_MANAGED;
1137 pvo_head = &moea_pvo_kunmanaged;
1138 zone = moea_upvo_zone;
1142 * If this is a managed page, and it's the first reference to the page,
1143 * clear the execness of the page. Otherwise fetch the execness.
1145 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) {
1146 if (LIST_EMPTY(pvo_head)) {
1147 moea_attr_clear(pg, PTE_EXEC);
1149 was_exec = moea_attr_fetch(pg) & PTE_EXEC;
1153 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1155 if (prot & VM_PROT_WRITE) {
1157 if (pmap_bootstrapped)
1158 vm_page_flag_set(m, PG_WRITEABLE);
1162 if (prot & VM_PROT_EXECUTE)
1163 pvo_flags |= PVO_EXECUTABLE;
1166 pvo_flags |= PVO_WIRED;
1168 if ((m->flags & PG_FICTITIOUS) != 0)
1169 pvo_flags |= PVO_FAKE;
1171 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1175 * Flush the real page from the instruction cache if this page is
1176 * mapped executable and cacheable and was not previously mapped (or
1177 * was not mapped executable).
1179 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
1180 (pte_lo & PTE_I) == 0 && was_exec == 0) {
1182 * Flush the real memory from the cache.
1184 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1186 moea_attr_save(pg, PTE_EXEC);
1189 /* XXX syncicache always until problems are sorted */
1190 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1194 * Maps a sequence of resident pages belonging to the same object.
1195 * The sequence begins with the given page m_start. This page is
1196 * mapped at the given virtual address start. Each subsequent page is
1197 * mapped at a virtual address that is offset from start by the same
1198 * amount as the page is offset from m_start within the object. The
1199 * last page in the sequence is the page with the largest offset from
1200 * m_start that can be mapped at a virtual address less than the given
1201 * virtual address end. Not every virtual page between start and end
1202 * is mapped; only those for which a resident page exists with the
1203 * corresponding offset from m_start are mapped.
1206 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1207 vm_page_t m_start, vm_prot_t prot)
1210 vm_pindex_t diff, psize;
1212 psize = atop(end - start);
1215 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1216 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1217 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1218 m = TAILQ_NEXT(m, listq);
1224 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1229 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1236 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1238 struct pvo_entry *pvo;
1242 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1246 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1252 * Atomically extract and hold the physical page with the given
1253 * pmap and virtual address pair if that mapping permits the given
1257 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1259 struct pvo_entry *pvo;
1263 vm_page_lock_queues();
1265 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1266 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1267 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1268 (prot & VM_PROT_WRITE) == 0)) {
1269 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1272 vm_page_unlock_queues();
1278 moea_init(mmu_t mmu)
1281 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1282 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1283 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1284 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1285 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1286 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1287 moea_initialized = TRUE;
1291 moea_is_modified(mmu_t mmu, vm_page_t m)
1294 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0)
1297 return (moea_query_bit(m, PTE_CHG));
1301 moea_clear_reference(mmu_t mmu, vm_page_t m)
1304 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1306 moea_clear_bit(m, PTE_REF, NULL);
1310 moea_clear_modify(mmu_t mmu, vm_page_t m)
1313 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1315 moea_clear_bit(m, PTE_CHG, NULL);
1319 * Clear the write and modified bits in each of the given page's mappings.
1322 moea_remove_write(mmu_t mmu, vm_page_t m)
1324 struct pvo_entry *pvo;
1329 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1330 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1331 (m->flags & PG_WRITEABLE) == 0)
1333 lo = moea_attr_fetch(m);
1335 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1336 pmap = pvo->pvo_pmap;
1338 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1339 pt = moea_pvo_to_pte(pvo, -1);
1340 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1341 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1343 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1344 lo |= pvo->pvo_pte.pte.pte_lo;
1345 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1346 moea_pte_change(pt, &pvo->pvo_pte.pte,
1348 mtx_unlock(&moea_table_mutex);
1353 if ((lo & PTE_CHG) != 0) {
1354 moea_attr_clear(m, PTE_CHG);
1357 vm_page_flag_clear(m, PG_WRITEABLE);
1361 * moea_ts_referenced:
1363 * Return a count of reference bits for a page, clearing those bits.
1364 * It is not necessary for every reference bit to be cleared, but it
1365 * is necessary that 0 only be returned when there are truly no
1366 * reference bits set.
1368 * XXX: The exact number of bits to check and clear is a matter that
1369 * should be tested and standardized at some point in the future for
1370 * optimal aging of shared pages.
1373 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1377 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1380 count = moea_clear_bit(m, PTE_REF, NULL);
1386 * Modify the WIMG settings of all mappings for a page.
1389 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1391 struct pvo_entry *pvo;
1392 struct pvo_head *pvo_head;
1397 if (m->flags & PG_FICTITIOUS) {
1398 m->md.mdpg_cache_attrs = ma;
1402 vm_page_lock_queues();
1403 pvo_head = vm_page_to_pvoh(m);
1404 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1406 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1407 pmap = pvo->pvo_pmap;
1409 pt = moea_pvo_to_pte(pvo, -1);
1410 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1411 pvo->pvo_pte.pte.pte_lo |= lo;
1413 moea_pte_change(pt, &pvo->pvo_pte.pte,
1415 if (pvo->pvo_pmap == kernel_pmap)
1418 mtx_unlock(&moea_table_mutex);
1421 m->md.mdpg_cache_attrs = ma;
1422 vm_page_unlock_queues();
1426 * Map a wired page into kernel virtual address space.
1429 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1432 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1436 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1442 if (va < VM_MIN_KERNEL_ADDRESS)
1443 panic("moea_kenter: attempt to enter non-kernel address %#x",
1447 pte_lo = moea_calc_wimg(pa, ma);
1449 PMAP_LOCK(kernel_pmap);
1450 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1451 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1453 if (error != 0 && error != ENOENT)
1454 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1458 * Flush the real memory from the instruction cache.
1460 if ((pte_lo & (PTE_I | PTE_G)) == 0) {
1461 moea_syncicache(pa, PAGE_SIZE);
1463 PMAP_UNLOCK(kernel_pmap);
1467 * Extract the physical page address associated with the given kernel virtual
1471 moea_kextract(mmu_t mmu, vm_offset_t va)
1473 struct pvo_entry *pvo;
1477 * Allow direct mappings on 32-bit OEA
1479 if (va < VM_MIN_KERNEL_ADDRESS) {
1483 PMAP_LOCK(kernel_pmap);
1484 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1485 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1486 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1487 PMAP_UNLOCK(kernel_pmap);
1492 * Remove a wired page from kernel virtual address space.
1495 moea_kremove(mmu_t mmu, vm_offset_t va)
1498 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1502 * Map a range of physical addresses into kernel virtual address space.
1504 * The value passed in *virt is a suggested virtual address for the mapping.
1505 * Architectures which can support a direct-mapped physical to virtual region
1506 * can return the appropriate address within that region, leaving '*virt'
1507 * unchanged. We cannot and therefore do not; *virt is updated with the
1508 * first usable address after the mapped region.
1511 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1512 vm_offset_t pa_end, int prot)
1514 vm_offset_t sva, va;
1518 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1519 moea_kenter(mmu, va, pa_start);
1525 * Returns true if the pmap's pv is one of the first
1526 * 16 pvs linked to from this page. This count may
1527 * be changed upwards or downwards in the future; it
1528 * is only necessary that true be returned for a small
1529 * subset of pmaps for proper page aging.
1532 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1535 struct pvo_entry *pvo;
1537 if (!moea_initialized || (m->flags & PG_FICTITIOUS))
1541 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1542 if (pvo->pvo_pmap == pmap)
1552 * Return the number of managed mappings to the given physical page
1556 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1558 struct pvo_entry *pvo;
1562 if (!moea_initialized || (m->flags & PG_FICTITIOUS) != 0)
1564 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1565 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1566 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1571 static u_int moea_vsidcontext;
1574 moea_pinit(mmu_t mmu, pmap_t pmap)
1579 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1580 PMAP_LOCK_INIT(pmap);
1583 __asm __volatile("mftb %0" : "=r"(entropy));
1585 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1587 pmap->pmap_phys = pmap;
1591 mtx_lock(&moea_vsid_mutex);
1593 * Allocate some segment registers for this pmap.
1595 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1599 * Create a new value by mutiplying by a prime and adding in
1600 * entropy from the timebase register. This is to make the
1601 * VSID more random so that the PT hash function collides
1602 * less often. (Note that the prime casues gcc to do shifts
1603 * instead of a multiply.)
1605 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1606 hash = moea_vsidcontext & (NPMAPS - 1);
1607 if (hash == 0) /* 0 is special, avoid it */
1610 mask = 1 << (hash & (VSID_NBPW - 1));
1611 hash = (moea_vsidcontext & 0xfffff);
1612 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1613 /* anything free in this bucket? */
1614 if (moea_vsid_bitmap[n] == 0xffffffff) {
1615 entropy = (moea_vsidcontext >> 20);
1618 i = ffs(~moea_vsid_bitmap[n]) - 1;
1620 hash &= 0xfffff & ~(VSID_NBPW - 1);
1623 moea_vsid_bitmap[n] |= mask;
1624 for (i = 0; i < 16; i++)
1625 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1626 mtx_unlock(&moea_vsid_mutex);
1630 mtx_unlock(&moea_vsid_mutex);
1631 panic("moea_pinit: out of segments");
1635 * Initialize the pmap associated with process 0.
1638 moea_pinit0(mmu_t mmu, pmap_t pm)
1641 moea_pinit(mmu, pm);
1642 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1646 * Set the physical protection on the specified range of this map as requested.
1649 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1652 struct pvo_entry *pvo;
1656 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1657 ("moea_protect: non current pmap"));
1659 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1660 moea_remove(mmu, pm, sva, eva);
1664 vm_page_lock_queues();
1666 for (; sva < eva; sva += PAGE_SIZE) {
1667 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1671 if ((prot & VM_PROT_EXECUTE) == 0)
1672 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1675 * Grab the PTE pointer before we diddle with the cached PTE
1678 pt = moea_pvo_to_pte(pvo, pteidx);
1680 * Change the protection of the page.
1682 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1683 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1686 * If the PVO is in the page table, update that pte as well.
1689 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1690 mtx_unlock(&moea_table_mutex);
1693 vm_page_unlock_queues();
1698 * Map a list of wired pages into kernel virtual address space. This is
1699 * intended for temporary mappings which do not need page modification or
1700 * references recorded. Existing mappings in the region are overwritten.
1703 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1708 while (count-- > 0) {
1709 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1716 * Remove page mappings from kernel virtual address space. Intended for
1717 * temporary mappings entered by moea_qenter.
1720 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1725 while (count-- > 0) {
1726 moea_kremove(mmu, va);
1732 moea_release(mmu_t mmu, pmap_t pmap)
1737 * Free segment register's VSID
1739 if (pmap->pm_sr[0] == 0)
1740 panic("moea_release");
1742 mtx_lock(&moea_vsid_mutex);
1743 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1744 mask = 1 << (idx % VSID_NBPW);
1746 moea_vsid_bitmap[idx] &= ~mask;
1747 mtx_unlock(&moea_vsid_mutex);
1748 PMAP_LOCK_DESTROY(pmap);
1752 * Remove the given range of addresses from the specified map.
1755 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1757 struct pvo_entry *pvo;
1760 vm_page_lock_queues();
1762 for (; sva < eva; sva += PAGE_SIZE) {
1763 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1765 moea_pvo_remove(pvo, pteidx);
1769 vm_page_unlock_queues();
1773 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1774 * will reflect changes in pte's back to the vm_page.
1777 moea_remove_all(mmu_t mmu, vm_page_t m)
1779 struct pvo_head *pvo_head;
1780 struct pvo_entry *pvo, *next_pvo;
1783 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1785 pvo_head = vm_page_to_pvoh(m);
1786 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1787 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1789 MOEA_PVO_CHECK(pvo); /* sanity check */
1790 pmap = pvo->pvo_pmap;
1792 moea_pvo_remove(pvo, -1);
1795 if ((m->flags & PG_WRITEABLE) && moea_is_modified(mmu, m)) {
1796 moea_attr_clear(m, LPTE_CHG);
1799 vm_page_flag_clear(m, PG_WRITEABLE);
1803 * Allocate a physical page of memory directly from the phys_avail map.
1804 * Can only be called from moea_bootstrap before avail start and end are
1808 moea_bootstrap_alloc(vm_size_t size, u_int align)
1813 size = round_page(size);
1814 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1816 s = (phys_avail[i] + align - 1) & ~(align - 1);
1821 if (s < phys_avail[i] || e > phys_avail[i + 1])
1824 if (s == phys_avail[i]) {
1825 phys_avail[i] += size;
1826 } else if (e == phys_avail[i + 1]) {
1827 phys_avail[i + 1] -= size;
1829 for (j = phys_avail_count * 2; j > i; j -= 2) {
1830 phys_avail[j] = phys_avail[j - 2];
1831 phys_avail[j + 1] = phys_avail[j - 1];
1834 phys_avail[i + 3] = phys_avail[i + 1];
1835 phys_avail[i + 1] = s;
1836 phys_avail[i + 2] = e;
1842 panic("moea_bootstrap_alloc: could not allocate memory");
1846 moea_syncicache(vm_offset_t pa, vm_size_t len)
1848 __syncicache((void *)pa, len);
1852 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1853 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1855 struct pvo_entry *pvo;
1862 moea_pvo_enter_calls++;
1867 * Compute the PTE Group index.
1870 sr = va_to_sr(pm->pm_sr, va);
1871 ptegidx = va_to_pteg(sr, va);
1874 * Remove any existing mapping for this page. Reuse the pvo entry if
1875 * there is a mapping.
1877 mtx_lock(&moea_table_mutex);
1878 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1879 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1880 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1881 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1882 (pte_lo & PTE_PP)) {
1883 mtx_unlock(&moea_table_mutex);
1886 moea_pvo_remove(pvo, -1);
1892 * If we aren't overwriting a mapping, try to allocate.
1894 if (moea_initialized) {
1895 pvo = uma_zalloc(zone, M_NOWAIT);
1897 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1898 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1899 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1900 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1902 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1903 moea_bpvo_pool_index++;
1908 mtx_unlock(&moea_table_mutex);
1913 pvo->pvo_vaddr = va;
1915 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1916 pvo->pvo_vaddr &= ~ADDR_POFF;
1917 if (flags & VM_PROT_EXECUTE)
1918 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1919 if (flags & PVO_WIRED)
1920 pvo->pvo_vaddr |= PVO_WIRED;
1921 if (pvo_head != &moea_pvo_kunmanaged)
1922 pvo->pvo_vaddr |= PVO_MANAGED;
1924 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1925 if (flags & PVO_FAKE)
1926 pvo->pvo_vaddr |= PVO_FAKE;
1928 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1931 * Remember if the list was empty and therefore will be the first
1934 if (LIST_FIRST(pvo_head) == NULL)
1936 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1938 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1939 pm->pm_stats.wired_count++;
1940 pm->pm_stats.resident_count++;
1943 * We hope this succeeds but it isn't required.
1945 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
1947 PVO_PTEGIDX_SET(pvo, i);
1949 panic("moea_pvo_enter: overflow");
1950 moea_pte_overflow++;
1952 mtx_unlock(&moea_table_mutex);
1954 return (first ? ENOENT : 0);
1958 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1963 * If there is an active pte entry, we need to deactivate it (and
1964 * save the ref & cfg bits).
1966 pt = moea_pvo_to_pte(pvo, pteidx);
1968 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1969 mtx_unlock(&moea_table_mutex);
1970 PVO_PTEGIDX_CLR(pvo);
1972 moea_pte_overflow--;
1976 * Update our statistics.
1978 pvo->pvo_pmap->pm_stats.resident_count--;
1979 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1980 pvo->pvo_pmap->pm_stats.wired_count--;
1983 * Save the REF/CHG bits into their cache if the page is managed.
1985 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
1988 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1990 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
1991 (PTE_REF | PTE_CHG));
1996 * Remove this PVO from the PV list.
1998 LIST_REMOVE(pvo, pvo_vlink);
2001 * Remove this from the overflow list and return it to the pool
2002 * if we aren't going to reuse it.
2004 LIST_REMOVE(pvo, pvo_olink);
2005 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2006 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2007 moea_upvo_zone, pvo);
2009 moea_pvo_remove_calls++;
2013 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2018 * We can find the actual pte entry without searching by grabbing
2019 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2020 * noticing the HID bit.
2022 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2023 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2024 pteidx ^= moea_pteg_mask * 8;
2029 static struct pvo_entry *
2030 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2032 struct pvo_entry *pvo;
2037 sr = va_to_sr(pm->pm_sr, va);
2038 ptegidx = va_to_pteg(sr, va);
2040 mtx_lock(&moea_table_mutex);
2041 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2042 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2044 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2048 mtx_unlock(&moea_table_mutex);
2054 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2059 * If we haven't been supplied the ptegidx, calculate it.
2065 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2066 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2067 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2070 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2071 mtx_lock(&moea_table_mutex);
2073 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2074 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2075 "valid pte index", pvo);
2078 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2079 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2080 "pvo but no valid pte", pvo);
2083 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2084 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2085 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2086 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2089 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2091 panic("moea_pvo_to_pte: pvo %p pte does not match "
2092 "pte %p in moea_pteg_table", pvo, pt);
2095 mtx_assert(&moea_table_mutex, MA_OWNED);
2099 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2100 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2101 "moea_pteg_table but valid in pvo", pvo, pt);
2104 mtx_unlock(&moea_table_mutex);
2109 * XXX: THIS STUFF SHOULD BE IN pte.c?
2112 moea_pte_spill(vm_offset_t addr)
2114 struct pvo_entry *source_pvo, *victim_pvo;
2115 struct pvo_entry *pvo;
2124 ptegidx = va_to_pteg(sr, addr);
2127 * Have to substitute some entry. Use the primary hash for this.
2128 * Use low bits of timebase as random generator.
2130 pteg = &moea_pteg_table[ptegidx];
2131 mtx_lock(&moea_table_mutex);
2132 __asm __volatile("mftb %0" : "=r"(i));
2138 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2140 * We need to find a pvo entry for this address.
2142 MOEA_PVO_CHECK(pvo);
2143 if (source_pvo == NULL &&
2144 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2145 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2147 * Now found an entry to be spilled into the pteg.
2148 * The PTE is now valid, so we know it's active.
2150 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2153 PVO_PTEGIDX_SET(pvo, j);
2154 moea_pte_overflow--;
2155 MOEA_PVO_CHECK(pvo);
2156 mtx_unlock(&moea_table_mutex);
2162 if (victim_pvo != NULL)
2167 * We also need the pvo entry of the victim we are replacing
2168 * so save the R & C bits of the PTE.
2170 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2171 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2173 if (source_pvo != NULL)
2178 if (source_pvo == NULL) {
2179 mtx_unlock(&moea_table_mutex);
2183 if (victim_pvo == NULL) {
2184 if ((pt->pte_hi & PTE_HID) == 0)
2185 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2189 * If this is a secondary PTE, we need to search it's primary
2190 * pvo bucket for the matching PVO.
2192 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2194 MOEA_PVO_CHECK(pvo);
2196 * We also need the pvo entry of the victim we are
2197 * replacing so save the R & C bits of the PTE.
2199 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2205 if (victim_pvo == NULL)
2206 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2211 * We are invalidating the TLB entry for the EA we are replacing even
2212 * though it's valid. If we don't, we lose any ref/chg bit changes
2213 * contained in the TLB entry.
2215 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2217 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2218 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2220 PVO_PTEGIDX_CLR(victim_pvo);
2221 PVO_PTEGIDX_SET(source_pvo, i);
2222 moea_pte_replacements++;
2224 MOEA_PVO_CHECK(victim_pvo);
2225 MOEA_PVO_CHECK(source_pvo);
2227 mtx_unlock(&moea_table_mutex);
2232 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2237 mtx_assert(&moea_table_mutex, MA_OWNED);
2240 * First try primary hash.
2242 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2243 if ((pt->pte_hi & PTE_VALID) == 0) {
2244 pvo_pt->pte_hi &= ~PTE_HID;
2245 moea_pte_set(pt, pvo_pt);
2251 * Now try secondary hash.
2253 ptegidx ^= moea_pteg_mask;
2255 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2256 if ((pt->pte_hi & PTE_VALID) == 0) {
2257 pvo_pt->pte_hi |= PTE_HID;
2258 moea_pte_set(pt, pvo_pt);
2263 panic("moea_pte_insert: overflow");
2268 moea_query_bit(vm_page_t m, int ptebit)
2270 struct pvo_entry *pvo;
2273 if (moea_attr_fetch(m) & ptebit)
2276 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2277 MOEA_PVO_CHECK(pvo); /* sanity check */
2280 * See if we saved the bit off. If so, cache it and return
2283 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2284 moea_attr_save(m, ptebit);
2285 MOEA_PVO_CHECK(pvo); /* sanity check */
2291 * No luck, now go through the hard part of looking at the PTEs
2292 * themselves. Sync so that any pending REF/CHG bits are flushed to
2296 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2297 MOEA_PVO_CHECK(pvo); /* sanity check */
2300 * See if this pvo has a valid PTE. if so, fetch the
2301 * REF/CHG bits from the valid PTE. If the appropriate
2302 * ptebit is set, cache it and return success.
2304 pt = moea_pvo_to_pte(pvo, -1);
2306 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2307 mtx_unlock(&moea_table_mutex);
2308 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2309 moea_attr_save(m, ptebit);
2310 MOEA_PVO_CHECK(pvo); /* sanity check */
2320 moea_clear_bit(vm_page_t m, int ptebit, int *origbit)
2323 struct pvo_entry *pvo;
2328 * Clear the cached value.
2330 rv = moea_attr_fetch(m);
2331 moea_attr_clear(m, ptebit);
2334 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2335 * we can reset the right ones). note that since the pvo entries and
2336 * list heads are accessed via BAT0 and are never placed in the page
2337 * table, we don't have to worry about further accesses setting the
2343 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2344 * valid pte clear the ptebit from the valid pte.
2347 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2348 MOEA_PVO_CHECK(pvo); /* sanity check */
2349 pt = moea_pvo_to_pte(pvo, -1);
2351 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2352 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2354 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2356 mtx_unlock(&moea_table_mutex);
2358 rv |= pvo->pvo_pte.pte.pte_lo;
2359 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2360 MOEA_PVO_CHECK(pvo); /* sanity check */
2363 if (origbit != NULL) {
2371 * Return true if the physical range is encompassed by the battable[idx]
2374 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2382 * Return immediately if not a valid mapping
2384 if (!(battable[idx].batu & BAT_Vs))
2388 * The BAT entry must be cache-inhibited, guarded, and r/w
2389 * so it can function as an i/o page
2391 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2392 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2396 * The address should be within the BAT range. Assume that the
2397 * start address in the BAT has the correct alignment (thus
2398 * not requiring masking)
2400 start = battable[idx].batl & BAT_PBS;
2401 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2402 end = start | (bat_ble << 15) | 0x7fff;
2404 if ((pa < start) || ((pa + size) > end))
2411 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2416 * This currently does not work for entries that
2417 * overlap 256M BAT segments.
2420 for(i = 0; i < 16; i++)
2421 if (moea_bat_mapped(i, pa, size) == 0)
2428 * Map a set of physical memory pages into the kernel virtual
2429 * address space. Return a pointer to where it is mapped. This
2430 * routine is intended to be used for mapping device memory,
2434 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2437 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2441 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2443 vm_offset_t va, tmpva, ppa, offset;
2446 ppa = trunc_page(pa);
2447 offset = pa & PAGE_MASK;
2448 size = roundup(offset + size, PAGE_SIZE);
2451 * If the physical address lies within a valid BAT table entry,
2452 * return the 1:1 mapping. This currently doesn't work
2453 * for regions that overlap 256M BAT segments.
2455 for (i = 0; i < 16; i++) {
2456 if (moea_bat_mapped(i, pa, size) == 0)
2457 return ((void *) pa);
2460 va = kmem_alloc_nofault(kernel_map, size);
2462 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2464 for (tmpva = va; size > 0;) {
2465 moea_kenter_attr(mmu, tmpva, ppa, ma);
2472 return ((void *)(va + offset));
2476 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2478 vm_offset_t base, offset;
2481 * If this is outside kernel virtual space, then it's a
2482 * battable entry and doesn't require unmapping
2484 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2485 base = trunc_page(va);
2486 offset = va & PAGE_MASK;
2487 size = roundup(offset + size, PAGE_SIZE);
2488 kmem_free(kernel_map, base, size);
2493 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2495 struct pvo_entry *pvo;
2502 lim = round_page(va);
2503 len = MIN(lim - va, sz);
2504 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2506 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2508 moea_syncicache(pa, len);