2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * Since the information managed by this module is also stored by the
100 * logical address mapping module, this module may throw away valid virtual
101 * to physical mappings at almost any time. However, invalidations of
102 * mappings must be done as requested.
104 * In order to cope with hardware architectures which make virtual to
105 * physical map invalidates expensive, this module may delay invalidate
106 * reduced protection operations until such time as they are actually
107 * necessary. This module is given full information as to which processors
108 * are currently using which maps, and to when physical maps must be made
112 #include "opt_kstack_pages.h"
114 #include <sys/param.h>
115 #include <sys/kernel.h>
116 #include <sys/queue.h>
117 #include <sys/cpuset.h>
119 #include <sys/lock.h>
120 #include <sys/msgbuf.h>
121 #include <sys/mutex.h>
122 #include <sys/proc.h>
123 #include <sys/rwlock.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #include <sys/systm.h>
127 #include <sys/vmmeter.h>
129 #include <dev/ofw/openfirm.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
141 #include <machine/cpu.h>
142 #include <machine/platform.h>
143 #include <machine/bat.h>
144 #include <machine/frame.h>
145 #include <machine/md_var.h>
146 #include <machine/psl.h>
147 #include <machine/pte.h>
148 #include <machine/smp.h>
149 #include <machine/sr.h>
150 #include <machine/mmuvar.h>
151 #include <machine/trap_aim.h>
157 #define TODO panic("%s: not implemented", __func__);
159 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
160 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
161 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
170 extern unsigned char _etext[];
171 extern unsigned char _end[];
173 extern int dumpsys_minidump;
176 * Map of physical memory regions.
178 static struct mem_region *regions;
179 static struct mem_region *pregions;
180 static u_int phys_avail_count;
181 static int regions_sz, pregions_sz;
182 static struct ofw_map *translations;
185 * Lock for the pteg and pvo tables.
187 struct mtx moea_table_mutex;
188 struct mtx moea_vsid_mutex;
190 /* tlbie instruction synchronization */
191 static struct mtx tlbie_mtx;
196 static struct pteg *moea_pteg_table;
197 u_int moea_pteg_count;
198 u_int moea_pteg_mask;
203 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
204 struct pvo_head moea_pvo_kunmanaged =
205 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
207 static struct rwlock_padalign pvh_global_lock;
209 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
210 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
212 #define BPVO_POOL_SIZE 32768
213 static struct pvo_entry *moea_bpvo_pool;
214 static int moea_bpvo_pool_index = 0;
216 #define VSID_NBPW (sizeof(u_int32_t) * 8)
217 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
219 static boolean_t moea_initialized = FALSE;
224 u_int moea_pte_valid = 0;
225 u_int moea_pte_overflow = 0;
226 u_int moea_pte_replacements = 0;
227 u_int moea_pvo_entries = 0;
228 u_int moea_pvo_enter_calls = 0;
229 u_int moea_pvo_remove_calls = 0;
230 u_int moea_pte_spills = 0;
231 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
233 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
234 &moea_pte_overflow, 0, "");
235 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
236 &moea_pte_replacements, 0, "");
237 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
239 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
240 &moea_pvo_enter_calls, 0, "");
241 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
242 &moea_pvo_remove_calls, 0, "");
243 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
244 &moea_pte_spills, 0, "");
247 * Allocate physical memory for use in moea_bootstrap.
249 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
254 static int moea_pte_insert(u_int, struct pte *);
259 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
260 vm_offset_t, vm_offset_t, u_int, int);
261 static void moea_pvo_remove(struct pvo_entry *, int);
262 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
263 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
268 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
269 vm_prot_t, boolean_t);
270 static void moea_syncicache(vm_offset_t, vm_size_t);
271 static boolean_t moea_query_bit(vm_page_t, int);
272 static u_int moea_clear_bit(vm_page_t, int);
273 static void moea_kremove(mmu_t, vm_offset_t);
274 int moea_pte_spill(vm_offset_t);
277 * Kernel MMU interface
279 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
280 void moea_clear_modify(mmu_t, vm_page_t);
281 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
282 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
283 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
284 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
285 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
287 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
288 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
289 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
290 void moea_init(mmu_t);
291 boolean_t moea_is_modified(mmu_t, vm_page_t);
292 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
293 boolean_t moea_is_referenced(mmu_t, vm_page_t);
294 int moea_ts_referenced(mmu_t, vm_page_t);
295 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
296 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
297 int moea_page_wired_mappings(mmu_t, vm_page_t);
298 void moea_pinit(mmu_t, pmap_t);
299 void moea_pinit0(mmu_t, pmap_t);
300 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
301 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
302 void moea_qremove(mmu_t, vm_offset_t, int);
303 void moea_release(mmu_t, pmap_t);
304 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
305 void moea_remove_all(mmu_t, vm_page_t);
306 void moea_remove_write(mmu_t, vm_page_t);
307 void moea_zero_page(mmu_t, vm_page_t);
308 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
309 void moea_zero_page_idle(mmu_t, vm_page_t);
310 void moea_activate(mmu_t, struct thread *);
311 void moea_deactivate(mmu_t, struct thread *);
312 void moea_cpu_bootstrap(mmu_t, int);
313 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
314 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
315 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
316 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
317 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
318 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
319 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
320 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
321 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
322 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
323 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
325 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev);
327 static mmu_method_t moea_methods[] = {
328 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
329 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
330 MMUMETHOD(mmu_copy_page, moea_copy_page),
331 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
332 MMUMETHOD(mmu_enter, moea_enter),
333 MMUMETHOD(mmu_enter_object, moea_enter_object),
334 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
335 MMUMETHOD(mmu_extract, moea_extract),
336 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
337 MMUMETHOD(mmu_init, moea_init),
338 MMUMETHOD(mmu_is_modified, moea_is_modified),
339 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
340 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
341 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
342 MMUMETHOD(mmu_map, moea_map),
343 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
344 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
345 MMUMETHOD(mmu_pinit, moea_pinit),
346 MMUMETHOD(mmu_pinit0, moea_pinit0),
347 MMUMETHOD(mmu_protect, moea_protect),
348 MMUMETHOD(mmu_qenter, moea_qenter),
349 MMUMETHOD(mmu_qremove, moea_qremove),
350 MMUMETHOD(mmu_release, moea_release),
351 MMUMETHOD(mmu_remove, moea_remove),
352 MMUMETHOD(mmu_remove_all, moea_remove_all),
353 MMUMETHOD(mmu_remove_write, moea_remove_write),
354 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
355 MMUMETHOD(mmu_zero_page, moea_zero_page),
356 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
357 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
358 MMUMETHOD(mmu_activate, moea_activate),
359 MMUMETHOD(mmu_deactivate, moea_deactivate),
360 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
362 /* Internal interfaces */
363 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
364 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
365 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
366 MMUMETHOD(mmu_mapdev, moea_mapdev),
367 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
368 MMUMETHOD(mmu_kextract, moea_kextract),
369 MMUMETHOD(mmu_kenter, moea_kenter),
370 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
371 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
372 MMUMETHOD(mmu_scan_md, moea_scan_md),
373 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
378 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
380 static __inline uint32_t
381 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
386 if (ma != VM_MEMATTR_DEFAULT) {
388 case VM_MEMATTR_UNCACHEABLE:
389 return (PTE_I | PTE_G);
390 case VM_MEMATTR_WRITE_COMBINING:
391 case VM_MEMATTR_WRITE_BACK:
392 case VM_MEMATTR_PREFETCHABLE:
394 case VM_MEMATTR_WRITE_THROUGH:
395 return (PTE_W | PTE_M);
400 * Assume the page is cache inhibited and access is guarded unless
401 * it's in our available memory array.
403 pte_lo = PTE_I | PTE_G;
404 for (i = 0; i < pregions_sz; i++) {
405 if ((pa >= pregions[i].mr_start) &&
406 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
416 tlbie(vm_offset_t va)
419 mtx_lock_spin(&tlbie_mtx);
420 __asm __volatile("ptesync");
421 __asm __volatile("tlbie %0" :: "r"(va));
422 __asm __volatile("eieio; tlbsync; ptesync");
423 mtx_unlock_spin(&tlbie_mtx);
431 for (va = 0; va < 0x00040000; va += 0x00001000) {
432 __asm __volatile("tlbie %0" :: "r"(va));
435 __asm __volatile("tlbsync");
440 va_to_sr(u_int *sr, vm_offset_t va)
442 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
445 static __inline u_int
446 va_to_pteg(u_int sr, vm_offset_t addr)
450 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
452 return (hash & moea_pteg_mask);
455 static __inline struct pvo_head *
456 vm_page_to_pvoh(vm_page_t m)
459 return (&m->md.mdpg_pvoh);
463 moea_attr_clear(vm_page_t m, int ptebit)
466 rw_assert(&pvh_global_lock, RA_WLOCKED);
467 m->md.mdpg_attrs &= ~ptebit;
471 moea_attr_fetch(vm_page_t m)
474 return (m->md.mdpg_attrs);
478 moea_attr_save(vm_page_t m, int ptebit)
481 rw_assert(&pvh_global_lock, RA_WLOCKED);
482 m->md.mdpg_attrs |= ptebit;
486 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
488 if (pt->pte_hi == pvo_pt->pte_hi)
495 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
497 return (pt->pte_hi & ~PTE_VALID) ==
498 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
499 ((va >> ADDR_API_SHFT) & PTE_API) | which);
503 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
506 mtx_assert(&moea_table_mutex, MA_OWNED);
509 * Construct a PTE. Default to IMB initially. Valid bit only gets
510 * set when the real pte is set in memory.
512 * Note: Don't set the valid bit for correct operation of tlb update.
514 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
515 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
520 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
523 mtx_assert(&moea_table_mutex, MA_OWNED);
524 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
528 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
531 mtx_assert(&moea_table_mutex, MA_OWNED);
534 * As shown in Section 7.6.3.2.3
536 pt->pte_lo &= ~ptebit;
541 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
544 mtx_assert(&moea_table_mutex, MA_OWNED);
545 pvo_pt->pte_hi |= PTE_VALID;
548 * Update the PTE as defined in section 7.6.3.1.
549 * Note that the REF/CHG bits are from pvo_pt and thus should have
550 * been saved so this routine can restore them (if desired).
552 pt->pte_lo = pvo_pt->pte_lo;
554 pt->pte_hi = pvo_pt->pte_hi;
560 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
563 mtx_assert(&moea_table_mutex, MA_OWNED);
564 pvo_pt->pte_hi &= ~PTE_VALID;
567 * Force the reg & chg bits back into the PTEs.
572 * Invalidate the pte.
574 pt->pte_hi &= ~PTE_VALID;
579 * Save the reg & chg bits.
581 moea_pte_synch(pt, pvo_pt);
586 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
592 moea_pte_unset(pt, pvo_pt, va);
593 moea_pte_set(pt, pvo_pt);
597 * Quick sort callout for comparing memory regions.
599 static int om_cmp(const void *a, const void *b);
602 om_cmp(const void *a, const void *b)
604 const struct ofw_map *mapa;
605 const struct ofw_map *mapb;
609 if (mapa->om_pa < mapb->om_pa)
611 else if (mapa->om_pa > mapb->om_pa)
618 moea_cpu_bootstrap(mmu_t mmup, int ap)
625 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
626 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
628 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
629 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
635 * Special case for the Wii: don't install the PCI BAT.
637 if (strcmp(installed_platform(), "wii") != 0) {
639 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
640 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
646 __asm __volatile("mtibatu 1,%0" :: "r"(0));
647 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
648 __asm __volatile("mtibatu 2,%0" :: "r"(0));
649 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
650 __asm __volatile("mtibatu 3,%0" :: "r"(0));
653 for (i = 0; i < 16; i++)
654 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
657 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
658 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
665 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
668 phandle_t chosen, mmu;
671 vm_size_t size, physsz, hwphyssz;
672 vm_offset_t pa, va, off;
677 * Set up BAT0 to map the lowest 256 MB area
679 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
680 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
683 * Map PCI memory space.
685 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
686 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
688 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
689 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
691 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
692 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
694 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
695 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
700 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
701 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
704 * Use an IBAT and a DBAT to map the bottom segment of memory
705 * where we are. Turn off instruction relocation temporarily
706 * to prevent faults while reprogramming the IBAT.
709 mtmsr(msr & ~PSL_IR);
710 __asm (".balign 32; \n"
711 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
712 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
713 :: "r"(battable[0].batu), "r"(battable[0].batl));
717 if (strcmp(installed_platform(), "wii") != 0) {
720 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
721 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
727 /* set global direct map flag */
730 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
731 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
733 for (i = 0; i < pregions_sz; i++) {
737 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
738 pregions[i].mr_start,
739 pregions[i].mr_start + pregions[i].mr_size,
740 pregions[i].mr_size);
742 * Install entries into the BAT table to allow all
743 * of physmem to be convered by on-demand BAT entries.
744 * The loop will sometimes set the same battable element
745 * twice, but that's fine since they won't be used for
748 pa = pregions[i].mr_start & 0xf0000000;
749 end = pregions[i].mr_start + pregions[i].mr_size;
751 u_int n = pa >> ADDR_SR_SHFT;
753 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
754 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
755 pa += SEGMENT_LENGTH;
759 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
760 panic("moea_bootstrap: phys_avail too small");
762 phys_avail_count = 0;
765 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
766 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
767 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
768 regions[i].mr_start + regions[i].mr_size,
771 (physsz + regions[i].mr_size) >= hwphyssz) {
772 if (physsz < hwphyssz) {
773 phys_avail[j] = regions[i].mr_start;
774 phys_avail[j + 1] = regions[i].mr_start +
781 phys_avail[j] = regions[i].mr_start;
782 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
784 physsz += regions[i].mr_size;
787 /* Check for overlap with the kernel and exception vectors */
788 for (j = 0; j < 2*phys_avail_count; j+=2) {
789 if (phys_avail[j] < EXC_LAST)
790 phys_avail[j] += EXC_LAST;
792 if (kernelstart >= phys_avail[j] &&
793 kernelstart < phys_avail[j+1]) {
794 if (kernelend < phys_avail[j+1]) {
795 phys_avail[2*phys_avail_count] =
796 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
797 phys_avail[2*phys_avail_count + 1] =
802 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
805 if (kernelend >= phys_avail[j] &&
806 kernelend < phys_avail[j+1]) {
807 if (kernelstart > phys_avail[j]) {
808 phys_avail[2*phys_avail_count] = phys_avail[j];
809 phys_avail[2*phys_avail_count + 1] =
810 kernelstart & ~PAGE_MASK;
814 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
818 physmem = btoc(physsz);
821 * Allocate PTEG table.
824 moea_pteg_count = PTEGCOUNT;
826 moea_pteg_count = 0x1000;
828 while (moea_pteg_count < physmem)
829 moea_pteg_count <<= 1;
831 moea_pteg_count >>= 1;
832 #endif /* PTEGCOUNT */
834 size = moea_pteg_count * sizeof(struct pteg);
835 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
837 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
838 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
839 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
840 moea_pteg_mask = moea_pteg_count - 1;
843 * Allocate pv/overflow lists.
845 size = sizeof(struct pvo_head) * moea_pteg_count;
846 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
848 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
849 for (i = 0; i < moea_pteg_count; i++)
850 LIST_INIT(&moea_pvo_table[i]);
853 * Initialize the lock that synchronizes access to the pteg and pvo
856 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
858 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
860 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
863 * Initialise the unmanaged pvo pool.
865 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
866 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
867 moea_bpvo_pool_index = 0;
870 * Make sure kernel vsid is allocated as well as VSID 0.
872 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
873 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
874 moea_vsid_bitmap[0] |= 1;
877 * Initialize the kernel pmap (which is statically allocated).
879 PMAP_LOCK_INIT(kernel_pmap);
880 for (i = 0; i < 16; i++)
881 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
882 CPU_FILL(&kernel_pmap->pm_active);
883 RB_INIT(&kernel_pmap->pmap_pvo);
886 * Initialize the global pv list lock.
888 rw_init(&pvh_global_lock, "pmap pv global");
891 * Set up the Open Firmware mappings
893 chosen = OF_finddevice("/chosen");
894 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
895 (mmu = OF_instance_to_package(mmui)) != -1 &&
896 (sz = OF_getproplen(mmu, "translations")) != -1) {
898 for (i = 0; phys_avail[i] != 0; i += 2) {
899 if (phys_avail[i + 1] >= sz) {
900 translations = (struct ofw_map *)phys_avail[i];
904 if (translations == NULL)
905 panic("moea_bootstrap: no space to copy translations");
906 bzero(translations, sz);
907 if (OF_getprop(mmu, "translations", translations, sz) == -1)
908 panic("moea_bootstrap: can't get ofw translations");
909 CTR0(KTR_PMAP, "moea_bootstrap: translations");
910 sz /= sizeof(*translations);
911 qsort(translations, sz, sizeof (*translations), om_cmp);
912 for (i = 0; i < sz; i++) {
913 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
914 translations[i].om_pa, translations[i].om_va,
915 translations[i].om_len);
918 * If the mapping is 1:1, let the RAM and device
919 * on-demand BAT tables take care of the translation.
921 if (translations[i].om_va == translations[i].om_pa)
924 /* Enter the pages */
925 for (off = 0; off < translations[i].om_len;
927 moea_kenter(mmup, translations[i].om_va + off,
928 translations[i].om_pa + off);
933 * Calculate the last available physical address.
935 for (i = 0; phys_avail[i + 2] != 0; i += 2)
937 Maxmem = powerpc_btop(phys_avail[i + 1]);
939 moea_cpu_bootstrap(mmup,0);
944 * Set the start and end of kva.
946 virtual_avail = VM_MIN_KERNEL_ADDRESS;
947 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
950 * Allocate a kernel stack with a guard page for thread0 and map it
951 * into the kernel page map.
953 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
954 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
955 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
956 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
957 thread0.td_kstack = va;
958 thread0.td_kstack_pages = KSTACK_PAGES;
959 for (i = 0; i < KSTACK_PAGES; i++) {
960 moea_kenter(mmup, va, pa);
966 * Allocate virtual address space for the message buffer.
968 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
969 msgbufp = (struct msgbuf *)virtual_avail;
971 virtual_avail += round_page(msgbufsize);
972 while (va < virtual_avail) {
973 moea_kenter(mmup, va, pa);
979 * Allocate virtual address space for the dynamic percpu area.
981 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
982 dpcpu = (void *)virtual_avail;
984 virtual_avail += DPCPU_SIZE;
985 while (va < virtual_avail) {
986 moea_kenter(mmup, va, pa);
990 dpcpu_init(dpcpu, 0);
994 * Activate a user pmap. The pmap must be activated before it's address
995 * space can be accessed in any way.
998 moea_activate(mmu_t mmu, struct thread *td)
1003 * Load all the data we need up front to encourage the compiler to
1004 * not issue any loads while we have interrupts disabled below.
1006 pm = &td->td_proc->p_vmspace->vm_pmap;
1007 pmr = pm->pmap_phys;
1009 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1010 PCPU_SET(curpmap, pmr);
1014 moea_deactivate(mmu_t mmu, struct thread *td)
1018 pm = &td->td_proc->p_vmspace->vm_pmap;
1019 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1020 PCPU_SET(curpmap, NULL);
1024 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1026 struct pvo_entry *pvo;
1029 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1033 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1034 pm->pm_stats.wired_count++;
1035 pvo->pvo_vaddr |= PVO_WIRED;
1037 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1038 pm->pm_stats.wired_count--;
1039 pvo->pvo_vaddr &= ~PVO_WIRED;
1046 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1051 dst = VM_PAGE_TO_PHYS(mdst);
1052 src = VM_PAGE_TO_PHYS(msrc);
1054 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1058 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1059 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1062 vm_offset_t a_pg_offset, b_pg_offset;
1065 while (xfersize > 0) {
1066 a_pg_offset = a_offset & PAGE_MASK;
1067 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1068 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1070 b_pg_offset = b_offset & PAGE_MASK;
1071 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1072 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1074 bcopy(a_cp, b_cp, cnt);
1082 * Zero a page of physical memory by temporarily mapping it into the tlb.
1085 moea_zero_page(mmu_t mmu, vm_page_t m)
1087 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1089 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1090 __asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1094 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1096 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1097 void *va = (void *)(pa + off);
1103 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1106 moea_zero_page(mmu, m);
1110 * Map the given physical page at the specified virtual address in the
1111 * target pmap with the protection requested. If specified the page
1112 * will be wired down.
1115 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1119 rw_wlock(&pvh_global_lock);
1121 moea_enter_locked(pmap, va, m, prot, wired);
1122 rw_wunlock(&pvh_global_lock);
1127 * Map the given physical page at the specified virtual address in the
1128 * target pmap with the protection requested. If specified the page
1129 * will be wired down.
1131 * The page queues and pmap must be locked.
1134 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1137 struct pvo_head *pvo_head;
1140 u_int pte_lo, pvo_flags;
1143 if (!moea_initialized) {
1144 pvo_head = &moea_pvo_kunmanaged;
1145 zone = moea_upvo_zone;
1149 pvo_head = vm_page_to_pvoh(m);
1151 zone = moea_mpvo_zone;
1152 pvo_flags = PVO_MANAGED;
1154 if (pmap_bootstrapped)
1155 rw_assert(&pvh_global_lock, RA_WLOCKED);
1156 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1157 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1158 VM_OBJECT_ASSERT_LOCKED(m->object);
1160 /* XXX change the pvo head for fake pages */
1161 if ((m->oflags & VPO_UNMANAGED) != 0) {
1162 pvo_flags &= ~PVO_MANAGED;
1163 pvo_head = &moea_pvo_kunmanaged;
1164 zone = moea_upvo_zone;
1167 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1169 if (prot & VM_PROT_WRITE) {
1171 if (pmap_bootstrapped &&
1172 (m->oflags & VPO_UNMANAGED) == 0)
1173 vm_page_aflag_set(m, PGA_WRITEABLE);
1177 if (prot & VM_PROT_EXECUTE)
1178 pvo_flags |= PVO_EXECUTABLE;
1181 pvo_flags |= PVO_WIRED;
1183 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1187 * Flush the real page from the instruction cache. This has be done
1188 * for all user mappings to prevent information leakage via the
1189 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1190 * mapping for a page.
1192 if (pmap != kernel_pmap && error == ENOENT &&
1193 (pte_lo & (PTE_I | PTE_G)) == 0)
1194 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1198 * Maps a sequence of resident pages belonging to the same object.
1199 * The sequence begins with the given page m_start. This page is
1200 * mapped at the given virtual address start. Each subsequent page is
1201 * mapped at a virtual address that is offset from start by the same
1202 * amount as the page is offset from m_start within the object. The
1203 * last page in the sequence is the page with the largest offset from
1204 * m_start that can be mapped at a virtual address less than the given
1205 * virtual address end. Not every virtual page between start and end
1206 * is mapped; only those for which a resident page exists with the
1207 * corresponding offset from m_start are mapped.
1210 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1211 vm_page_t m_start, vm_prot_t prot)
1214 vm_pindex_t diff, psize;
1216 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1218 psize = atop(end - start);
1220 rw_wlock(&pvh_global_lock);
1222 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1223 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1224 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1225 m = TAILQ_NEXT(m, listq);
1227 rw_wunlock(&pvh_global_lock);
1232 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1236 rw_wlock(&pvh_global_lock);
1238 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1240 rw_wunlock(&pvh_global_lock);
1245 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1247 struct pvo_entry *pvo;
1251 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1255 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1261 * Atomically extract and hold the physical page with the given
1262 * pmap and virtual address pair if that mapping permits the given
1266 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1268 struct pvo_entry *pvo;
1276 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1277 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1278 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1279 (prot & VM_PROT_WRITE) == 0)) {
1280 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1282 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1291 moea_init(mmu_t mmu)
1294 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1295 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1296 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1297 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1298 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1299 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1300 moea_initialized = TRUE;
1304 moea_is_referenced(mmu_t mmu, vm_page_t m)
1308 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1309 ("moea_is_referenced: page %p is not managed", m));
1310 rw_wlock(&pvh_global_lock);
1311 rv = moea_query_bit(m, PTE_REF);
1312 rw_wunlock(&pvh_global_lock);
1317 moea_is_modified(mmu_t mmu, vm_page_t m)
1321 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1322 ("moea_is_modified: page %p is not managed", m));
1325 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1326 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1327 * is clear, no PTEs can have PTE_CHG set.
1329 VM_OBJECT_ASSERT_WLOCKED(m->object);
1330 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1332 rw_wlock(&pvh_global_lock);
1333 rv = moea_query_bit(m, PTE_CHG);
1334 rw_wunlock(&pvh_global_lock);
1339 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1341 struct pvo_entry *pvo;
1345 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1346 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1352 moea_clear_modify(mmu_t mmu, vm_page_t m)
1355 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1356 ("moea_clear_modify: page %p is not managed", m));
1357 VM_OBJECT_ASSERT_WLOCKED(m->object);
1358 KASSERT(!vm_page_xbusied(m),
1359 ("moea_clear_modify: page %p is exclusive busy", m));
1362 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1363 * set. If the object containing the page is locked and the page is
1364 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1366 if ((m->aflags & PGA_WRITEABLE) == 0)
1368 rw_wlock(&pvh_global_lock);
1369 moea_clear_bit(m, PTE_CHG);
1370 rw_wunlock(&pvh_global_lock);
1374 * Clear the write and modified bits in each of the given page's mappings.
1377 moea_remove_write(mmu_t mmu, vm_page_t m)
1379 struct pvo_entry *pvo;
1384 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1385 ("moea_remove_write: page %p is not managed", m));
1388 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1389 * set by another thread while the object is locked. Thus,
1390 * if PGA_WRITEABLE is clear, no page table entries need updating.
1392 VM_OBJECT_ASSERT_WLOCKED(m->object);
1393 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1395 rw_wlock(&pvh_global_lock);
1396 lo = moea_attr_fetch(m);
1398 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1399 pmap = pvo->pvo_pmap;
1401 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1402 pt = moea_pvo_to_pte(pvo, -1);
1403 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1404 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1406 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1407 lo |= pvo->pvo_pte.pte.pte_lo;
1408 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1409 moea_pte_change(pt, &pvo->pvo_pte.pte,
1411 mtx_unlock(&moea_table_mutex);
1416 if ((lo & PTE_CHG) != 0) {
1417 moea_attr_clear(m, PTE_CHG);
1420 vm_page_aflag_clear(m, PGA_WRITEABLE);
1421 rw_wunlock(&pvh_global_lock);
1425 * moea_ts_referenced:
1427 * Return a count of reference bits for a page, clearing those bits.
1428 * It is not necessary for every reference bit to be cleared, but it
1429 * is necessary that 0 only be returned when there are truly no
1430 * reference bits set.
1432 * XXX: The exact number of bits to check and clear is a matter that
1433 * should be tested and standardized at some point in the future for
1434 * optimal aging of shared pages.
1437 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1441 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1442 ("moea_ts_referenced: page %p is not managed", m));
1443 rw_wlock(&pvh_global_lock);
1444 count = moea_clear_bit(m, PTE_REF);
1445 rw_wunlock(&pvh_global_lock);
1450 * Modify the WIMG settings of all mappings for a page.
1453 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1455 struct pvo_entry *pvo;
1456 struct pvo_head *pvo_head;
1461 if ((m->oflags & VPO_UNMANAGED) != 0) {
1462 m->md.mdpg_cache_attrs = ma;
1466 rw_wlock(&pvh_global_lock);
1467 pvo_head = vm_page_to_pvoh(m);
1468 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1470 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1471 pmap = pvo->pvo_pmap;
1473 pt = moea_pvo_to_pte(pvo, -1);
1474 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1475 pvo->pvo_pte.pte.pte_lo |= lo;
1477 moea_pte_change(pt, &pvo->pvo_pte.pte,
1479 if (pvo->pvo_pmap == kernel_pmap)
1482 mtx_unlock(&moea_table_mutex);
1485 m->md.mdpg_cache_attrs = ma;
1486 rw_wunlock(&pvh_global_lock);
1490 * Map a wired page into kernel virtual address space.
1493 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1496 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1500 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1506 if (va < VM_MIN_KERNEL_ADDRESS)
1507 panic("moea_kenter: attempt to enter non-kernel address %#x",
1511 pte_lo = moea_calc_wimg(pa, ma);
1513 PMAP_LOCK(kernel_pmap);
1514 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1515 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1517 if (error != 0 && error != ENOENT)
1518 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1521 PMAP_UNLOCK(kernel_pmap);
1525 * Extract the physical page address associated with the given kernel virtual
1529 moea_kextract(mmu_t mmu, vm_offset_t va)
1531 struct pvo_entry *pvo;
1535 * Allow direct mappings on 32-bit OEA
1537 if (va < VM_MIN_KERNEL_ADDRESS) {
1541 PMAP_LOCK(kernel_pmap);
1542 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1543 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1544 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1545 PMAP_UNLOCK(kernel_pmap);
1550 * Remove a wired page from kernel virtual address space.
1553 moea_kremove(mmu_t mmu, vm_offset_t va)
1556 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1560 * Map a range of physical addresses into kernel virtual address space.
1562 * The value passed in *virt is a suggested virtual address for the mapping.
1563 * Architectures which can support a direct-mapped physical to virtual region
1564 * can return the appropriate address within that region, leaving '*virt'
1565 * unchanged. We cannot and therefore do not; *virt is updated with the
1566 * first usable address after the mapped region.
1569 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1570 vm_paddr_t pa_end, int prot)
1572 vm_offset_t sva, va;
1576 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1577 moea_kenter(mmu, va, pa_start);
1583 * Returns true if the pmap's pv is one of the first
1584 * 16 pvs linked to from this page. This count may
1585 * be changed upwards or downwards in the future; it
1586 * is only necessary that true be returned for a small
1587 * subset of pmaps for proper page aging.
1590 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1593 struct pvo_entry *pvo;
1596 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1597 ("moea_page_exists_quick: page %p is not managed", m));
1600 rw_wlock(&pvh_global_lock);
1601 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1602 if (pvo->pvo_pmap == pmap) {
1609 rw_wunlock(&pvh_global_lock);
1614 * Return the number of managed mappings to the given physical page
1618 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1620 struct pvo_entry *pvo;
1624 if ((m->oflags & VPO_UNMANAGED) != 0)
1626 rw_wlock(&pvh_global_lock);
1627 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1628 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1630 rw_wunlock(&pvh_global_lock);
1634 static u_int moea_vsidcontext;
1637 moea_pinit(mmu_t mmu, pmap_t pmap)
1642 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1643 RB_INIT(&pmap->pmap_pvo);
1646 __asm __volatile("mftb %0" : "=r"(entropy));
1648 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1650 pmap->pmap_phys = pmap;
1654 mtx_lock(&moea_vsid_mutex);
1656 * Allocate some segment registers for this pmap.
1658 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1662 * Create a new value by mutiplying by a prime and adding in
1663 * entropy from the timebase register. This is to make the
1664 * VSID more random so that the PT hash function collides
1665 * less often. (Note that the prime casues gcc to do shifts
1666 * instead of a multiply.)
1668 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1669 hash = moea_vsidcontext & (NPMAPS - 1);
1670 if (hash == 0) /* 0 is special, avoid it */
1673 mask = 1 << (hash & (VSID_NBPW - 1));
1674 hash = (moea_vsidcontext & 0xfffff);
1675 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1676 /* anything free in this bucket? */
1677 if (moea_vsid_bitmap[n] == 0xffffffff) {
1678 entropy = (moea_vsidcontext >> 20);
1681 i = ffs(~moea_vsid_bitmap[n]) - 1;
1683 hash &= 0xfffff & ~(VSID_NBPW - 1);
1686 KASSERT(!(moea_vsid_bitmap[n] & mask),
1687 ("Allocating in-use VSID group %#x\n", hash));
1688 moea_vsid_bitmap[n] |= mask;
1689 for (i = 0; i < 16; i++)
1690 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1691 mtx_unlock(&moea_vsid_mutex);
1695 mtx_unlock(&moea_vsid_mutex);
1696 panic("moea_pinit: out of segments");
1700 * Initialize the pmap associated with process 0.
1703 moea_pinit0(mmu_t mmu, pmap_t pm)
1707 moea_pinit(mmu, pm);
1708 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1712 * Set the physical protection on the specified range of this map as requested.
1715 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1718 struct pvo_entry *pvo, *tpvo, key;
1721 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1722 ("moea_protect: non current pmap"));
1724 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1725 moea_remove(mmu, pm, sva, eva);
1729 rw_wlock(&pvh_global_lock);
1731 key.pvo_vaddr = sva;
1732 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1733 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1734 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1735 if ((prot & VM_PROT_EXECUTE) == 0)
1736 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1739 * Grab the PTE pointer before we diddle with the cached PTE
1742 pt = moea_pvo_to_pte(pvo, -1);
1744 * Change the protection of the page.
1746 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1747 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1750 * If the PVO is in the page table, update that pte as well.
1753 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1754 mtx_unlock(&moea_table_mutex);
1757 rw_wunlock(&pvh_global_lock);
1762 * Map a list of wired pages into kernel virtual address space. This is
1763 * intended for temporary mappings which do not need page modification or
1764 * references recorded. Existing mappings in the region are overwritten.
1767 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1772 while (count-- > 0) {
1773 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1780 * Remove page mappings from kernel virtual address space. Intended for
1781 * temporary mappings entered by moea_qenter.
1784 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1789 while (count-- > 0) {
1790 moea_kremove(mmu, va);
1796 moea_release(mmu_t mmu, pmap_t pmap)
1801 * Free segment register's VSID
1803 if (pmap->pm_sr[0] == 0)
1804 panic("moea_release");
1806 mtx_lock(&moea_vsid_mutex);
1807 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1808 mask = 1 << (idx % VSID_NBPW);
1810 moea_vsid_bitmap[idx] &= ~mask;
1811 mtx_unlock(&moea_vsid_mutex);
1815 * Remove the given range of addresses from the specified map.
1818 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1820 struct pvo_entry *pvo, *tpvo, key;
1822 rw_wlock(&pvh_global_lock);
1824 key.pvo_vaddr = sva;
1825 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1826 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1827 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1828 moea_pvo_remove(pvo, -1);
1831 rw_wunlock(&pvh_global_lock);
1835 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1836 * will reflect changes in pte's back to the vm_page.
1839 moea_remove_all(mmu_t mmu, vm_page_t m)
1841 struct pvo_head *pvo_head;
1842 struct pvo_entry *pvo, *next_pvo;
1845 rw_wlock(&pvh_global_lock);
1846 pvo_head = vm_page_to_pvoh(m);
1847 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1848 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1850 pmap = pvo->pvo_pmap;
1852 moea_pvo_remove(pvo, -1);
1855 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1856 moea_attr_clear(m, PTE_CHG);
1859 vm_page_aflag_clear(m, PGA_WRITEABLE);
1860 rw_wunlock(&pvh_global_lock);
1864 * Allocate a physical page of memory directly from the phys_avail map.
1865 * Can only be called from moea_bootstrap before avail start and end are
1869 moea_bootstrap_alloc(vm_size_t size, u_int align)
1874 size = round_page(size);
1875 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1877 s = (phys_avail[i] + align - 1) & ~(align - 1);
1882 if (s < phys_avail[i] || e > phys_avail[i + 1])
1885 if (s == phys_avail[i]) {
1886 phys_avail[i] += size;
1887 } else if (e == phys_avail[i + 1]) {
1888 phys_avail[i + 1] -= size;
1890 for (j = phys_avail_count * 2; j > i; j -= 2) {
1891 phys_avail[j] = phys_avail[j - 2];
1892 phys_avail[j + 1] = phys_avail[j - 1];
1895 phys_avail[i + 3] = phys_avail[i + 1];
1896 phys_avail[i + 1] = s;
1897 phys_avail[i + 2] = e;
1903 panic("moea_bootstrap_alloc: could not allocate memory");
1907 moea_syncicache(vm_offset_t pa, vm_size_t len)
1909 __syncicache((void *)pa, len);
1913 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1914 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1916 struct pvo_entry *pvo;
1923 moea_pvo_enter_calls++;
1928 * Compute the PTE Group index.
1931 sr = va_to_sr(pm->pm_sr, va);
1932 ptegidx = va_to_pteg(sr, va);
1935 * Remove any existing mapping for this page. Reuse the pvo entry if
1936 * there is a mapping.
1938 mtx_lock(&moea_table_mutex);
1939 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1940 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1941 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1942 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1943 (pte_lo & PTE_PP)) {
1944 mtx_unlock(&moea_table_mutex);
1947 moea_pvo_remove(pvo, -1);
1953 * If we aren't overwriting a mapping, try to allocate.
1955 if (moea_initialized) {
1956 pvo = uma_zalloc(zone, M_NOWAIT);
1958 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1959 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1960 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1961 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1963 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1964 moea_bpvo_pool_index++;
1969 mtx_unlock(&moea_table_mutex);
1974 pvo->pvo_vaddr = va;
1976 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1977 pvo->pvo_vaddr &= ~ADDR_POFF;
1978 if (flags & VM_PROT_EXECUTE)
1979 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1980 if (flags & PVO_WIRED)
1981 pvo->pvo_vaddr |= PVO_WIRED;
1982 if (pvo_head != &moea_pvo_kunmanaged)
1983 pvo->pvo_vaddr |= PVO_MANAGED;
1985 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1987 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1992 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
1995 * Remember if the list was empty and therefore will be the first
1998 if (LIST_FIRST(pvo_head) == NULL)
2000 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2002 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2003 pm->pm_stats.wired_count++;
2004 pm->pm_stats.resident_count++;
2006 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2007 KASSERT(i < 8, ("Invalid PTE index"));
2009 PVO_PTEGIDX_SET(pvo, i);
2011 panic("moea_pvo_enter: overflow");
2012 moea_pte_overflow++;
2014 mtx_unlock(&moea_table_mutex);
2016 return (first ? ENOENT : 0);
2020 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2025 * If there is an active pte entry, we need to deactivate it (and
2026 * save the ref & cfg bits).
2028 pt = moea_pvo_to_pte(pvo, pteidx);
2030 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2031 mtx_unlock(&moea_table_mutex);
2032 PVO_PTEGIDX_CLR(pvo);
2034 moea_pte_overflow--;
2038 * Update our statistics.
2040 pvo->pvo_pmap->pm_stats.resident_count--;
2041 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2042 pvo->pvo_pmap->pm_stats.wired_count--;
2045 * Save the REF/CHG bits into their cache if the page is managed.
2047 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2050 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2052 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2053 (PTE_REF | PTE_CHG));
2058 * Remove this PVO from the PV and pmap lists.
2060 LIST_REMOVE(pvo, pvo_vlink);
2061 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2064 * Remove this from the overflow list and return it to the pool
2065 * if we aren't going to reuse it.
2067 LIST_REMOVE(pvo, pvo_olink);
2068 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2069 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2070 moea_upvo_zone, pvo);
2072 moea_pvo_remove_calls++;
2076 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2081 * We can find the actual pte entry without searching by grabbing
2082 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2083 * noticing the HID bit.
2085 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2086 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2087 pteidx ^= moea_pteg_mask * 8;
2092 static struct pvo_entry *
2093 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2095 struct pvo_entry *pvo;
2100 sr = va_to_sr(pm->pm_sr, va);
2101 ptegidx = va_to_pteg(sr, va);
2103 mtx_lock(&moea_table_mutex);
2104 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2105 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2107 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2111 mtx_unlock(&moea_table_mutex);
2117 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2122 * If we haven't been supplied the ptegidx, calculate it.
2128 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2129 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2130 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2133 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2134 mtx_lock(&moea_table_mutex);
2136 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2137 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2138 "valid pte index", pvo);
2141 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2142 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2143 "pvo but no valid pte", pvo);
2146 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2147 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2148 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2149 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2152 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2154 panic("moea_pvo_to_pte: pvo %p pte does not match "
2155 "pte %p in moea_pteg_table", pvo, pt);
2158 mtx_assert(&moea_table_mutex, MA_OWNED);
2162 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2163 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2164 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2167 mtx_unlock(&moea_table_mutex);
2172 * XXX: THIS STUFF SHOULD BE IN pte.c?
2175 moea_pte_spill(vm_offset_t addr)
2177 struct pvo_entry *source_pvo, *victim_pvo;
2178 struct pvo_entry *pvo;
2187 ptegidx = va_to_pteg(sr, addr);
2190 * Have to substitute some entry. Use the primary hash for this.
2191 * Use low bits of timebase as random generator.
2193 pteg = &moea_pteg_table[ptegidx];
2194 mtx_lock(&moea_table_mutex);
2195 __asm __volatile("mftb %0" : "=r"(i));
2201 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2203 * We need to find a pvo entry for this address.
2205 if (source_pvo == NULL &&
2206 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2207 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2209 * Now found an entry to be spilled into the pteg.
2210 * The PTE is now valid, so we know it's active.
2212 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2215 PVO_PTEGIDX_SET(pvo, j);
2216 moea_pte_overflow--;
2217 mtx_unlock(&moea_table_mutex);
2223 if (victim_pvo != NULL)
2228 * We also need the pvo entry of the victim we are replacing
2229 * so save the R & C bits of the PTE.
2231 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2232 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2234 if (source_pvo != NULL)
2239 if (source_pvo == NULL) {
2240 mtx_unlock(&moea_table_mutex);
2244 if (victim_pvo == NULL) {
2245 if ((pt->pte_hi & PTE_HID) == 0)
2246 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2250 * If this is a secondary PTE, we need to search it's primary
2251 * pvo bucket for the matching PVO.
2253 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2256 * We also need the pvo entry of the victim we are
2257 * replacing so save the R & C bits of the PTE.
2259 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2265 if (victim_pvo == NULL)
2266 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2271 * We are invalidating the TLB entry for the EA we are replacing even
2272 * though it's valid. If we don't, we lose any ref/chg bit changes
2273 * contained in the TLB entry.
2275 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2277 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2278 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2280 PVO_PTEGIDX_CLR(victim_pvo);
2281 PVO_PTEGIDX_SET(source_pvo, i);
2282 moea_pte_replacements++;
2284 mtx_unlock(&moea_table_mutex);
2288 static __inline struct pvo_entry *
2289 moea_pte_spillable_ident(u_int ptegidx)
2292 struct pvo_entry *pvo_walk, *pvo = NULL;
2294 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2295 if (pvo_walk->pvo_vaddr & PVO_WIRED)
2298 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2301 pt = moea_pvo_to_pte(pvo_walk, -1);
2308 mtx_unlock(&moea_table_mutex);
2309 if (!(pt->pte_lo & PTE_REF))
2317 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2320 struct pvo_entry *victim_pvo;
2323 u_int pteg_bkpidx = ptegidx;
2325 mtx_assert(&moea_table_mutex, MA_OWNED);
2328 * First try primary hash.
2330 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2331 if ((pt->pte_hi & PTE_VALID) == 0) {
2332 pvo_pt->pte_hi &= ~PTE_HID;
2333 moea_pte_set(pt, pvo_pt);
2339 * Now try secondary hash.
2341 ptegidx ^= moea_pteg_mask;
2343 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2344 if ((pt->pte_hi & PTE_VALID) == 0) {
2345 pvo_pt->pte_hi |= PTE_HID;
2346 moea_pte_set(pt, pvo_pt);
2351 /* Try again, but this time try to force a PTE out. */
2352 ptegidx = pteg_bkpidx;
2354 victim_pvo = moea_pte_spillable_ident(ptegidx);
2355 if (victim_pvo == NULL) {
2356 ptegidx ^= moea_pteg_mask;
2357 victim_pvo = moea_pte_spillable_ident(ptegidx);
2360 if (victim_pvo == NULL) {
2361 panic("moea_pte_insert: overflow");
2365 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2367 if (pteg_bkpidx == ptegidx)
2368 pvo_pt->pte_hi &= ~PTE_HID;
2370 pvo_pt->pte_hi |= PTE_HID;
2373 * Synchronize the sacrifice PTE with its PVO, then mark both
2374 * invalid. The PVO will be reused when/if the VM system comes
2375 * here after a fault.
2377 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2379 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2380 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2385 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2386 PVO_PTEGIDX_CLR(victim_pvo);
2387 moea_pte_overflow++;
2388 moea_pte_set(pt, pvo_pt);
2390 return (victim_idx & 7);
2394 moea_query_bit(vm_page_t m, int ptebit)
2396 struct pvo_entry *pvo;
2399 rw_assert(&pvh_global_lock, RA_WLOCKED);
2400 if (moea_attr_fetch(m) & ptebit)
2403 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2406 * See if we saved the bit off. If so, cache it and return
2409 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2410 moea_attr_save(m, ptebit);
2416 * No luck, now go through the hard part of looking at the PTEs
2417 * themselves. Sync so that any pending REF/CHG bits are flushed to
2421 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2424 * See if this pvo has a valid PTE. if so, fetch the
2425 * REF/CHG bits from the valid PTE. If the appropriate
2426 * ptebit is set, cache it and return success.
2428 pt = moea_pvo_to_pte(pvo, -1);
2430 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2431 mtx_unlock(&moea_table_mutex);
2432 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2433 moea_attr_save(m, ptebit);
2443 moea_clear_bit(vm_page_t m, int ptebit)
2446 struct pvo_entry *pvo;
2449 rw_assert(&pvh_global_lock, RA_WLOCKED);
2452 * Clear the cached value.
2454 moea_attr_clear(m, ptebit);
2457 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2458 * we can reset the right ones). note that since the pvo entries and
2459 * list heads are accessed via BAT0 and are never placed in the page
2460 * table, we don't have to worry about further accesses setting the
2466 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2467 * valid pte clear the ptebit from the valid pte.
2470 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2471 pt = moea_pvo_to_pte(pvo, -1);
2473 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2474 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2476 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2478 mtx_unlock(&moea_table_mutex);
2480 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2487 * Return true if the physical range is encompassed by the battable[idx]
2490 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2498 * Return immediately if not a valid mapping
2500 if (!(battable[idx].batu & BAT_Vs))
2504 * The BAT entry must be cache-inhibited, guarded, and r/w
2505 * so it can function as an i/o page
2507 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2508 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2512 * The address should be within the BAT range. Assume that the
2513 * start address in the BAT has the correct alignment (thus
2514 * not requiring masking)
2516 start = battable[idx].batl & BAT_PBS;
2517 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2518 end = start | (bat_ble << 15) | 0x7fff;
2520 if ((pa < start) || ((pa + size) > end))
2527 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2532 * This currently does not work for entries that
2533 * overlap 256M BAT segments.
2536 for(i = 0; i < 16; i++)
2537 if (moea_bat_mapped(i, pa, size) == 0)
2544 * Map a set of physical memory pages into the kernel virtual
2545 * address space. Return a pointer to where it is mapped. This
2546 * routine is intended to be used for mapping device memory,
2550 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2553 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2557 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2559 vm_offset_t va, tmpva, ppa, offset;
2562 ppa = trunc_page(pa);
2563 offset = pa & PAGE_MASK;
2564 size = roundup(offset + size, PAGE_SIZE);
2567 * If the physical address lies within a valid BAT table entry,
2568 * return the 1:1 mapping. This currently doesn't work
2569 * for regions that overlap 256M BAT segments.
2571 for (i = 0; i < 16; i++) {
2572 if (moea_bat_mapped(i, pa, size) == 0)
2573 return ((void *) pa);
2576 va = kva_alloc(size);
2578 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2580 for (tmpva = va; size > 0;) {
2581 moea_kenter_attr(mmu, tmpva, ppa, ma);
2588 return ((void *)(va + offset));
2592 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2594 vm_offset_t base, offset;
2597 * If this is outside kernel virtual space, then it's a
2598 * battable entry and doesn't require unmapping
2600 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2601 base = trunc_page(va);
2602 offset = va & PAGE_MASK;
2603 size = roundup(offset + size, PAGE_SIZE);
2604 kva_free(base, size);
2609 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2611 struct pvo_entry *pvo;
2618 lim = round_page(va);
2619 len = MIN(lim - va, sz);
2620 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2622 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2624 moea_syncicache(pa, len);
2633 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2636 if (md->md_vaddr == ~0UL)
2637 return (md->md_paddr + ofs);
2639 return (md->md_vaddr + ofs);
2643 moea_scan_md(mmu_t mmu, struct pmap_md *prev)
2645 static struct pmap_md md;
2646 struct pvo_entry *pvo;
2649 if (dumpsys_minidump) {
2650 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2652 /* 1st: kernel .data and .bss. */
2654 md.md_vaddr = trunc_page((uintptr_t)_etext);
2655 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2658 switch (prev->md_index) {
2660 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2662 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2663 md.md_size = round_page(msgbufp->msg_size);
2666 /* 3rd: kernel VM. */
2667 va = prev->md_vaddr + prev->md_size;
2668 /* Find start of next chunk (from va). */
2669 while (va < virtual_end) {
2670 /* Don't dump the buffer cache. */
2671 if (va >= kmi.buffer_sva &&
2672 va < kmi.buffer_eva) {
2673 va = kmi.buffer_eva;
2676 pvo = moea_pvo_find_va(kernel_pmap,
2677 va & ~ADDR_POFF, NULL);
2679 (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2683 if (va < virtual_end) {
2686 /* Find last page in chunk. */
2687 while (va < virtual_end) {
2688 /* Don't run into the buffer cache. */
2689 if (va == kmi.buffer_sva)
2691 pvo = moea_pvo_find_va(kernel_pmap,
2692 va & ~ADDR_POFF, NULL);
2694 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2698 md.md_size = va - md.md_vaddr;
2706 } else { /* minidumps */
2707 mem_regions(&pregions, &pregions_sz,
2708 ®ions, ®ions_sz);
2711 /* first physical chunk. */
2712 md.md_paddr = pregions[0].mr_start;
2713 md.md_size = pregions[0].mr_size;
2716 } else if (md.md_index < pregions_sz) {
2717 md.md_paddr = pregions[md.md_index].mr_start;
2718 md.md_size = pregions[md.md_index].mr_size;
2722 /* There's no next physical chunk. */