2 * Copyright (c) 2008 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
38 #include <machine/bus.h>
39 #include <machine/cpu.h>
40 #include <machine/hid.h>
41 #include <machine/intr_machdep.h>
42 #include <machine/pcb.h>
43 #include <machine/psl.h>
44 #include <machine/smp.h>
45 #include <machine/spr.h>
46 #include <machine/trap_aim.h>
48 #include <dev/ofw/openfirm.h>
49 #include <machine/ofw_machdep.h>
53 static register_t bsp_state[8] __aligned(8);
55 static void cpudep_save_config(void *dummy);
56 SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
59 cpudep_ap_early_bootstrap(void)
63 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
66 switch (mfpvr() >> 16) {
70 /* Restore HID4 and HID5, which are necessary for the MMU */
72 __asm __volatile("ld %0, 16(%2); sync; isync; \
73 mtspr %1, %0; sync; isync;"
74 : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state));
75 __asm __volatile("ld %0, 24(%2); sync; isync; \
76 mtspr %1, %0; sync; isync;"
77 : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state));
84 cpudep_ap_bootstrap(void)
88 msr = PSL_KERNSET & ~PSL_EE;
91 curthread_reg = pcpup->pc_curthread = pcpup->pc_idlethread;
92 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
93 sp = pcpup->pc_curpcb->pcb_sp;
99 mpc74xx_l2_enable(register_t l2cr_config)
104 vers = mfpvr() >> 16;
115 ccr = mfspr(SPR_L2CR);
119 /* Configure L2 cache. */
120 ccr = l2cr_config & ~L2CR_L2E;
121 mtspr(SPR_L2CR, ccr | L2CR_L2I);
123 ccr = mfspr(SPR_L2CR);
126 mtspr(SPR_L2CR, l2cr_config);
129 return (l2cr_config);
133 mpc745x_l3_enable(register_t l3cr_config)
137 ccr = mfspr(SPR_L3CR);
141 /* Configure L3 cache. */
142 ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN);
143 mtspr(SPR_L3CR, ccr);
144 ccr |= 0x4000000; /* Magic, but documented. */
145 mtspr(SPR_L3CR, ccr);
147 mtspr(SPR_L3CR, ccr);
148 mtspr(SPR_L3CR, ccr | L3CR_L3I);
149 while (mfspr(SPR_L3CR) & L3CR_L3I)
151 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN);
154 mtspr(SPR_L3CR, ccr);
158 mtspr(SPR_L3CR, ccr);
165 mpc74xx_l1d_enable(void)
169 hid = mfspr(SPR_HID0);
173 /* Enable L1 D-cache */
176 mtspr(SPR_HID0, hid | HID0_DCFI);
183 mpc74xx_l1i_enable(void)
187 hid = mfspr(SPR_HID0);
191 /* Enable L1 I-cache */
194 mtspr(SPR_HID0, hid | HID0_ICFI);
201 cpudep_save_config(void *dummy)
205 vers = mfpvr() >> 16;
212 bsp_state[0] = mfspr(SPR_HID0);
213 bsp_state[1] = mfspr(SPR_HID1);
214 bsp_state[2] = mfspr(SPR_HID4);
215 bsp_state[3] = mfspr(SPR_HID5);
217 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
218 : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));
219 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
220 : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));
221 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
222 : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));
223 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
224 : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
231 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
232 if (mfmsr() & PSL_HV) {
233 bsp_state[0] = mfspr(SPR_HID0);
234 bsp_state[1] = mfspr(SPR_HID1);
235 bsp_state[2] = mfspr(SPR_HID4);
236 bsp_state[3] = mfspr(SPR_HID6);
238 bsp_state[4] = mfspr(SPR_CELL_TSCR);
242 bsp_state[5] = mfspr(SPR_CELL_TSRL);
248 /* Only MPC745x CPUs have an L3 cache. */
249 bsp_state[3] = mfspr(SPR_L3CR);
256 bsp_state[2] = mfspr(SPR_L2CR);
257 bsp_state[1] = mfspr(SPR_HID1);
258 bsp_state[0] = mfspr(SPR_HID0);
269 vers = mfpvr() >> 16;
276 __asm __volatile("mtspr 311,%0" :: "r"(0));
280 * The 970 has strange rules about how to update HID registers.
281 * See Table 2-3, 970MP manual
284 __asm __volatile("mtasr %0; sync" :: "r"(0));
289 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
290 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
292 : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state));
293 __asm __volatile("ld %0, 8(%2); sync; isync; \
294 mtspr %1, %0; mtspr %1, %0; sync; isync"
295 : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state));
296 __asm __volatile("ld %0, 16(%2); sync; isync; \
297 mtspr %1, %0; sync; isync;"
298 : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state));
299 __asm __volatile("ld %0, 24(%2); sync; isync; \
300 mtspr %1, %0; sync; isync;"
301 : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state));
306 #ifdef NOTYET /* Causes problems if in instruction stream on 970 */
307 if (mfmsr() & PSL_HV) {
308 mtspr(SPR_HID0, bsp_state[0]);
309 mtspr(SPR_HID1, bsp_state[1]);
310 mtspr(SPR_HID4, bsp_state[2]);
311 mtspr(SPR_HID6, bsp_state[3]);
313 mtspr(SPR_CELL_TSCR, bsp_state[4]);
317 mtspr(SPR_CELL_TSRL, bsp_state[5]);
323 /* Only MPC745x CPUs have an L3 cache. */
324 reg = mpc745x_l3_enable(bsp_state[3]);
331 /* XXX: Program the CPU ID into PIR */
332 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
337 mtspr(SPR_HID0, bsp_state[0]); isync();
338 mtspr(SPR_HID1, bsp_state[1]); isync();
340 reg = mpc74xx_l2_enable(bsp_state[2]);
341 reg = mpc74xx_l1d_enable();
342 reg = mpc74xx_l1i_enable();
347 if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */
350 printf("WARNING: Unknown CPU type. Cache performace may be "