2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
39 * #include <powerpc/aim/trap_subr.S>
43 * Save/restore segment registers
45 #define RESTORE_SRS(pmap,sr) mtsr 0,sr; \
46 lwz sr,1*4(pmap); mtsr 1,sr; \
47 lwz sr,2*4(pmap); mtsr 2,sr; \
48 lwz sr,3*4(pmap); mtsr 3,sr; \
49 lwz sr,4*4(pmap); mtsr 4,sr; \
50 lwz sr,5*4(pmap); mtsr 5,sr; \
51 lwz sr,6*4(pmap); mtsr 6,sr; \
52 lwz sr,7*4(pmap); mtsr 7,sr; \
53 lwz sr,8*4(pmap); mtsr 8,sr; \
54 lwz sr,9*4(pmap); mtsr 9,sr; \
55 lwz sr,10*4(pmap); mtsr 10,sr; \
56 lwz sr,11*4(pmap); mtsr 11,sr; \
57 /* Skip segment 12 (USER_SR), which is restored differently */ \
58 lwz sr,13*4(pmap); mtsr 13,sr; \
59 lwz sr,14*4(pmap); mtsr 14,sr; \
60 lwz sr,15*4(pmap); mtsr 15,sr; isync;
63 * User SRs are loaded through a pointer to the current pmap.
65 #define RESTORE_USER_SRS(pmap,sr) \
67 lwz pmap,PC_CURPMAP(pmap); \
68 lwzu sr,PM_SR(pmap); \
69 RESTORE_SRS(pmap,sr) \
71 lwz sr,12*4(pmap); mtsr 12,sr
74 * Kernel SRs are loaded directly from kernel_pmap_
76 #define RESTORE_KERN_SRS(pmap,sr) \
77 lis pmap,CNAME(kernel_pmap_store)@ha; \
78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
82 * FRAME_SETUP assumes:
85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
91 * SRR0/1 as at start of trap
93 #define FRAME_SETUP(savearea) \
94 /* Have to enable translation to allow access of kernel stack: */ \
97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
102 mtmsr %r30; /* stack can now be accessed */ \
104 mfsprg1 %r31; /* get saved SP */ \
105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \
106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \
107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \
108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \
109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \
110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \
112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \
117 stw %r4, FRAME_4+8(%r1); \
118 stw %r5, FRAME_5+8(%r1); \
119 stw %r6, FRAME_6+8(%r1); \
120 stw %r7, FRAME_7+8(%r1); \
121 stw %r8, FRAME_8+8(%r1); \
122 stw %r9, FRAME_9+8(%r1); \
123 stw %r10, FRAME_10+8(%r1); \
124 stw %r11, FRAME_11+8(%r1); \
125 stw %r12, FRAME_12+8(%r1); \
126 stw %r13, FRAME_13+8(%r1); \
127 stw %r14, FRAME_14+8(%r1); \
128 stw %r15, FRAME_15+8(%r1); \
129 stw %r16, FRAME_16+8(%r1); \
130 stw %r17, FRAME_17+8(%r1); \
131 stw %r18, FRAME_18+8(%r1); \
132 stw %r19, FRAME_19+8(%r1); \
133 stw %r20, FRAME_20+8(%r1); \
134 stw %r21, FRAME_21+8(%r1); \
135 stw %r22, FRAME_22+8(%r1); \
136 stw %r23, FRAME_23+8(%r1); \
137 stw %r24, FRAME_24+8(%r1); \
138 stw %r25, FRAME_25+8(%r1); \
139 stw %r26, FRAME_26+8(%r1); \
140 stw %r27, FRAME_27+8(%r1); \
141 stw %r28, FRAME_28+8(%r1); \
142 stw %r29, FRAME_29+8(%r1); \
143 stw %r30, FRAME_30+8(%r1); \
144 stw %r31, FRAME_31+8(%r1); \
145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
153 stw %r4, FRAME_CTR+8(1); \
154 stw %r5, FRAME_EXC+8(1); \
155 stw %r28,FRAME_AIM_DAR+8(1); \
156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
157 stw %r30,FRAME_SRR0+8(1); \
158 stw %r31,FRAME_SRR1+8(1); \
159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */
161 #define FRAME_LEAVE(savearea) \
162 /* Disable exceptions: */ \
164 andi. %r2,%r2,~PSL_EE@l; \
167 /* Now restore regs: */ \
168 lwz %r2,FRAME_SRR0+8(%r1); \
169 lwz %r3,FRAME_SRR1+8(%r1); \
170 lwz %r4,FRAME_CTR+8(%r1); \
171 lwz %r5,FRAME_XER+8(%r1); \
172 lwz %r6,FRAME_LR+8(%r1); \
174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
176 lwz %r7,FRAME_CR+8(%r1); \
180 mtsprg1 %r7; /* save cr */ \
181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \
182 lwz %r30,FRAME_30+8(%r1); \
183 lwz %r29,FRAME_29+8(%r1); \
184 lwz %r28,FRAME_28+8(%r1); \
185 lwz %r27,FRAME_27+8(%r1); \
186 lwz %r26,FRAME_26+8(%r1); \
187 lwz %r25,FRAME_25+8(%r1); \
188 lwz %r24,FRAME_24+8(%r1); \
189 lwz %r23,FRAME_23+8(%r1); \
190 lwz %r22,FRAME_22+8(%r1); \
191 lwz %r21,FRAME_21+8(%r1); \
192 lwz %r20,FRAME_20+8(%r1); \
193 lwz %r19,FRAME_19+8(%r1); \
194 lwz %r18,FRAME_18+8(%r1); \
195 lwz %r17,FRAME_17+8(%r1); \
196 lwz %r16,FRAME_16+8(%r1); \
197 lwz %r15,FRAME_15+8(%r1); \
198 lwz %r14,FRAME_14+8(%r1); \
199 lwz %r13,FRAME_13+8(%r1); \
200 lwz %r12,FRAME_12+8(%r1); \
201 lwz %r11,FRAME_11+8(%r1); \
202 lwz %r10,FRAME_10+8(%r1); \
203 lwz %r9, FRAME_9+8(%r1); \
204 lwz %r8, FRAME_8+8(%r1); \
205 lwz %r7, FRAME_7+8(%r1); \
206 lwz %r6, FRAME_6+8(%r1); \
207 lwz %r5, FRAME_5+8(%r1); \
208 lwz %r4, FRAME_4+8(%r1); \
209 lwz %r3, FRAME_3+8(%r1); \
210 lwz %r2, FRAME_2+8(%r1); \
211 lwz %r0, FRAME_0+8(%r1); \
212 lwz %r1, FRAME_1+8(%r1); \
213 /* Can't touch %r1 from here on */ \
214 mtsprg2 %r2; /* save r2 & r3 */ \
216 /* Disable translation, machine check and recoverability: */ \
218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
221 /* Decide whether we return to user mode: */ \
223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \
225 bf 17,1f; /* branch if PSL_PR is false */ \
226 /* Restore user SRs */ \
227 RESTORE_USER_SRS(%r2,%r3); \
228 1: mfsprg1 %r2; /* restore cr */ \
231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
235 /* Make sure HV bit of MSR propagated to SRR1 */ \
240 mfsprg2 %r2; /* restore r2 & r3 */ \
244 * The next two routines are 64-bit glue code. The first is used to test if
245 * we are on a 64-bit system. By copying it to the illegal instruction
246 * handler, we can test for 64-bit mode by trying to execute a 64-bit
247 * instruction and seeing what happens. The second gets copied in front
248 * of all the other handlers to restore 32-bit bridge mode when traps
252 /* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */
254 .globl CNAME(testppc64),CNAME(testppc64size)
266 CNAME(testppc64size) = .-CNAME(testppc64)
269 /* 64-bit bridge mode restore snippet. Gets copied in front of everything else
270 * on 64-bit systems. */
272 .globl CNAME(restorebridge),CNAME(restorebridgesize)
273 CNAME(restorebridge):
280 CNAME(restorebridgesize) = .-CNAME(restorebridge)
284 * Processor reset exception handler. These are typically
285 * the first instructions the processor executes after a
286 * software reset. We do this in two bits so that we are
287 * not still hanging around in the trap handling region
288 * once the MMU is turned on.
290 .globl CNAME(rstcode), CNAME(rstsize)
293 CNAME(rstsize) = . - CNAME(rstcode)
302 addi %r1,%r1,(124-16)@l
305 bla CNAME(cpudep_ap_early_bootstrap)
306 bla CNAME(pmap_cpu_bootstrap)
307 bla CNAME(cpudep_ap_bootstrap)
309 bla CNAME(machdep_ap_bootstrap)
311 /* Should not be reached */
317 * This code gets copied to all the trap vectors
318 * (except ISI/DSI, ALI, and the interrupts)
321 .globl CNAME(trapcode),CNAME(trapsize)
323 mtsprg1 %r1 /* save SP */
324 mflr %r1 /* Save the old LR in r1 */
325 mtsprg2 %r1 /* And then in SPRG2 */
326 li %r1, 0x20 /* How to get the vector from LR */
327 bla generictrap /* LR & SPRG3 is exception # */
328 CNAME(trapsize) = .-CNAME(trapcode)
331 * 64-bit version of trapcode. Identical, except it calls generictrap64.
333 .globl CNAME(trapcode64)
335 mtsprg1 %r1 /* save SP */
336 mflr %r1 /* Save the old LR in r1 */
337 mtsprg2 %r1 /* And then in SPRG2 */
338 li %r1, 0x20 /* How to get the vector from LR */
339 bla generictrap64 /* LR & SPRG3 is exception # */
342 * For ALI: has to save DSISR and DAR
344 .globl CNAME(alitrap),CNAME(alisize)
346 mtsprg1 %r1 /* save SP */
348 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
349 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
350 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
351 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
354 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
355 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
356 mfsprg1 %r1 /* restore SP, in case of branch */
357 mflr %r28 /* save LR */
358 mfcr %r29 /* save CR */
360 /* Put our exception vector in SPRG3 */
364 /* Test whether we already had PR set */
368 CNAME(alisize) = .-CNAME(alitrap)
371 * G2 specific: instuction TLB miss.
373 .globl CNAME(imisstrap),CNAME(imisssize)
375 mfspr %r2, SPR_HASH1 /* get first pointer */
376 addi %r1, 0, 8 /* load 8 for counter */
377 mfctr %r0 /* save counter */
378 mfspr %r3, SPR_ICMP /* get first compare value */
379 addi %r2, %r2, -8 /* pre dec the pointer */
381 mtctr %r1 /* load counter */
383 lwzu %r1, 8(%r2) /* get next pte */
384 cmp 0, %r1, %r3 /* see if found pte */
385 bdnzf 2, im1 /* dec count br if cmp ne and if
387 bne instr_sec_hash /* if not found set up second hash
389 lwz %r1, +4(%r2) /* load tlb entry lower-word */
390 andi. %r3, %r1, 8 /* check G bit */
391 bne do_isi_prot /* if guarded, take an ISI */
392 mtctr %r0 /* restore counter */
393 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */
394 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
395 mtcrf 0x80, %r3 /* restore CR0 */
396 mtspr SPR_RPA, %r1 /* set the pte */
397 ori %r1, %r1, 0x100 /* set reference bit */
398 srwi %r1, %r1, 8 /* get byte 7 of pte */
399 tlbli %r0 /* load the itlb */
400 stb %r1, +6(%r2) /* update page table */
401 rfi /* return to executing program */
404 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
405 bne do_isi /* if so, go to ISI interrupt */
406 mfspr %r2, SPR_HASH2 /* get the second pointer */
407 ori %r3, %r3, 0x0040 /* change the compare value */
408 addi %r1, %r0, 8 /* load 8 for counter */
409 addi %r2, %r2, -8 /* pre dec for update on load */
410 b im0 /* try second hash */
412 /* Create a faked ISI interrupt as the address was not found */
414 mfspr %r3, SPR_SRR1 /* get srr1 */
415 andi. %r2, %r3, 0xffff /* clean upper srr1 */
416 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot
420 mfspr %r3, SPR_SRR1 /* get srr1 */
421 andi. %r2, %r3, 0xffff /* clean srr1 */
422 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte
425 mtctr %r0 /* restore counter */
426 mtspr SPR_SRR1, %r2 /* set srr1 */
427 mfmsr %r0 /* get msr */
428 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
429 mtcrf 0x80, %r3 /* restore CR0 */
430 mtmsr %r0 /* flip back to the native gprs */
431 ba EXC_ISI /* go to instr. access interrupt */
433 CNAME(imisssize) = .-CNAME(imisstrap)
436 * G2 specific: data load TLB miss.
438 .globl CNAME(dlmisstrap),CNAME(dlmisssize)
440 mfspr %r2, SPR_HASH1 /* get first pointer */
441 addi %r1, 0, 8 /* load 8 for counter */
442 mfctr %r0 /* save counter */
443 mfspr %r3, SPR_DCMP /* get first compare value */
444 addi %r2, %r2, -8 /* pre dec the pointer */
446 mtctr %r1 /* load counter */
448 lwzu %r1, 8(%r2) /* get next pte */
449 cmp 0, 0, %r1, %r3 /* see if found pte */
450 bdnzf 2, dm1 /* dec count br if cmp ne and if
452 bne data_sec_hash /* if not found set up second hash
454 lwz %r1, +4(%r2) /* load tlb entry lower-word */
455 mtctr %r0 /* restore counter */
456 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
457 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
458 mtcrf 0x80, %r3 /* restore CR0 */
459 mtspr SPR_RPA, %r1 /* set the pte */
460 ori %r1, %r1, 0x100 /* set reference bit */
461 srwi %r1, %r1, 8 /* get byte 7 of pte */
462 tlbld %r0 /* load the dtlb */
463 stb %r1, +6(%r2) /* update page table */
464 rfi /* return to executing program */
467 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
468 bne do_dsi /* if so, go to DSI interrupt */
469 mfspr %r2, SPR_HASH2 /* get the second pointer */
470 ori %r3, %r3, 0x0040 /* change the compare value */
471 addi %r1, 0, 8 /* load 8 for counter */
472 addi %r2, %r2, -8 /* pre dec for update on load */
473 b dm0 /* try second hash */
475 CNAME(dlmisssize) = .-CNAME(dlmisstrap)
478 * G2 specific: data store TLB miss.
480 .globl CNAME(dsmisstrap),CNAME(dsmisssize)
482 mfspr %r2, SPR_HASH1 /* get first pointer */
483 addi %r1, 0, 8 /* load 8 for counter */
484 mfctr %r0 /* save counter */
485 mfspr %r3, SPR_DCMP /* get first compare value */
486 addi %r2, %r2, -8 /* pre dec the pointer */
488 mtctr %r1 /* load counter */
490 lwzu %r1, 8(%r2) /* get next pte */
491 cmp 0, 0, %r1, %r3 /* see if found pte */
492 bdnzf 2, ds1 /* dec count br if cmp ne and if
494 bne data_store_sec_hash /* if not found set up second hash
496 lwz %r1, +4(%r2) /* load tlb entry lower-word */
497 andi. %r3, %r1, 0x80 /* check the C-bit */
498 beq data_store_chk_prot /* if (C==0)
499 * go check protection modes */
501 mtctr %r0 /* restore counter */
502 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
503 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
504 mtcrf 0x80, %r3 /* restore CR0 */
505 mtspr SPR_RPA, %r1 /* set the pte */
506 tlbld %r0 /* load the dtlb */
507 rfi /* return to executing program */
510 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
511 bne do_dsi /* if so, go to DSI interrupt */
512 mfspr %r2, SPR_HASH2 /* get the second pointer */
513 ori %r3, %r3, 0x0040 /* change the compare value */
514 addi %r1, 0, 8 /* load 8 for counter */
515 addi %r2, %r2, -8 /* pre dec for update on load */
516 b ds0 /* try second hash */
518 /* Check the protection before setting PTE(c-bit) */
520 rlwinm. %r3,%r1,30,0,1 /* test PP */
521 bge- chk0 /* if (PP == 00 or PP == 01)
523 andi. %r3, %r1, 1 /* test PP[0] */
524 beq+ chk2 /* return if PP[0] == 0 */
525 b do_dsi_prot /* else DSIp */
527 mfspr %r3,SPR_SRR1 /* get old msr */
528 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */
529 beq chk2 /* if (KEY==0) goto chk2: */
530 b do_dsi_prot /* else do_dsi_prot */
532 ori %r1, %r1, 0x180 /* set reference and change bit */
533 sth %r1, 6(%r2) /* update page table */
534 b ds2 /* and back we go */
536 /* Create a faked DSI interrupt as the address was not found */
538 mfspr %r3, SPR_SRR1 /* get srr1 */
539 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
540 * load/store, zero rest */
541 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte
546 mfspr %r3, SPR_SRR1 /* get srr1 */
547 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
548 *load/store, zero rest */
549 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot
553 mtctr %r0 /* restore counter */
554 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */
555 mtspr SPR_SRR1, %r2 /* set srr1 */
556 mtspr SPR_DSISR, %r1 /* load the dsisr */
557 mfspr %r1, SPR_DMISS /* get miss address */
558 rlwinm. %r2,%r2,0,31,31 /* test LE bit */
559 beq dsi2 /* if little endian then: */
560 xor %r1, %r1, 0x07 /* de-mung the data address */
562 mtspr SPR_DAR, %r1 /* put in dar */
563 mfmsr %r0 /* get msr */
564 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
565 mtcrf 0x80, %r3 /* restore CR0 */
566 mtmsr %r0 /* flip back to the native gprs */
567 ba EXC_DSI /* branch to DSI interrupt */
569 CNAME(dsmisssize) = .-CNAME(dsmisstrap)
572 * Similar to the above for DSI
573 * Has to handle BAT spills
574 * and standard pagetable spills
576 .globl CNAME(dsitrap),CNAME(dsisize)
578 mtsprg1 %r1 /* save SP */
580 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
581 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
582 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
583 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
584 mfsprg1 %r1 /* restore SP */
585 mfcr %r29 /* save CR */
586 mfxer %r30 /* save XER */
587 mtsprg2 %r30 /* in SPRG2 */
588 mfsrr1 %r31 /* test kernel mode */
590 bt 17,1f /* branch if PSL_PR is set */
591 mfdar %r31 /* get fault address */
592 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */
595 addis %r31,%r31,CNAME(battable)@ha
596 lwz %r30,CNAME(battable)@l(31)
598 bf 30,1f /* branch if supervisor valid is
601 lwz %r31,CNAME(battable)+4@l(31)
602 /* We randomly use the highest two bat registers here */
613 mfsprg2 %r30 /* restore XER */
615 mtcr %r29 /* restore CR */
618 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */
619 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
620 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
621 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
623 rfi /* return to trapped code */
625 mflr %r28 /* save LR (SP already saved) */
627 CNAME(dsisize) = .-CNAME(dsitrap)
630 * Preamble code for DSI/ISI traps
633 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
639 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
640 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
641 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
642 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
643 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
644 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
645 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
646 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
649 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
650 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
653 /* Try and detect a kernel stack overflow */
656 bt 17,realtrap /* branch is user mode */
657 mfsprg1 %r31 /* get old SP */
658 sub. %r30,%r31,%r30 /* SP - DAR */
660 neg %r30,%r30 /* modulo value */
661 1: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */
662 bge %cr0,realtrap /* no, too far away. */
664 /* Now convert this DSI into a DDB trap. */
666 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
667 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
668 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
669 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
670 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
671 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
672 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
673 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
674 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
675 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
676 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
677 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
681 /* XXX need stack probe here */
683 /* Test whether we already had PR set */
686 mfsprg1 %r1 /* restore SP (might have been
688 bf 17,k_trap /* branch if PSL_PR is false */
690 lwz %r1,PC_CURPCB(%r1)
691 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
695 * generictrap does some standard setup for trap handling to minimize
696 * the code that need be installed in the actual vectors. It expects
697 * the following conditions.
699 * R1 - Trap vector = LR & (0xff00 | R1)
700 * SPRG1 - Original R1 contents
701 * SPRG2 - Original LR
713 /* Save R1 for computing the exception vector */
716 /* Save interesting registers */
718 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
719 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
720 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
721 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
722 mfsprg1 %r1 /* restore SP, in case of branch */
723 mfsprg2 %r28 /* save LR */
724 mfcr %r29 /* save CR */
726 /* Compute the exception vector from the link register */
733 /* Test whether we already had PR set */
738 bf 17,k_trap /* branch if PSL_PR is false */
741 lwz %r1,PC_CURPCB(%r1)
742 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
745 * Now the common trap catching code.
748 FRAME_SETUP(PC_TEMPSAVE)
749 /* Restore USER_SR */
751 lwz %r30,PC_CURPCB(%r30)
752 lwz %r30,PCB_AIM_USR_VSID(%r30)
753 mtsr USER_SR,%r30; sync; isync
754 /* Call C interrupt dispatcher: */
757 bl CNAME(powerpc_interrupt)
758 .globl CNAME(trapexit) /* backtrace code sentinel */
761 /* Disable interrupts: */
763 andi. %r3,%r3,~PSL_EE@l
765 /* Test AST pending: */
766 lwz %r5,FRAME_SRR1+8(%r1)
768 bf 17,1f /* branch if PSL_PR is false */
770 GET_CPUINFO(%r3) /* get per-CPU pointer */
771 lwz %r4, TD_FLAGS(%r2) /* get thread flags value
772 * (r2 is curthread) */
773 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
774 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
777 mfmsr %r3 /* re-enable interrupts */
783 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
785 b trapexit /* test ast ret value ? */
787 FRAME_LEAVE(PC_TEMPSAVE)
789 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */
793 .globl CNAME(rfid_patch)
799 * Deliberate entry to dbtrap
801 .globl CNAME(breakpoint)
806 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
807 mtmsr %r3 /* disable interrupts */
810 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
811 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
812 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
813 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
821 * Now the kdb trap catching code.
824 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
829 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
830 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
832 FRAME_SETUP(PC_DBSAVE)
833 /* Call C trap code: */
835 bl CNAME(db_trap_glue)
838 /* This wasn't for KDB, so switch to real trap: */
839 lwz %r3,FRAME_EXC+8(%r1) /* save exception */
841 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
842 FRAME_LEAVE(PC_DBSAVE)
843 mtsprg1 %r1 /* prepare for entrance to realtrap */
845 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
846 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
847 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
848 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
851 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
852 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
856 FRAME_LEAVE(PC_DBSAVE)
857 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */
862 * In case of KDB we want a separate trap catcher for it
864 .globl CNAME(dblow),CNAME(dbsize)
866 mtsprg1 %r1 /* save SP */
867 mtsprg2 %r29 /* save r29 */
868 mfcr %r29 /* save CR in r29 */
871 bf 17,1f /* branch if privileged */
873 /* Unprivileged case */
874 mtcr %r29 /* put the condition register back */
875 mfsprg2 %r29 /* ... and r29 */
876 mflr %r1 /* save LR */
877 mtsprg2 %r1 /* And then in SPRG2 */
878 li %r1, 0 /* How to get the vector from LR */
880 bla generictrap /* and we look like a generic trap */
882 /* Privileged, so drop to KDB */
884 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
885 mfsprg2 %r28 /* r29 holds cr... */
886 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
887 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
888 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
889 mflr %r28 /* save LR */
891 CNAME(dbsize) = .-CNAME(dblow)