2 /* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
39 * #include <powerpc/aim/trap_subr.S>
43 * Save/restore segment registers
47 * Restore SRs for a pmap
49 * Requires that r28-r31 be scratch, with r28 initialized to the SLB cache
53 * User SRs are loaded through a pointer to the current pmap.
57 ld %r28,PC_USERSLB(%r28)
58 li %r29, 0 /* Set the counter to zero */
64 1: ld %r31, 0(%r28) /* Load SLB entry pointer */
65 cmpli 0, %r31, 0 /* If NULL, stop */
68 ld %r30, 0(%r31) /* Load SLBV */
69 ld %r31, 8(%r31) /* Load SLBE */
70 or %r31, %r31, %r29 /* Set SLBE slot */
71 slbmte %r30, %r31 /* Install SLB entry */
73 addi %r28, %r28, 8 /* Advance pointer */
78 * Kernel SRs are loaded directly from the PCPU fields
82 addi %r28,%r28,PC_KERNSLB
83 li %r29, 0 /* Set the counter to zero */
89 1: cmpli 0, %r29, USER_SLB_SLOT /* Skip the user slot */
92 ld %r31, 8(%r28) /* Load SLBE */
93 cmpli 0, %r31, 0 /* If SLBE is not valid, stop */
95 ld %r30, 0(%r28) /* Load SLBV */
96 slbmte %r30, %r31 /* Install SLB entry */
98 2: addi %r28, %r28, 16 /* Advance pointer */
100 cmpli 0, %r29, 64 /* Repeat if we are not at the end */
105 * FRAME_SETUP assumes:
108 * savearea r27-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
114 * SRR0/1 as at start of trap
116 * NOTE: SPRG1 is never used while the MMU is on, making it safe to reuse
117 * in any real-mode fault handler, including those handling double faults.
119 #define FRAME_SETUP(savearea) \
120 /* Have to enable translation to allow access of kernel stack: */ \
123 std %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
125 std %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
126 mfsprg1 %r31; /* get saved SP (clears SPRG1) */ \
128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
129 mtmsr %r30; /* stack can now be accessed */ \
131 stdu %r31,-(FRAMELEN+288)(%r1); /* save it in the callframe */ \
132 std %r0, FRAME_0+48(%r1); /* save r0 in the trapframe */ \
133 std %r31,FRAME_1+48(%r1); /* save SP " " */ \
134 std %r2, FRAME_2+48(%r1); /* save r2 " " */ \
135 std %r28,FRAME_LR+48(%r1); /* save LR " " */ \
136 std %r29,FRAME_CR+48(%r1); /* save CR " " */ \
138 ld %r27,(savearea+CPUSAVE_R27)(%r2); /* get saved r27 */ \
139 ld %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
140 ld %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
141 ld %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
142 ld %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
143 std %r3, FRAME_3+48(%r1); /* save r3-r31 */ \
144 std %r4, FRAME_4+48(%r1); \
145 std %r5, FRAME_5+48(%r1); \
146 std %r6, FRAME_6+48(%r1); \
147 std %r7, FRAME_7+48(%r1); \
148 std %r8, FRAME_8+48(%r1); \
149 std %r9, FRAME_9+48(%r1); \
150 std %r10, FRAME_10+48(%r1); \
151 std %r11, FRAME_11+48(%r1); \
152 std %r12, FRAME_12+48(%r1); \
153 std %r13, FRAME_13+48(%r1); \
154 std %r14, FRAME_14+48(%r1); \
155 std %r15, FRAME_15+48(%r1); \
156 std %r16, FRAME_16+48(%r1); \
157 std %r17, FRAME_17+48(%r1); \
158 std %r18, FRAME_18+48(%r1); \
159 std %r19, FRAME_19+48(%r1); \
160 std %r20, FRAME_20+48(%r1); \
161 std %r21, FRAME_21+48(%r1); \
162 std %r22, FRAME_22+48(%r1); \
163 std %r23, FRAME_23+48(%r1); \
164 std %r24, FRAME_24+48(%r1); \
165 std %r25, FRAME_25+48(%r1); \
166 std %r26, FRAME_26+48(%r1); \
167 std %r27, FRAME_27+48(%r1); \
168 std %r28, FRAME_28+48(%r1); \
169 std %r29, FRAME_29+48(%r1); \
170 std %r30, FRAME_30+48(%r1); \
171 std %r31, FRAME_31+48(%r1); \
172 ld %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
173 ld %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
174 ld %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
175 ld %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
179 std %r3, FRAME_XER+48(1); /* save xer/ctr/exc */ \
180 std %r4, FRAME_CTR+48(1); \
181 std %r5, FRAME_EXC+48(1); \
182 std %r28,FRAME_AIM_DAR+48(1); \
183 std %r29,FRAME_AIM_DSISR+48(1); /* save dsisr/srr0/srr1 */ \
184 std %r30,FRAME_SRR0+48(1); \
185 std %r31,FRAME_SRR1+48(1); \
186 ld %r13,PC_CURTHREAD(%r2) /* set kernel curthread */
188 #define FRAME_LEAVE(savearea) \
189 /* Disable exceptions: */ \
191 andi. %r2,%r2,~PSL_EE@l; \
194 /* Now restore regs: */ \
195 ld %r2,FRAME_SRR0+48(%r1); \
196 ld %r3,FRAME_SRR1+48(%r1); \
197 ld %r4,FRAME_CTR+48(%r1); \
198 ld %r5,FRAME_XER+48(%r1); \
199 ld %r6,FRAME_LR+48(%r1); \
201 std %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
202 std %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
203 ld %r7,FRAME_CR+48(%r1); \
207 mtsprg2 %r7; /* save cr */ \
208 ld %r31,FRAME_31+48(%r1); /* restore r0-31 */ \
209 ld %r30,FRAME_30+48(%r1); \
210 ld %r29,FRAME_29+48(%r1); \
211 ld %r28,FRAME_28+48(%r1); \
212 ld %r27,FRAME_27+48(%r1); \
213 ld %r26,FRAME_26+48(%r1); \
214 ld %r25,FRAME_25+48(%r1); \
215 ld %r24,FRAME_24+48(%r1); \
216 ld %r23,FRAME_23+48(%r1); \
217 ld %r22,FRAME_22+48(%r1); \
218 ld %r21,FRAME_21+48(%r1); \
219 ld %r20,FRAME_20+48(%r1); \
220 ld %r19,FRAME_19+48(%r1); \
221 ld %r18,FRAME_18+48(%r1); \
222 ld %r17,FRAME_17+48(%r1); \
223 ld %r16,FRAME_16+48(%r1); \
224 ld %r15,FRAME_15+48(%r1); \
225 ld %r14,FRAME_14+48(%r1); \
226 ld %r13,FRAME_13+48(%r1); \
227 ld %r12,FRAME_12+48(%r1); \
228 ld %r11,FRAME_11+48(%r1); \
229 ld %r10,FRAME_10+48(%r1); \
230 ld %r9, FRAME_9+48(%r1); \
231 ld %r8, FRAME_8+48(%r1); \
232 ld %r7, FRAME_7+48(%r1); \
233 ld %r6, FRAME_6+48(%r1); \
234 ld %r5, FRAME_5+48(%r1); \
235 ld %r4, FRAME_4+48(%r1); \
236 ld %r3, FRAME_3+48(%r1); \
237 ld %r2, FRAME_2+48(%r1); \
238 ld %r0, FRAME_0+48(%r1); \
239 ld %r1, FRAME_1+48(%r1); \
240 /* Can't touch %r1 from here on */ \
241 mtsprg3 %r3; /* save r3 */ \
242 /* Disable translation, machine check and recoverability: */ \
244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
247 /* Decide whether we return to user mode: */ \
249 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); \
251 bf 17,1f; /* branch if PSL_PR is false */ \
252 /* Restore user SRs */ \
254 std %r27,(savearea+CPUSAVE_R27)(%r3); \
255 std %r28,(savearea+CPUSAVE_R28)(%r3); \
256 std %r29,(savearea+CPUSAVE_R29)(%r3); \
257 std %r30,(savearea+CPUSAVE_R30)(%r3); \
258 std %r31,(savearea+CPUSAVE_R31)(%r3); \
259 mflr %r27; /* preserve LR */ \
260 bl restore_usersrs; /* uses r28-r31 */ \
262 ld %r31,(savearea+CPUSAVE_R31)(%r3); \
263 ld %r30,(savearea+CPUSAVE_R30)(%r3); \
264 ld %r29,(savearea+CPUSAVE_R29)(%r3); \
265 ld %r28,(savearea+CPUSAVE_R28)(%r3); \
266 ld %r27,(savearea+CPUSAVE_R27)(%r3); \
267 1: mfsprg2 %r3; /* restore cr */ \
270 ld %r3,(savearea+CPUSAVE_SRR0)(%r3); /* restore srr0 */ \
273 ld %r3,(savearea+CPUSAVE_SRR1)(%r3); /* restore srr1 */ \
275 mfsprg3 %r3 /* restore r3 */
279 .globl dtrace_invop_calltrap_addr
281 .type dtrace_invop_calltrap_addr, @object
282 .size dtrace_invop_calltrap_addr, 8
283 dtrace_invop_calltrap_addr:
292 * Processor reset exception handler. These are typically
293 * the first instructions the processor executes after a
294 * software reset. We do this in two bits so that we are
295 * not still hanging around in the trap handling region
296 * once the MMU is turned on.
298 .globl CNAME(rstcode), CNAME(rstsize)
300 /* Explicitly set MSR[SF] */
308 CNAME(rstsize) = . - CNAME(rstcode)
311 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
312 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
315 ld %r2,tocbase@l(%r3)
317 bl CNAME(cpudep_ap_early_bootstrap) /* Set PCPU */
320 bl CNAME(pmap_cpu_bootstrap) /* Turn on virtual memory */
322 bl CNAME(cpudep_ap_bootstrap) /* Set up PCPU and stack */
324 mr %r1,%r3 /* Use new stack */
325 bl CNAME(machdep_ap_bootstrap) /* And away! */
328 /* Should not be reached */
334 * This code gets copied to all the trap vectors
335 * (except ISI/DSI, ALI, and the interrupts)
338 .globl CNAME(trapcode),CNAME(trapsize)
340 mtsprg1 %r1 /* save SP */
341 mflr %r1 /* Save the old LR in r1 */
342 mtsprg2 %r1 /* And then in SPRG2 */
343 li %r1, 0xA0 /* How to get the vector from LR */
344 bla generictrap /* LR & SPRG3 is exception # */
345 CNAME(trapsize) = .-CNAME(trapcode)
348 * For SLB misses: do special things for the kernel
350 * Note: SPRG1 is always safe to overwrite any time the MMU is on, which is
351 * the only time this can be called.
353 .globl CNAME(slbtrap),CNAME(slbtrapsize)
355 mtsprg1 %r1 /* save SP */
357 std %r2,(PC_SLBSAVE+16)(%r1)
358 mfcr %r2 /* save CR */
359 std %r2,(PC_SLBSAVE+104)(%r1)
360 mfsrr1 %r2 /* test kernel mode */
362 bf 17,1f /* branch if PSL_PR is false */
364 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
366 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2 */
367 mflr %r1 /* Save the old LR in r1 */
368 mtsprg2 %r1 /* And then in SPRG2 */
369 li %r1, 0x80 /* How to get the vector from LR */
370 bla generictrap /* LR & SPRG3 is exception # */
371 1: mflr %r2 /* Save the old LR in r2 */
373 CNAME(slbtrapsize) = .-CNAME(slbtrap)
376 std %r2,(PC_SLBSAVE+136)(%r1) /* old LR */
377 std %r3,(PC_SLBSAVE+24)(%r1) /* save R3 */
379 /* Check if this needs to be handled as a regular trap (userseg miss) */
387 2: /* r2 now contains the fault address */
388 lis %r3,SEGMENT_MASK@highesta
389 ori %r3,%r3,SEGMENT_MASK@highera
391 oris %r3,%r3,SEGMENT_MASK@ha
392 ori %r3,%r3,SEGMENT_MASK@l
393 and %r2,%r2,%r3 /* R2 = segment base address */
394 lis %r3,USER_ADDR@highesta
395 ori %r3,%r3,USER_ADDR@highera
397 oris %r3,%r3,USER_ADDR@ha
398 ori %r3,%r3,USER_ADDR@l
399 cmpd %r2,%r3 /* Compare fault base to USER_ADDR */
402 /* User seg miss, handle as a regular trap */
403 ld %r2,(PC_SLBSAVE+104)(%r1) /* Restore CR */
405 ld %r2,(PC_SLBSAVE+16)(%r1) /* Restore R2,R3 */
406 ld %r3,(PC_SLBSAVE+24)(%r1)
407 ld %r1,(PC_SLBSAVE+136)(%r1) /* Save the old LR in r1 */
408 mtsprg2 %r1 /* And then in SPRG2 */
409 li %r1, 0x80 /* How to get the vector from LR */
410 b generictrap /* Retain old LR using b */
412 3: /* Real kernel SLB miss */
413 std %r0,(PC_SLBSAVE+0)(%r1) /* free all volatile regs */
414 mfsprg1 %r2 /* Old R1 */
415 std %r2,(PC_SLBSAVE+8)(%r1)
416 /* R2,R3 already saved */
417 std %r4,(PC_SLBSAVE+32)(%r1)
418 std %r5,(PC_SLBSAVE+40)(%r1)
419 std %r6,(PC_SLBSAVE+48)(%r1)
420 std %r7,(PC_SLBSAVE+56)(%r1)
421 std %r8,(PC_SLBSAVE+64)(%r1)
422 std %r9,(PC_SLBSAVE+72)(%r1)
423 std %r10,(PC_SLBSAVE+80)(%r1)
424 std %r11,(PC_SLBSAVE+88)(%r1)
425 std %r12,(PC_SLBSAVE+96)(%r1)
426 /* CR already saved */
427 mfxer %r2 /* save XER */
428 std %r2,(PC_SLBSAVE+112)(%r1)
429 mflr %r2 /* save LR (SP already saved) */
430 std %r2,(PC_SLBSAVE+120)(%r1)
431 mfctr %r2 /* save CTR */
432 std %r2,(PC_SLBSAVE+128)(%r1)
435 addi %r1,%r1,PC_SLBSTACK-48+1024
439 ld %r2,tocbase@l(%r3)
444 bl handle_kernel_slb_spill
447 /* Save r28-31, restore r4-r12 */
449 ld %r4,(PC_SLBSAVE+32)(%r1)
450 ld %r5,(PC_SLBSAVE+40)(%r1)
451 ld %r6,(PC_SLBSAVE+48)(%r1)
452 ld %r7,(PC_SLBSAVE+56)(%r1)
453 ld %r8,(PC_SLBSAVE+64)(%r1)
454 ld %r9,(PC_SLBSAVE+72)(%r1)
455 ld %r10,(PC_SLBSAVE+80)(%r1)
456 ld %r11,(PC_SLBSAVE+88)(%r1)
457 ld %r12,(PC_SLBSAVE+96)(%r1)
458 std %r28,(PC_SLBSAVE+64)(%r1)
459 std %r29,(PC_SLBSAVE+72)(%r1)
460 std %r30,(PC_SLBSAVE+80)(%r1)
461 std %r31,(PC_SLBSAVE+88)(%r1)
463 /* Restore kernel mapping */
466 /* Restore remaining registers */
467 ld %r28,(PC_SLBSAVE+64)(%r1)
468 ld %r29,(PC_SLBSAVE+72)(%r1)
469 ld %r30,(PC_SLBSAVE+80)(%r1)
470 ld %r31,(PC_SLBSAVE+88)(%r1)
472 ld %r2,(PC_SLBSAVE+104)(%r1)
474 ld %r2,(PC_SLBSAVE+112)(%r1)
476 ld %r2,(PC_SLBSAVE+120)(%r1)
478 ld %r2,(PC_SLBSAVE+128)(%r1)
480 ld %r2,(PC_SLBSAVE+136)(%r1)
484 ld %r0,(PC_SLBSAVE+0)(%r1)
485 ld %r2,(PC_SLBSAVE+16)(%r1)
486 ld %r3,(PC_SLBSAVE+24)(%r1)
489 /* Back to whatever we were doing */
493 * For ALI: has to save DSISR and DAR
495 .globl CNAME(alitrap),CNAME(alisize)
497 mtsprg1 %r1 /* save SP */
499 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
500 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
501 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
502 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
503 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
506 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
507 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
508 mfsprg1 %r1 /* restore SP, in case of branch */
509 mflr %r28 /* save LR */
510 mfcr %r29 /* save CR */
512 /* Put our exception vector in SPRG3 */
516 /* Test whether we already had PR set */
520 CNAME(alisize) = .-CNAME(alitrap)
523 * Similar to the above for DSI
524 * Has to handle BAT spills
525 * and standard pagetable spills
527 .globl CNAME(dsitrap),CNAME(dsisize)
529 mtsprg1 %r1 /* save SP */
531 std %r27,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
532 std %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1)
533 std %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
534 std %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
535 std %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
536 mfsprg1 %r1 /* restore SP */
537 mfcr %r29 /* save CR */
538 mfxer %r30 /* save XER */
539 mtsprg2 %r30 /* in SPRG2 */
540 mfsrr1 %r31 /* test kernel mode */
542 mflr %r28 /* save LR (SP already saved) */
544 CNAME(dsisize) = .-CNAME(dsitrap)
547 * Preamble code for DSI/ISI traps
550 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
556 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1)
557 std %r31,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
558 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
559 std %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
560 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
561 std %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
562 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
563 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
564 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
565 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
568 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
569 std %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
572 /* Try and detect a kernel stack overflow */
575 bt 17,realtrap /* branch is user mode */
576 mfsprg1 %r31 /* get old SP */
577 sub. %r30,%r31,%r30 /* SP - DAR */
579 neg %r30,%r30 /* modulo value */
580 1: cmpldi %cr0,%r30,4096 /* is DAR within a page of SP? */
581 bge %cr0,realtrap /* no, too far away. */
583 /* Now convert this DSI into a DDB trap. */
585 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
586 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
587 ld %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
588 std %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
589 ld %r31,(PC_DISISAVE+CPUSAVE_R27)(%r1) /* get r27 */
590 std %r31,(PC_DBSAVE +CPUSAVE_R27)(%r1) /* save r27 */
591 ld %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
592 std %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
593 ld %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
594 std %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
595 ld %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
596 std %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
597 ld %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
598 std %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
602 /* XXX need stack probe here */
604 /* Test whether we already had PR set */
607 mfsprg1 %r1 /* restore SP (might have been
609 bf 17,k_trap /* branch if PSL_PR is false */
611 ld %r1,PC_CURPCB(%r1)
612 mr %r27,%r28 /* Save LR, r29 */
614 bl restore_kernsrs /* enable kernel mapping */
620 * generictrap does some standard setup for trap handling to minimize
621 * the code that need be installed in the actual vectors. It expects
622 * the following conditions.
624 * R1 - Trap vector = LR & (0xff00 | R1)
625 * SPRG1 - Original R1 contents
626 * SPRG2 - Original LR
630 /* Save R1 for computing the exception vector */
633 /* Save interesting registers */
635 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1) /* free r27-r31 */
636 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
637 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
638 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
639 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
641 std %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
642 mfsprg1 %r1 /* restore SP, in case of branch */
643 mfsprg2 %r28 /* save LR */
644 mfcr %r29 /* save CR */
646 /* Compute the exception vector from the link register */
653 /* Test whether we already had PR set */
658 bf 17,k_trap /* branch if PSL_PR is false */
661 ld %r1,PC_CURPCB(%r1)
662 mr %r27,%r28 /* Save LR, r29 */
664 bl restore_kernsrs /* enable kernel mapping */
669 * Now the common trap catching code.
672 FRAME_SETUP(PC_TEMPSAVE)
673 /* Call C interrupt dispatcher: */
676 ld %r2,tocbase@l(%r3)
678 bl CNAME(powerpc_interrupt)
681 .globl CNAME(trapexit) /* backtrace code sentinel */
683 /* Disable interrupts: */
685 andi. %r3,%r3,~PSL_EE@l
688 /* Test AST pending: */
689 ld %r5,FRAME_SRR1+48(%r1)
691 bf 17,1f /* branch if PSL_PR is false */
693 GET_CPUINFO(%r3) /* get per-CPU pointer */
694 lwz %r4, TD_FLAGS(%r13) /* get thread flags value */
695 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
696 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
699 mfmsr %r3 /* re-enable interrupts */
704 ld %r2,tocbase@l(%r3)
708 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
710 b trapexit /* test ast ret value ? */
712 FRAME_LEAVE(PC_TEMPSAVE)
717 * Deliberate entry to dbtrap
719 ASENTRY_NOPROF(breakpoint)
723 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
724 mtmsr %r3 /* disable interrupts */
727 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r3)
728 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
729 std %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
730 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
731 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
739 * Now the kdb trap catching code.
742 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
747 lis %r1,(tmpstk+TMPSTKSZ-48)@ha /* get new SP */
748 addi %r1,%r1,(tmpstk+TMPSTKSZ-48)@l
750 FRAME_SETUP(PC_DBSAVE)
751 /* Call C trap code: */
753 ld %r2,tocbase@l(%r3)
755 bl CNAME(db_trap_glue)
759 /* This wasn't for KDB, so switch to real trap: */
760 ld %r3,FRAME_EXC+48(%r1) /* save exception */
762 std %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
763 FRAME_LEAVE(PC_DBSAVE)
764 mtsprg1 %r1 /* prepare for entrance to realtrap */
766 std %r27,(PC_TEMPSAVE+CPUSAVE_R27)(%r1)
767 std %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
768 std %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
769 std %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
770 std %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
773 ld %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
774 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
778 FRAME_LEAVE(PC_DBSAVE)
782 * In case of KDB we want a separate trap catcher for it
784 .globl CNAME(dblow),CNAME(dbsize)
786 mtsprg1 %r1 /* save SP */
787 mtsprg2 %r29 /* save r29 */
788 mfcr %r29 /* save CR in r29 */
791 bf 17,1f /* branch if privileged */
793 /* Unprivileged case */
794 mtcr %r29 /* put the condition register back */
795 mfsprg2 %r29 /* ... and r29 */
796 mflr %r1 /* save LR */
797 mtsprg2 %r1 /* And then in SPRG2 */
798 li %r1, 0 /* How to get the vector from LR */
800 bla generictrap /* and we look like a generic trap */
802 /* Privileged, so drop to KDB */
804 std %r27,(PC_DBSAVE+CPUSAVE_R27)(%r1) /* free r27 */
805 std %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
806 mfsprg2 %r28 /* r29 holds cr... */
807 std %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
808 std %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
809 std %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
810 mflr %r28 /* save LR */
812 CNAME(dbsize) = .-CNAME(dblow)