2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * Some hw specific parts of this pmap were derived or influenced
27 * by NetBSD's ibm4xx pmap module. More generic code is shared with
28 * a few other pmap modules from the FreeBSD tree.
34 * Kernel and user threads run within one common virtual address space
37 * Virtual address space layout:
38 * -----------------------------
39 * 0x0000_0000 - 0xafff_ffff : user process
40 * 0xb000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
41 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
42 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
43 * 0xc100_0000 - 0xfeef_ffff : KVA
44 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
45 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
46 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
47 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
48 * 0xfef0_0000 - 0xffff_ffff : I/O devices region
51 #include <sys/cdefs.h>
52 __FBSDID("$FreeBSD$");
54 #include <sys/param.h>
55 #include <sys/malloc.h>
59 #include <sys/queue.h>
60 #include <sys/systm.h>
61 #include <sys/kernel.h>
62 #include <sys/linker.h>
63 #include <sys/msgbuf.h>
65 #include <sys/mutex.h>
66 #include <sys/rwlock.h>
67 #include <sys/sched.h>
69 #include <sys/vmmeter.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
82 #include <machine/cpu.h>
83 #include <machine/pcb.h>
84 #include <machine/platform.h>
86 #include <machine/tlb.h>
87 #include <machine/spr.h>
88 #include <machine/md_var.h>
89 #include <machine/mmuvar.h>
90 #include <machine/pmap.h>
91 #include <machine/pte.h>
96 #define debugf(fmt, args...) printf(fmt, ##args)
98 #define debugf(fmt, args...)
101 #define TODO panic("%s: not implemented", __func__);
103 extern struct mtx sched_lock;
105 extern int dumpsys_minidump;
107 extern unsigned char _etext[];
108 extern unsigned char _end[];
110 extern uint32_t *bootinfo;
113 extern uint32_t bp_ntlb1s;
117 vm_offset_t kernstart;
120 /* Message buffer and tables. */
121 static vm_offset_t data_start;
122 static vm_size_t data_end;
124 /* Phys/avail memory regions. */
125 static struct mem_region *availmem_regions;
126 static int availmem_regions_sz;
127 static struct mem_region *physmem_regions;
128 static int physmem_regions_sz;
130 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
131 static vm_offset_t zero_page_va;
132 static struct mtx zero_page_mutex;
134 static struct mtx tlbivax_mutex;
137 * Reserved KVA space for mmu_booke_zero_page_idle. This is used
138 * by idle thred only, no lock required.
140 static vm_offset_t zero_page_idle_va;
142 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
143 static vm_offset_t copy_page_src_va;
144 static vm_offset_t copy_page_dst_va;
145 static struct mtx copy_page_mutex;
147 /**************************************************************************/
149 /**************************************************************************/
151 static void mmu_booke_enter_locked(mmu_t, pmap_t, vm_offset_t, vm_page_t,
152 vm_prot_t, boolean_t);
154 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
155 unsigned int kernel_ptbls; /* Number of KVA ptbls. */
158 * If user pmap is processed with mmu_booke_remove and the resident count
159 * drops to 0, there are no more pages to remove, so we need not continue.
161 #define PMAP_REMOVE_DONE(pmap) \
162 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
164 extern void tid_flush(tlbtid_t);
166 /**************************************************************************/
167 /* TLB and TID handling */
168 /**************************************************************************/
170 /* Translation ID busy table */
171 static volatile pmap_t tidbusy[MAXCPU][TID_MAX + 1];
174 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
175 * core revisions and should be read from h/w registers during early config.
177 uint32_t tlb0_entries;
179 uint32_t tlb0_entries_per_way;
181 #define TLB0_ENTRIES (tlb0_entries)
182 #define TLB0_WAYS (tlb0_ways)
183 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
185 #define TLB1_ENTRIES 16
187 /* In-ram copy of the TLB1 */
188 static tlb_entry_t tlb1[TLB1_ENTRIES];
190 /* Next free entry in the TLB1 */
191 static unsigned int tlb1_idx;
193 static tlbtid_t tid_alloc(struct pmap *);
195 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
197 static int tlb1_set_entry(vm_offset_t, vm_offset_t, vm_size_t, uint32_t);
198 static void tlb1_write_entry(unsigned int);
199 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
200 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t);
202 static vm_size_t tsize2size(unsigned int);
203 static unsigned int size2tsize(vm_size_t);
204 static unsigned int ilog2(unsigned int);
206 static void set_mas4_defaults(void);
208 static inline void tlb0_flush_entry(vm_offset_t);
209 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
211 /**************************************************************************/
212 /* Page table management */
213 /**************************************************************************/
215 static struct rwlock_padalign pvh_global_lock;
217 /* Data for the pv entry allocation mechanism */
218 static uma_zone_t pvzone;
219 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
221 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
223 #ifndef PMAP_SHPGPERPROC
224 #define PMAP_SHPGPERPROC 200
227 static void ptbl_init(void);
228 static struct ptbl_buf *ptbl_buf_alloc(void);
229 static void ptbl_buf_free(struct ptbl_buf *);
230 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
232 static pte_t *ptbl_alloc(mmu_t, pmap_t, unsigned int);
233 static void ptbl_free(mmu_t, pmap_t, unsigned int);
234 static void ptbl_hold(mmu_t, pmap_t, unsigned int);
235 static int ptbl_unhold(mmu_t, pmap_t, unsigned int);
237 static vm_paddr_t pte_vatopa(mmu_t, pmap_t, vm_offset_t);
238 static pte_t *pte_find(mmu_t, pmap_t, vm_offset_t);
239 static void pte_enter(mmu_t, pmap_t, vm_page_t, vm_offset_t, uint32_t);
240 static int pte_remove(mmu_t, pmap_t, vm_offset_t, uint8_t);
242 static pv_entry_t pv_alloc(void);
243 static void pv_free(pv_entry_t);
244 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
245 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
247 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
248 #define PTBL_BUFS (128 * 16)
251 TAILQ_ENTRY(ptbl_buf) link; /* list link */
252 vm_offset_t kva; /* va of mapping */
255 /* ptbl free list and a lock used for access synchronization. */
256 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
257 static struct mtx ptbl_buf_freelist_lock;
259 /* Base address of kva space allocated fot ptbl bufs. */
260 static vm_offset_t ptbl_buf_pool_vabase;
262 /* Pointer to ptbl_buf structures. */
263 static struct ptbl_buf *ptbl_bufs;
265 void pmap_bootstrap_ap(volatile uint32_t *);
268 * Kernel MMU interface
270 static void mmu_booke_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
271 static void mmu_booke_clear_modify(mmu_t, vm_page_t);
272 static void mmu_booke_copy(mmu_t, pmap_t, pmap_t, vm_offset_t,
273 vm_size_t, vm_offset_t);
274 static void mmu_booke_copy_page(mmu_t, vm_page_t, vm_page_t);
275 static void mmu_booke_copy_pages(mmu_t, vm_page_t *,
276 vm_offset_t, vm_page_t *, vm_offset_t, int);
277 static void mmu_booke_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t,
278 vm_prot_t, boolean_t);
279 static void mmu_booke_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
280 vm_page_t, vm_prot_t);
281 static void mmu_booke_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t,
283 static vm_paddr_t mmu_booke_extract(mmu_t, pmap_t, vm_offset_t);
284 static vm_page_t mmu_booke_extract_and_hold(mmu_t, pmap_t, vm_offset_t,
286 static void mmu_booke_init(mmu_t);
287 static boolean_t mmu_booke_is_modified(mmu_t, vm_page_t);
288 static boolean_t mmu_booke_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
289 static boolean_t mmu_booke_is_referenced(mmu_t, vm_page_t);
290 static int mmu_booke_ts_referenced(mmu_t, vm_page_t);
291 static vm_offset_t mmu_booke_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t,
293 static int mmu_booke_mincore(mmu_t, pmap_t, vm_offset_t,
295 static void mmu_booke_object_init_pt(mmu_t, pmap_t, vm_offset_t,
296 vm_object_t, vm_pindex_t, vm_size_t);
297 static boolean_t mmu_booke_page_exists_quick(mmu_t, pmap_t, vm_page_t);
298 static void mmu_booke_page_init(mmu_t, vm_page_t);
299 static int mmu_booke_page_wired_mappings(mmu_t, vm_page_t);
300 static void mmu_booke_pinit(mmu_t, pmap_t);
301 static void mmu_booke_pinit0(mmu_t, pmap_t);
302 static void mmu_booke_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t,
304 static void mmu_booke_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
305 static void mmu_booke_qremove(mmu_t, vm_offset_t, int);
306 static void mmu_booke_release(mmu_t, pmap_t);
307 static void mmu_booke_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
308 static void mmu_booke_remove_all(mmu_t, vm_page_t);
309 static void mmu_booke_remove_write(mmu_t, vm_page_t);
310 static void mmu_booke_zero_page(mmu_t, vm_page_t);
311 static void mmu_booke_zero_page_area(mmu_t, vm_page_t, int, int);
312 static void mmu_booke_zero_page_idle(mmu_t, vm_page_t);
313 static void mmu_booke_activate(mmu_t, struct thread *);
314 static void mmu_booke_deactivate(mmu_t, struct thread *);
315 static void mmu_booke_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
316 static void *mmu_booke_mapdev(mmu_t, vm_paddr_t, vm_size_t);
317 static void *mmu_booke_mapdev_attr(mmu_t, vm_paddr_t, vm_size_t, vm_memattr_t);
318 static void mmu_booke_unmapdev(mmu_t, vm_offset_t, vm_size_t);
319 static vm_paddr_t mmu_booke_kextract(mmu_t, vm_offset_t);
320 static void mmu_booke_kenter(mmu_t, vm_offset_t, vm_paddr_t);
321 static void mmu_booke_kenter_attr(mmu_t, vm_offset_t, vm_paddr_t, vm_memattr_t);
322 static void mmu_booke_kremove(mmu_t, vm_offset_t);
323 static boolean_t mmu_booke_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
324 static void mmu_booke_sync_icache(mmu_t, pmap_t, vm_offset_t,
326 static vm_offset_t mmu_booke_dumpsys_map(mmu_t, struct pmap_md *,
327 vm_size_t, vm_size_t *);
328 static void mmu_booke_dumpsys_unmap(mmu_t, struct pmap_md *,
329 vm_size_t, vm_offset_t);
330 static struct pmap_md *mmu_booke_scan_md(mmu_t, struct pmap_md *);
332 static mmu_method_t mmu_booke_methods[] = {
333 /* pmap dispatcher interface */
334 MMUMETHOD(mmu_change_wiring, mmu_booke_change_wiring),
335 MMUMETHOD(mmu_clear_modify, mmu_booke_clear_modify),
336 MMUMETHOD(mmu_copy, mmu_booke_copy),
337 MMUMETHOD(mmu_copy_page, mmu_booke_copy_page),
338 MMUMETHOD(mmu_copy_pages, mmu_booke_copy_pages),
339 MMUMETHOD(mmu_enter, mmu_booke_enter),
340 MMUMETHOD(mmu_enter_object, mmu_booke_enter_object),
341 MMUMETHOD(mmu_enter_quick, mmu_booke_enter_quick),
342 MMUMETHOD(mmu_extract, mmu_booke_extract),
343 MMUMETHOD(mmu_extract_and_hold, mmu_booke_extract_and_hold),
344 MMUMETHOD(mmu_init, mmu_booke_init),
345 MMUMETHOD(mmu_is_modified, mmu_booke_is_modified),
346 MMUMETHOD(mmu_is_prefaultable, mmu_booke_is_prefaultable),
347 MMUMETHOD(mmu_is_referenced, mmu_booke_is_referenced),
348 MMUMETHOD(mmu_ts_referenced, mmu_booke_ts_referenced),
349 MMUMETHOD(mmu_map, mmu_booke_map),
350 MMUMETHOD(mmu_mincore, mmu_booke_mincore),
351 MMUMETHOD(mmu_object_init_pt, mmu_booke_object_init_pt),
352 MMUMETHOD(mmu_page_exists_quick,mmu_booke_page_exists_quick),
353 MMUMETHOD(mmu_page_init, mmu_booke_page_init),
354 MMUMETHOD(mmu_page_wired_mappings, mmu_booke_page_wired_mappings),
355 MMUMETHOD(mmu_pinit, mmu_booke_pinit),
356 MMUMETHOD(mmu_pinit0, mmu_booke_pinit0),
357 MMUMETHOD(mmu_protect, mmu_booke_protect),
358 MMUMETHOD(mmu_qenter, mmu_booke_qenter),
359 MMUMETHOD(mmu_qremove, mmu_booke_qremove),
360 MMUMETHOD(mmu_release, mmu_booke_release),
361 MMUMETHOD(mmu_remove, mmu_booke_remove),
362 MMUMETHOD(mmu_remove_all, mmu_booke_remove_all),
363 MMUMETHOD(mmu_remove_write, mmu_booke_remove_write),
364 MMUMETHOD(mmu_sync_icache, mmu_booke_sync_icache),
365 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
366 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
367 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
368 MMUMETHOD(mmu_activate, mmu_booke_activate),
369 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
371 /* Internal interfaces */
372 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
373 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
374 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
375 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
376 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
377 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
378 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
379 /* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
380 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
382 /* dumpsys() support */
383 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
384 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
385 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
390 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
392 static __inline uint32_t
393 tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
398 if (ma != VM_MEMATTR_DEFAULT) {
400 case VM_MEMATTR_UNCACHEABLE:
401 return (PTE_I | PTE_G);
402 case VM_MEMATTR_WRITE_COMBINING:
403 case VM_MEMATTR_WRITE_BACK:
404 case VM_MEMATTR_PREFETCHABLE:
406 case VM_MEMATTR_WRITE_THROUGH:
407 return (PTE_W | PTE_M);
412 * Assume the page is cache inhibited and access is guarded unless
413 * it's in our available memory array.
415 attrib = _TLB_ENTRY_IO;
416 for (i = 0; i < physmem_regions_sz; i++) {
417 if ((pa >= physmem_regions[i].mr_start) &&
418 (pa < (physmem_regions[i].mr_start +
419 physmem_regions[i].mr_size))) {
420 attrib = _TLB_ENTRY_MEM;
437 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
440 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
441 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
443 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
444 ("tlb_miss_lock: tried to lock self"));
446 tlb_lock(pc->pc_booke_tlb_lock);
448 CTR1(KTR_PMAP, "%s: locked", __func__);
455 tlb_miss_unlock(void)
463 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
465 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
466 __func__, pc->pc_cpuid);
468 tlb_unlock(pc->pc_booke_tlb_lock);
470 CTR1(KTR_PMAP, "%s: unlocked", __func__);
476 /* Return number of entries in TLB0. */
478 tlb0_get_tlbconf(void)
482 tlb0_cfg = mfspr(SPR_TLB0CFG);
483 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
484 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
485 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
488 /* Initialize pool of kva ptbl buffers. */
494 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
495 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
496 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
497 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
499 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
500 TAILQ_INIT(&ptbl_buf_freelist);
502 for (i = 0; i < PTBL_BUFS; i++) {
503 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
504 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
508 /* Get a ptbl_buf from the freelist. */
509 static struct ptbl_buf *
512 struct ptbl_buf *buf;
514 mtx_lock(&ptbl_buf_freelist_lock);
515 buf = TAILQ_FIRST(&ptbl_buf_freelist);
517 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
518 mtx_unlock(&ptbl_buf_freelist_lock);
520 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
525 /* Return ptbl buff to free pool. */
527 ptbl_buf_free(struct ptbl_buf *buf)
530 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
532 mtx_lock(&ptbl_buf_freelist_lock);
533 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
534 mtx_unlock(&ptbl_buf_freelist_lock);
538 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
541 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
543 struct ptbl_buf *pbuf;
545 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
547 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
549 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
550 if (pbuf->kva == (vm_offset_t)ptbl) {
551 /* Remove from pmap ptbl buf list. */
552 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
554 /* Free corresponding ptbl buf. */
560 /* Allocate page table. */
562 ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
564 vm_page_t mtbl[PTBL_PAGES];
566 struct ptbl_buf *pbuf;
571 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
572 (pmap == kernel_pmap), pdir_idx);
574 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
575 ("ptbl_alloc: invalid pdir_idx"));
576 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
577 ("pte_alloc: valid ptbl entry exists!"));
579 pbuf = ptbl_buf_alloc();
581 panic("pte_alloc: couldn't alloc kernel virtual memory");
583 ptbl = (pte_t *)pbuf->kva;
585 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
587 /* Allocate ptbl pages, this will sleep! */
588 for (i = 0; i < PTBL_PAGES; i++) {
589 pidx = (PTBL_PAGES * pdir_idx) + i;
590 while ((m = vm_page_alloc(NULL, pidx,
591 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
594 rw_wunlock(&pvh_global_lock);
596 rw_wlock(&pvh_global_lock);
602 /* Map allocated pages into kernel_pmap. */
603 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
605 /* Zero whole ptbl. */
606 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
608 /* Add pbuf to the pmap ptbl bufs list. */
609 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
614 /* Free ptbl pages and invalidate pdir entry. */
616 ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
624 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
625 (pmap == kernel_pmap), pdir_idx);
627 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
628 ("ptbl_free: invalid pdir_idx"));
630 ptbl = pmap->pm_pdir[pdir_idx];
632 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
634 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
637 * Invalidate the pdir entry as soon as possible, so that other CPUs
638 * don't attempt to look up the page tables we are releasing.
640 mtx_lock_spin(&tlbivax_mutex);
643 pmap->pm_pdir[pdir_idx] = NULL;
646 mtx_unlock_spin(&tlbivax_mutex);
648 for (i = 0; i < PTBL_PAGES; i++) {
649 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
650 pa = pte_vatopa(mmu, kernel_pmap, va);
651 m = PHYS_TO_VM_PAGE(pa);
652 vm_page_free_zero(m);
653 atomic_subtract_int(&cnt.v_wire_count, 1);
654 mmu_booke_kremove(mmu, va);
657 ptbl_free_pmap_ptbl(pmap, ptbl);
661 * Decrement ptbl pages hold count and attempt to free ptbl pages.
662 * Called when removing pte entry from ptbl.
664 * Return 1 if ptbl pages were freed.
667 ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
674 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
675 (pmap == kernel_pmap), pdir_idx);
677 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
678 ("ptbl_unhold: invalid pdir_idx"));
679 KASSERT((pmap != kernel_pmap),
680 ("ptbl_unhold: unholding kernel ptbl!"));
682 ptbl = pmap->pm_pdir[pdir_idx];
684 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
685 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
686 ("ptbl_unhold: non kva ptbl"));
688 /* decrement hold count */
689 for (i = 0; i < PTBL_PAGES; i++) {
690 pa = pte_vatopa(mmu, kernel_pmap,
691 (vm_offset_t)ptbl + (i * PAGE_SIZE));
692 m = PHYS_TO_VM_PAGE(pa);
697 * Free ptbl pages if there are no pte etries in this ptbl.
698 * wire_count has the same value for all ptbl pages, so check the last
701 if (m->wire_count == 0) {
702 ptbl_free(mmu, pmap, pdir_idx);
704 //debugf("ptbl_unhold: e (freed ptbl)\n");
712 * Increment hold count for ptbl pages. This routine is used when a new pte
713 * entry is being inserted into the ptbl.
716 ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
723 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
726 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
727 ("ptbl_hold: invalid pdir_idx"));
728 KASSERT((pmap != kernel_pmap),
729 ("ptbl_hold: holding kernel ptbl!"));
731 ptbl = pmap->pm_pdir[pdir_idx];
733 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
735 for (i = 0; i < PTBL_PAGES; i++) {
736 pa = pte_vatopa(mmu, kernel_pmap,
737 (vm_offset_t)ptbl + (i * PAGE_SIZE));
738 m = PHYS_TO_VM_PAGE(pa);
743 /* Allocate pv_entry structure. */
750 if (pv_entry_count > pv_entry_high_water)
752 pv = uma_zalloc(pvzone, M_NOWAIT);
757 /* Free pv_entry structure. */
759 pv_free(pv_entry_t pve)
763 uma_zfree(pvzone, pve);
767 /* Allocate and initialize pv_entry structure. */
769 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
773 //int su = (pmap == kernel_pmap);
774 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
775 // (u_int32_t)pmap, va, (u_int32_t)m);
779 panic("pv_insert: no pv entries!");
785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
786 rw_assert(&pvh_global_lock, RA_WLOCKED);
788 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
790 //debugf("pv_insert: e\n");
793 /* Destroy pv entry. */
795 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
799 //int su = (pmap == kernel_pmap);
800 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
802 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
803 rw_assert(&pvh_global_lock, RA_WLOCKED);
806 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
807 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
808 /* remove from pv_list */
809 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
810 if (TAILQ_EMPTY(&m->md.pv_list))
811 vm_page_aflag_clear(m, PGA_WRITEABLE);
813 /* free pv entry struct */
819 //debugf("pv_remove: e\n");
823 * Clean pte entry, try to free page table page if requested.
825 * Return 1 if ptbl pages were freed, otherwise return 0.
828 pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
830 unsigned int pdir_idx = PDIR_IDX(va);
831 unsigned int ptbl_idx = PTBL_IDX(va);
836 //int su = (pmap == kernel_pmap);
837 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
838 // su, (u_int32_t)pmap, va, flags);
840 ptbl = pmap->pm_pdir[pdir_idx];
841 KASSERT(ptbl, ("pte_remove: null ptbl"));
843 pte = &ptbl[ptbl_idx];
845 if (pte == NULL || !PTE_ISVALID(pte))
848 if (PTE_ISWIRED(pte))
849 pmap->pm_stats.wired_count--;
851 /* Handle managed entry. */
852 if (PTE_ISMANAGED(pte)) {
853 /* Get vm_page_t for mapped pte. */
854 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
856 if (PTE_ISMODIFIED(pte))
859 if (PTE_ISREFERENCED(pte))
860 vm_page_aflag_set(m, PGA_REFERENCED);
862 pv_remove(pmap, va, m);
865 mtx_lock_spin(&tlbivax_mutex);
868 tlb0_flush_entry(va);
873 mtx_unlock_spin(&tlbivax_mutex);
875 pmap->pm_stats.resident_count--;
877 if (flags & PTBL_UNHOLD) {
878 //debugf("pte_remove: e (unhold)\n");
879 return (ptbl_unhold(mmu, pmap, pdir_idx));
882 //debugf("pte_remove: e\n");
887 * Insert PTE for a given page and virtual address.
890 pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags)
892 unsigned int pdir_idx = PDIR_IDX(va);
893 unsigned int ptbl_idx = PTBL_IDX(va);
896 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
897 pmap == kernel_pmap, pmap, va);
899 /* Get the page table pointer. */
900 ptbl = pmap->pm_pdir[pdir_idx];
903 /* Allocate page table pages. */
904 ptbl = ptbl_alloc(mmu, pmap, pdir_idx);
907 * Check if there is valid mapping for requested
908 * va, if there is, remove it.
910 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
911 if (PTE_ISVALID(pte)) {
912 pte_remove(mmu, pmap, va, PTBL_HOLD);
915 * pte is not used, increment hold count
918 if (pmap != kernel_pmap)
919 ptbl_hold(mmu, pmap, pdir_idx);
924 * Insert pv_entry into pv_list for mapped page if part of managed
927 if ((m->oflags & VPO_UNMANAGED) == 0) {
928 flags |= PTE_MANAGED;
930 /* Create and insert pv entry. */
931 pv_insert(pmap, va, m);
934 pmap->pm_stats.resident_count++;
936 mtx_lock_spin(&tlbivax_mutex);
939 tlb0_flush_entry(va);
940 if (pmap->pm_pdir[pdir_idx] == NULL) {
942 * If we just allocated a new page table, hook it in
945 pmap->pm_pdir[pdir_idx] = ptbl;
947 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
948 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
949 pte->flags |= (PTE_VALID | flags);
952 mtx_unlock_spin(&tlbivax_mutex);
955 /* Return the pa for the given pmap/va. */
957 pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
962 pte = pte_find(mmu, pmap, va);
963 if ((pte != NULL) && PTE_ISVALID(pte))
964 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
968 /* Get a pointer to a PTE in a page table. */
970 pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
972 unsigned int pdir_idx = PDIR_IDX(va);
973 unsigned int ptbl_idx = PTBL_IDX(va);
975 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
977 if (pmap->pm_pdir[pdir_idx])
978 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
983 /**************************************************************************/
985 /**************************************************************************/
988 * This is called during booke_init, before the system is really initialized.
991 mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
993 vm_offset_t phys_kernelend;
994 struct mem_region *mp, *mp1;
997 u_int phys_avail_count;
998 vm_size_t physsz, hwphyssz, kstack0_sz;
999 vm_offset_t kernel_pdir, kstack0, va;
1000 vm_paddr_t kstack0_phys;
1004 debugf("mmu_booke_bootstrap: entered\n");
1006 /* Initialize invalidation mutex */
1007 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1009 /* Read TLB0 size and associativity. */
1013 * Align kernel start and end address (kernel image).
1014 * Note that kernel end does not necessarily relate to kernsize.
1015 * kernsize is the size of the kernel that is actually mapped.
1016 * Also note that "start - 1" is deliberate. With SMP, the
1017 * entry point is exactly a page from the actual load address.
1018 * As such, trunc_page() has no effect and we're off by a page.
1019 * Since we always have the ELF header between the load address
1020 * and the entry point, we can safely subtract 1 to compensate.
1022 kernstart = trunc_page(start - 1);
1023 data_start = round_page(kernelend);
1024 data_end = data_start;
1027 * Addresses of preloaded modules (like file systems) use
1028 * physical addresses. Make sure we relocate those into
1029 * virtual addresses.
1031 preload_addr_relocate = kernstart - kernload;
1033 /* Allocate the dynamic per-cpu area. */
1034 dpcpu = (void *)data_end;
1035 data_end += DPCPU_SIZE;
1037 /* Allocate space for the message buffer. */
1038 msgbufp = (struct msgbuf *)data_end;
1039 data_end += msgbufsize;
1040 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1043 data_end = round_page(data_end);
1045 /* Allocate space for ptbl_bufs. */
1046 ptbl_bufs = (struct ptbl_buf *)data_end;
1047 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1048 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1051 data_end = round_page(data_end);
1053 /* Allocate PTE tables for kernel KVA. */
1054 kernel_pdir = data_end;
1055 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1056 PDIR_SIZE - 1) / PDIR_SIZE;
1057 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1058 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1059 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1061 debugf(" data_end: 0x%08x\n", data_end);
1062 if (data_end - kernstart > kernsize) {
1063 kernsize += tlb1_mapin_region(kernstart + kernsize,
1064 kernload + kernsize, (data_end - kernstart) - kernsize);
1066 data_end = kernstart + kernsize;
1067 debugf(" updated data_end: 0x%08x\n", data_end);
1070 * Clear the structures - note we can only do it safely after the
1071 * possible additional TLB1 translations are in place (above) so that
1072 * all range up to the currently calculated 'data_end' is covered.
1074 dpcpu_init(dpcpu, 0);
1075 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1076 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1078 /*******************************************************/
1079 /* Set the start and end of kva. */
1080 /*******************************************************/
1081 virtual_avail = round_page(data_end);
1082 virtual_end = VM_MAX_KERNEL_ADDRESS;
1084 /* Allocate KVA space for page zero/copy operations. */
1085 zero_page_va = virtual_avail;
1086 virtual_avail += PAGE_SIZE;
1087 zero_page_idle_va = virtual_avail;
1088 virtual_avail += PAGE_SIZE;
1089 copy_page_src_va = virtual_avail;
1090 virtual_avail += PAGE_SIZE;
1091 copy_page_dst_va = virtual_avail;
1092 virtual_avail += PAGE_SIZE;
1093 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1094 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1095 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1096 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1098 /* Initialize page zero/copy mutexes. */
1099 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1100 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1102 /* Allocate KVA space for ptbl bufs. */
1103 ptbl_buf_pool_vabase = virtual_avail;
1104 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1105 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1106 ptbl_buf_pool_vabase, virtual_avail);
1108 /* Calculate corresponding physical addresses for the kernel region. */
1109 phys_kernelend = kernload + kernsize;
1110 debugf("kernel image and allocated data:\n");
1111 debugf(" kernload = 0x%08x\n", kernload);
1112 debugf(" kernstart = 0x%08x\n", kernstart);
1113 debugf(" kernsize = 0x%08x\n", kernsize);
1115 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1116 panic("mmu_booke_bootstrap: phys_avail too small");
1119 * Remove kernel physical address range from avail regions list. Page
1120 * align all regions. Non-page aligned memory isn't very interesting
1121 * to us. Also, sort the entries for ascending addresses.
1124 /* Retrieve phys/avail mem regions */
1125 mem_regions(&physmem_regions, &physmem_regions_sz,
1126 &availmem_regions, &availmem_regions_sz);
1128 cnt = availmem_regions_sz;
1129 debugf("processing avail regions:\n");
1130 for (mp = availmem_regions; mp->mr_size; mp++) {
1132 e = mp->mr_start + mp->mr_size;
1133 debugf(" %08x-%08x -> ", s, e);
1134 /* Check whether this region holds all of the kernel. */
1135 if (s < kernload && e > phys_kernelend) {
1136 availmem_regions[cnt].mr_start = phys_kernelend;
1137 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1140 /* Look whether this regions starts within the kernel. */
1141 if (s >= kernload && s < phys_kernelend) {
1142 if (e <= phys_kernelend)
1146 /* Now look whether this region ends within the kernel. */
1147 if (e > kernload && e <= phys_kernelend) {
1152 /* Now page align the start and size of the region. */
1158 debugf("%08x-%08x = %x\n", s, e, sz);
1160 /* Check whether some memory is left here. */
1164 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1170 /* Do an insertion sort. */
1171 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1172 if (s < mp1->mr_start)
1175 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1183 availmem_regions_sz = cnt;
1185 /*******************************************************/
1186 /* Steal physical memory for kernel stack from the end */
1187 /* of the first avail region */
1188 /*******************************************************/
1189 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1190 kstack0_phys = availmem_regions[0].mr_start +
1191 availmem_regions[0].mr_size;
1192 kstack0_phys -= kstack0_sz;
1193 availmem_regions[0].mr_size -= kstack0_sz;
1195 /*******************************************************/
1196 /* Fill in phys_avail table, based on availmem_regions */
1197 /*******************************************************/
1198 phys_avail_count = 0;
1201 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1203 debugf("fill in phys_avail:\n");
1204 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1206 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1207 availmem_regions[i].mr_start,
1208 availmem_regions[i].mr_start +
1209 availmem_regions[i].mr_size,
1210 availmem_regions[i].mr_size);
1212 if (hwphyssz != 0 &&
1213 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1214 debugf(" hw.physmem adjust\n");
1215 if (physsz < hwphyssz) {
1216 phys_avail[j] = availmem_regions[i].mr_start;
1218 availmem_regions[i].mr_start +
1226 phys_avail[j] = availmem_regions[i].mr_start;
1227 phys_avail[j + 1] = availmem_regions[i].mr_start +
1228 availmem_regions[i].mr_size;
1230 physsz += availmem_regions[i].mr_size;
1232 physmem = btoc(physsz);
1234 /* Calculate the last available physical address. */
1235 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1237 Maxmem = powerpc_btop(phys_avail[i + 1]);
1239 debugf("Maxmem = 0x%08lx\n", Maxmem);
1240 debugf("phys_avail_count = %d\n", phys_avail_count);
1241 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1244 /*******************************************************/
1245 /* Initialize (statically allocated) kernel pmap. */
1246 /*******************************************************/
1247 PMAP_LOCK_INIT(kernel_pmap);
1248 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1250 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1251 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1252 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1253 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1255 /* Initialize kernel pdir */
1256 for (i = 0; i < kernel_ptbls; i++)
1257 kernel_pmap->pm_pdir[kptbl_min + i] =
1258 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1260 for (i = 0; i < MAXCPU; i++) {
1261 kernel_pmap->pm_tid[i] = TID_KERNEL;
1263 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1264 tidbusy[i][0] = kernel_pmap;
1268 * Fill in PTEs covering kernel code and data. They are not required
1269 * for address translation, as this area is covered by static TLB1
1270 * entries, but for pte_vatopa() to work correctly with kernel area
1273 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1274 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1275 pte->rpn = kernload + (va - kernstart);
1276 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1279 /* Mark kernel_pmap active on all CPUs */
1280 CPU_FILL(&kernel_pmap->pm_active);
1283 * Initialize the global pv list lock.
1285 rw_init(&pvh_global_lock, "pmap pv global");
1287 /*******************************************************/
1289 /*******************************************************/
1291 /* Enter kstack0 into kernel map, provide guard page */
1292 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1293 thread0.td_kstack = kstack0;
1294 thread0.td_kstack_pages = KSTACK_PAGES;
1296 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1297 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1298 kstack0_phys, kstack0_phys + kstack0_sz);
1299 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1301 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1302 for (i = 0; i < KSTACK_PAGES; i++) {
1303 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1304 kstack0 += PAGE_SIZE;
1305 kstack0_phys += PAGE_SIZE;
1308 debugf("virtual_avail = %08x\n", virtual_avail);
1309 debugf("virtual_end = %08x\n", virtual_end);
1311 debugf("mmu_booke_bootstrap: exit\n");
1315 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1320 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1321 * have the snapshot of its contents in the s/w tlb1[] table, so use
1322 * these values directly to (re)program AP's TLB1 hardware.
1324 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1325 /* Skip invalid entries */
1326 if (!(tlb1[i].mas1 & MAS1_VALID))
1329 tlb1_write_entry(i);
1332 set_mas4_defaults();
1336 * Get the physical page address for the given pmap/virtual address.
1339 mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1344 pa = pte_vatopa(mmu, pmap, va);
1351 * Extract the physical page address associated with the given
1352 * kernel virtual address.
1355 mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1359 /* Check TLB1 mappings */
1360 for (i = 0; i < tlb1_idx; i++) {
1361 if (!(tlb1[i].mas1 & MAS1_VALID))
1363 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size)
1364 return (tlb1[i].phys + (va - tlb1[i].virt));
1367 return (pte_vatopa(mmu, kernel_pmap, va));
1371 * Initialize the pmap module.
1372 * Called by vm_init, to initialize any structures that the pmap
1373 * system needs to map virtual memory.
1376 mmu_booke_init(mmu_t mmu)
1378 int shpgperproc = PMAP_SHPGPERPROC;
1381 * Initialize the address space (zone) for the pv entries. Set a
1382 * high water mark so that the system can recover from excessive
1383 * numbers of pv entries.
1385 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1386 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1388 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1389 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1391 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1392 pv_entry_high_water = 9 * (pv_entry_max / 10);
1394 uma_zone_reserve_kva(pvzone, pv_entry_max);
1396 /* Pre-fill pvzone with initial number of pv entries. */
1397 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1399 /* Initialize ptbl allocation. */
1404 * Map a list of wired pages into kernel virtual address space. This is
1405 * intended for temporary mappings which do not need page modification or
1406 * references recorded. Existing mappings in the region are overwritten.
1409 mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1414 while (count-- > 0) {
1415 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1422 * Remove page mappings from kernel virtual address space. Intended for
1423 * temporary mappings entered by mmu_booke_qenter.
1426 mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1431 while (count-- > 0) {
1432 mmu_booke_kremove(mmu, va);
1438 * Map a wired page into kernel virtual address space.
1441 mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1444 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1448 mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1450 unsigned int pdir_idx = PDIR_IDX(va);
1451 unsigned int ptbl_idx = PTBL_IDX(va);
1455 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1456 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1458 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1459 flags |= tlb_calc_wimg(pa, ma);
1461 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1463 mtx_lock_spin(&tlbivax_mutex);
1466 if (PTE_ISVALID(pte)) {
1468 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1470 /* Flush entry from TLB0 */
1471 tlb0_flush_entry(va);
1474 pte->rpn = pa & ~PTE_PA_MASK;
1477 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1478 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1479 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1481 /* Flush the real memory from the instruction cache. */
1482 if ((flags & (PTE_I | PTE_G)) == 0) {
1483 __syncicache((void *)va, PAGE_SIZE);
1487 mtx_unlock_spin(&tlbivax_mutex);
1491 * Remove a page from kernel page table.
1494 mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1496 unsigned int pdir_idx = PDIR_IDX(va);
1497 unsigned int ptbl_idx = PTBL_IDX(va);
1500 // CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1502 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1503 (va <= VM_MAX_KERNEL_ADDRESS)),
1504 ("mmu_booke_kremove: invalid va"));
1506 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1508 if (!PTE_ISVALID(pte)) {
1510 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1515 mtx_lock_spin(&tlbivax_mutex);
1518 /* Invalidate entry in TLB0, update PTE. */
1519 tlb0_flush_entry(va);
1524 mtx_unlock_spin(&tlbivax_mutex);
1528 * Initialize pmap associated with process 0.
1531 mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1534 PMAP_LOCK_INIT(pmap);
1535 mmu_booke_pinit(mmu, pmap);
1536 PCPU_SET(curpmap, pmap);
1540 * Initialize a preallocated and zeroed pmap structure,
1541 * such as one in a vmspace structure.
1544 mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1548 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1549 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1551 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1553 for (i = 0; i < MAXCPU; i++)
1554 pmap->pm_tid[i] = TID_NONE;
1555 CPU_ZERO(&kernel_pmap->pm_active);
1556 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1557 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1558 TAILQ_INIT(&pmap->pm_ptbl_list);
1562 * Release any resources held by the given physical map.
1563 * Called when a pmap initialized by mmu_booke_pinit is being released.
1564 * Should only be called if the map contains no valid mappings.
1567 mmu_booke_release(mmu_t mmu, pmap_t pmap)
1570 KASSERT(pmap->pm_stats.resident_count == 0,
1571 ("pmap_release: pmap resident count %ld != 0",
1572 pmap->pm_stats.resident_count));
1576 * Insert the given physical page at the specified virtual address in the
1577 * target physical map with the protection requested. If specified the page
1578 * will be wired down.
1581 mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1582 vm_prot_t prot, boolean_t wired)
1585 rw_wlock(&pvh_global_lock);
1587 mmu_booke_enter_locked(mmu, pmap, va, m, prot, wired);
1588 rw_wunlock(&pvh_global_lock);
1593 mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1594 vm_prot_t prot, boolean_t wired)
1601 pa = VM_PAGE_TO_PHYS(m);
1602 su = (pmap == kernel_pmap);
1605 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1606 // "pa=0x%08x prot=0x%08x wired=%d)\n",
1607 // (u_int32_t)pmap, su, pmap->pm_tid,
1608 // (u_int32_t)m, va, pa, prot, wired);
1611 KASSERT(((va >= virtual_avail) &&
1612 (va <= VM_MAX_KERNEL_ADDRESS)),
1613 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1615 KASSERT((va <= VM_MAXUSER_ADDRESS),
1616 ("mmu_booke_enter_locked: user pmap, non user va"));
1618 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1619 VM_OBJECT_ASSERT_LOCKED(m->object);
1621 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1624 * If there is an existing mapping, and the physical address has not
1625 * changed, must be protection or wiring change.
1627 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1628 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1631 * Before actually updating pte->flags we calculate and
1632 * prepare its new value in a helper var.
1635 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1637 /* Wiring change, just update stats. */
1639 if (!PTE_ISWIRED(pte)) {
1641 pmap->pm_stats.wired_count++;
1644 if (PTE_ISWIRED(pte)) {
1645 flags &= ~PTE_WIRED;
1646 pmap->pm_stats.wired_count--;
1650 if (prot & VM_PROT_WRITE) {
1651 /* Add write permissions. */
1656 if ((flags & PTE_MANAGED) != 0)
1657 vm_page_aflag_set(m, PGA_WRITEABLE);
1659 /* Handle modified pages, sense modify status. */
1662 * The PTE_MODIFIED flag could be set by underlying
1663 * TLB misses since we last read it (above), possibly
1664 * other CPUs could update it so we check in the PTE
1665 * directly rather than rely on that saved local flags
1668 if (PTE_ISMODIFIED(pte))
1672 if (prot & VM_PROT_EXECUTE) {
1678 * Check existing flags for execute permissions: if we
1679 * are turning execute permissions on, icache should
1682 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1686 flags &= ~PTE_REFERENCED;
1689 * The new flags value is all calculated -- only now actually
1692 mtx_lock_spin(&tlbivax_mutex);
1695 tlb0_flush_entry(va);
1699 mtx_unlock_spin(&tlbivax_mutex);
1703 * If there is an existing mapping, but it's for a different
1704 * physical address, pte_enter() will delete the old mapping.
1706 //if ((pte != NULL) && PTE_ISVALID(pte))
1707 // debugf("mmu_booke_enter_locked: replace\n");
1709 // debugf("mmu_booke_enter_locked: new\n");
1711 /* Now set up the flags and install the new mapping. */
1712 flags = (PTE_SR | PTE_VALID);
1718 if (prot & VM_PROT_WRITE) {
1723 if ((m->oflags & VPO_UNMANAGED) == 0)
1724 vm_page_aflag_set(m, PGA_WRITEABLE);
1727 if (prot & VM_PROT_EXECUTE) {
1733 /* If its wired update stats. */
1735 pmap->pm_stats.wired_count++;
1739 pte_enter(mmu, pmap, m, va, flags);
1741 /* Flush the real memory from the instruction cache. */
1742 if (prot & VM_PROT_EXECUTE)
1746 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1747 __syncicache((void *)va, PAGE_SIZE);
1753 * Maps a sequence of resident pages belonging to the same object.
1754 * The sequence begins with the given page m_start. This page is
1755 * mapped at the given virtual address start. Each subsequent page is
1756 * mapped at a virtual address that is offset from start by the same
1757 * amount as the page is offset from m_start within the object. The
1758 * last page in the sequence is the page with the largest offset from
1759 * m_start that can be mapped at a virtual address less than the given
1760 * virtual address end. Not every virtual page between start and end
1761 * is mapped; only those for which a resident page exists with the
1762 * corresponding offset from m_start are mapped.
1765 mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1766 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1769 vm_pindex_t diff, psize;
1771 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1773 psize = atop(end - start);
1775 rw_wlock(&pvh_global_lock);
1777 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1778 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1779 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1780 m = TAILQ_NEXT(m, listq);
1782 rw_wunlock(&pvh_global_lock);
1787 mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1791 rw_wlock(&pvh_global_lock);
1793 mmu_booke_enter_locked(mmu, pmap, va, m,
1794 prot & (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1795 rw_wunlock(&pvh_global_lock);
1800 * Remove the given range of addresses from the specified map.
1802 * It is assumed that the start and end are properly rounded to the page size.
1805 mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1810 int su = (pmap == kernel_pmap);
1812 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1813 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1816 KASSERT(((va >= virtual_avail) &&
1817 (va <= VM_MAX_KERNEL_ADDRESS)),
1818 ("mmu_booke_remove: kernel pmap, non kernel va"));
1820 KASSERT((va <= VM_MAXUSER_ADDRESS),
1821 ("mmu_booke_remove: user pmap, non user va"));
1824 if (PMAP_REMOVE_DONE(pmap)) {
1825 //debugf("mmu_booke_remove: e (empty)\n");
1829 hold_flag = PTBL_HOLD_FLAG(pmap);
1830 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1832 rw_wlock(&pvh_global_lock);
1834 for (; va < endva; va += PAGE_SIZE) {
1835 pte = pte_find(mmu, pmap, va);
1836 if ((pte != NULL) && PTE_ISVALID(pte))
1837 pte_remove(mmu, pmap, va, hold_flag);
1840 rw_wunlock(&pvh_global_lock);
1842 //debugf("mmu_booke_remove: e\n");
1846 * Remove physical page from all pmaps in which it resides.
1849 mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1854 rw_wlock(&pvh_global_lock);
1855 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1856 pvn = TAILQ_NEXT(pv, pv_link);
1858 PMAP_LOCK(pv->pv_pmap);
1859 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1860 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1861 PMAP_UNLOCK(pv->pv_pmap);
1863 vm_page_aflag_clear(m, PGA_WRITEABLE);
1864 rw_wunlock(&pvh_global_lock);
1868 * Map a range of physical addresses into kernel virtual address space.
1871 mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1872 vm_paddr_t pa_end, int prot)
1874 vm_offset_t sva = *virt;
1875 vm_offset_t va = sva;
1877 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1878 // sva, pa_start, pa_end);
1880 while (pa_start < pa_end) {
1881 mmu_booke_kenter(mmu, va, pa_start);
1883 pa_start += PAGE_SIZE;
1887 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1892 * The pmap must be activated before it's address space can be accessed in any
1896 mmu_booke_activate(mmu_t mmu, struct thread *td)
1901 pmap = &td->td_proc->p_vmspace->vm_pmap;
1903 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1904 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1906 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1908 mtx_lock_spin(&sched_lock);
1910 cpuid = PCPU_GET(cpuid);
1911 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1912 PCPU_SET(curpmap, pmap);
1914 if (pmap->pm_tid[cpuid] == TID_NONE)
1917 /* Load PID0 register with pmap tid value. */
1918 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1919 __asm __volatile("isync");
1921 mtx_unlock_spin(&sched_lock);
1923 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1924 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1928 * Deactivate the specified process's address space.
1931 mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1935 pmap = &td->td_proc->p_vmspace->vm_pmap;
1937 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1938 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1940 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1941 PCPU_SET(curpmap, NULL);
1945 * Copy the range specified by src_addr/len
1946 * from the source map to the range dst_addr/len
1947 * in the destination map.
1949 * This routine is only advisory and need not do anything.
1952 mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1953 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1959 * Set the physical protection on the specified range of this map as requested.
1962 mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1969 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1970 mmu_booke_remove(mmu, pmap, sva, eva);
1974 if (prot & VM_PROT_WRITE)
1978 for (va = sva; va < eva; va += PAGE_SIZE) {
1979 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
1980 if (PTE_ISVALID(pte)) {
1981 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1983 mtx_lock_spin(&tlbivax_mutex);
1986 /* Handle modified pages. */
1987 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1990 tlb0_flush_entry(va);
1991 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1994 mtx_unlock_spin(&tlbivax_mutex);
2002 * Clear the write and modified bits in each of the given page's mappings.
2005 mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2010 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2011 ("mmu_booke_remove_write: page %p is not managed", m));
2014 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2015 * set by another thread while the object is locked. Thus,
2016 * if PGA_WRITEABLE is clear, no page table entries need updating.
2018 VM_OBJECT_ASSERT_WLOCKED(m->object);
2019 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2021 rw_wlock(&pvh_global_lock);
2022 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2023 PMAP_LOCK(pv->pv_pmap);
2024 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2025 if (PTE_ISVALID(pte)) {
2026 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2028 mtx_lock_spin(&tlbivax_mutex);
2031 /* Handle modified pages. */
2032 if (PTE_ISMODIFIED(pte))
2035 /* Flush mapping from TLB0. */
2036 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2039 mtx_unlock_spin(&tlbivax_mutex);
2042 PMAP_UNLOCK(pv->pv_pmap);
2044 vm_page_aflag_clear(m, PGA_WRITEABLE);
2045 rw_wunlock(&pvh_global_lock);
2049 mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2058 va = trunc_page(va);
2059 sz = round_page(sz);
2061 rw_wlock(&pvh_global_lock);
2062 pmap = PCPU_GET(curpmap);
2063 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2066 pte = pte_find(mmu, pm, va);
2067 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2073 /* Create a mapping in the active pmap. */
2075 m = PHYS_TO_VM_PAGE(pa);
2077 pte_enter(mmu, pmap, m, addr,
2078 PTE_SR | PTE_VALID | PTE_UR);
2079 __syncicache((void *)addr, PAGE_SIZE);
2080 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2083 __syncicache((void *)va, PAGE_SIZE);
2088 rw_wunlock(&pvh_global_lock);
2092 * Atomically extract and hold the physical page with the given
2093 * pmap and virtual address pair if that mapping permits the given
2097 mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2109 pte = pte_find(mmu, pmap, va);
2110 if ((pte != NULL) && PTE_ISVALID(pte)) {
2111 if (pmap == kernel_pmap)
2116 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2117 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2119 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2130 * Initialize a vm_page's machine-dependent fields.
2133 mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2136 TAILQ_INIT(&m->md.pv_list);
2140 * mmu_booke_zero_page_area zeros the specified hardware page by
2141 * mapping it into virtual memory and using bzero to clear
2144 * off and size must reside within a single page.
2147 mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2151 /* XXX KASSERT off and size are within a single page? */
2153 mtx_lock(&zero_page_mutex);
2156 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2157 bzero((caddr_t)va + off, size);
2158 mmu_booke_kremove(mmu, va);
2160 mtx_unlock(&zero_page_mutex);
2164 * mmu_booke_zero_page zeros the specified hardware page.
2167 mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2170 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2174 * mmu_booke_copy_page copies the specified (machine independent) page by
2175 * mapping the page into virtual memory and using memcopy to copy the page,
2176 * one machine dependent page at a time.
2179 mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2181 vm_offset_t sva, dva;
2183 sva = copy_page_src_va;
2184 dva = copy_page_dst_va;
2186 mtx_lock(©_page_mutex);
2187 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2188 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2189 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2190 mmu_booke_kremove(mmu, dva);
2191 mmu_booke_kremove(mmu, sva);
2192 mtx_unlock(©_page_mutex);
2196 mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2197 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2200 vm_offset_t a_pg_offset, b_pg_offset;
2203 mtx_lock(©_page_mutex);
2204 while (xfersize > 0) {
2205 a_pg_offset = a_offset & PAGE_MASK;
2206 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2207 mmu_booke_kenter(mmu, copy_page_src_va,
2208 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2209 a_cp = (char *)copy_page_src_va + a_pg_offset;
2210 b_pg_offset = b_offset & PAGE_MASK;
2211 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2212 mmu_booke_kenter(mmu, copy_page_dst_va,
2213 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2214 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2215 bcopy(a_cp, b_cp, cnt);
2216 mmu_booke_kremove(mmu, copy_page_dst_va);
2217 mmu_booke_kremove(mmu, copy_page_src_va);
2222 mtx_unlock(©_page_mutex);
2226 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2227 * into virtual memory and using bzero to clear its contents. This is intended
2228 * to be called from the vm_pagezero process only and outside of Giant. No
2232 mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2236 va = zero_page_idle_va;
2237 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2238 bzero((caddr_t)va, PAGE_SIZE);
2239 mmu_booke_kremove(mmu, va);
2243 * Return whether or not the specified physical page was modified
2244 * in any of physical maps.
2247 mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2253 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2254 ("mmu_booke_is_modified: page %p is not managed", m));
2258 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2259 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2260 * is clear, no PTEs can be modified.
2262 VM_OBJECT_ASSERT_WLOCKED(m->object);
2263 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2265 rw_wlock(&pvh_global_lock);
2266 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2267 PMAP_LOCK(pv->pv_pmap);
2268 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2270 if (PTE_ISMODIFIED(pte))
2273 PMAP_UNLOCK(pv->pv_pmap);
2277 rw_wunlock(&pvh_global_lock);
2282 * Return whether or not the specified virtual address is eligible
2286 mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2293 * Return whether or not the specified physical page was referenced
2294 * in any physical maps.
2297 mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2303 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2304 ("mmu_booke_is_referenced: page %p is not managed", m));
2306 rw_wlock(&pvh_global_lock);
2307 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2308 PMAP_LOCK(pv->pv_pmap);
2309 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2311 if (PTE_ISREFERENCED(pte))
2314 PMAP_UNLOCK(pv->pv_pmap);
2318 rw_wunlock(&pvh_global_lock);
2323 * Clear the modify bits on the specified physical page.
2326 mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2331 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2332 ("mmu_booke_clear_modify: page %p is not managed", m));
2333 VM_OBJECT_ASSERT_WLOCKED(m->object);
2334 KASSERT(!vm_page_xbusied(m),
2335 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2338 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2339 * If the object containing the page is locked and the page is not
2340 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2342 if ((m->aflags & PGA_WRITEABLE) == 0)
2344 rw_wlock(&pvh_global_lock);
2345 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2346 PMAP_LOCK(pv->pv_pmap);
2347 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2349 mtx_lock_spin(&tlbivax_mutex);
2352 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2353 tlb0_flush_entry(pv->pv_va);
2354 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2359 mtx_unlock_spin(&tlbivax_mutex);
2361 PMAP_UNLOCK(pv->pv_pmap);
2363 rw_wunlock(&pvh_global_lock);
2367 * Return a count of reference bits for a page, clearing those bits.
2368 * It is not necessary for every reference bit to be cleared, but it
2369 * is necessary that 0 only be returned when there are truly no
2370 * reference bits set.
2372 * XXX: The exact number of bits to check and clear is a matter that
2373 * should be tested and standardized at some point in the future for
2374 * optimal aging of shared pages.
2377 mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2383 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2384 ("mmu_booke_ts_referenced: page %p is not managed", m));
2386 rw_wlock(&pvh_global_lock);
2387 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2388 PMAP_LOCK(pv->pv_pmap);
2389 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2391 if (PTE_ISREFERENCED(pte)) {
2392 mtx_lock_spin(&tlbivax_mutex);
2395 tlb0_flush_entry(pv->pv_va);
2396 pte->flags &= ~PTE_REFERENCED;
2399 mtx_unlock_spin(&tlbivax_mutex);
2402 PMAP_UNLOCK(pv->pv_pmap);
2407 PMAP_UNLOCK(pv->pv_pmap);
2409 rw_wunlock(&pvh_global_lock);
2414 * Change wiring attribute for a map/virtual-address pair.
2417 mmu_booke_change_wiring(mmu_t mmu, pmap_t pmap, vm_offset_t va, boolean_t wired)
2422 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2424 if (!PTE_ISWIRED(pte)) {
2425 pte->flags |= PTE_WIRED;
2426 pmap->pm_stats.wired_count++;
2429 if (PTE_ISWIRED(pte)) {
2430 pte->flags &= ~PTE_WIRED;
2431 pmap->pm_stats.wired_count--;
2439 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2440 * page. This count may be changed upwards or downwards in the future; it is
2441 * only necessary that true be returned for a small subset of pmaps for proper
2445 mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2451 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2452 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2455 rw_wlock(&pvh_global_lock);
2456 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2457 if (pv->pv_pmap == pmap) {
2464 rw_wunlock(&pvh_global_lock);
2469 * Return the number of managed mappings to the given physical page that are
2473 mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2479 if ((m->oflags & VPO_UNMANAGED) != 0)
2481 rw_wlock(&pvh_global_lock);
2482 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2483 PMAP_LOCK(pv->pv_pmap);
2484 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2485 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2487 PMAP_UNLOCK(pv->pv_pmap);
2489 rw_wunlock(&pvh_global_lock);
2494 mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2500 * This currently does not work for entries that
2501 * overlap TLB1 entries.
2503 for (i = 0; i < tlb1_idx; i ++) {
2504 if (tlb1_iomapped(i, pa, size, &va) == 0)
2512 mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2519 /* Raw physical memory dumps don't have a virtual address. */
2520 if (md->md_vaddr == ~0UL) {
2521 /* We always map a 256MB page at 256M. */
2522 gran = 256 * 1024 * 1024;
2523 pa = md->md_paddr + ofs;
2524 ppa = pa & ~(gran - 1);
2527 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2528 if (*sz > (gran - ofs))
2533 /* Minidumps are based on virtual memory addresses. */
2534 va = md->md_vaddr + ofs;
2535 if (va >= kernstart + kernsize) {
2536 gran = PAGE_SIZE - (va & PAGE_MASK);
2544 mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2548 /* Raw physical memory dumps don't have a virtual address. */
2549 if (md->md_vaddr == ~0UL) {
2551 tlb1[tlb1_idx].mas1 = 0;
2552 tlb1[tlb1_idx].mas2 = 0;
2553 tlb1[tlb1_idx].mas3 = 0;
2554 tlb1_write_entry(tlb1_idx);
2558 /* Minidumps are based on virtual memory addresses. */
2559 /* Nothing to do... */
2563 mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2565 static struct pmap_md md;
2569 if (dumpsys_minidump) {
2570 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2572 /* 1st: kernel .data and .bss. */
2574 md.md_vaddr = trunc_page((uintptr_t)_etext);
2575 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2578 switch (prev->md_index) {
2580 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2582 md.md_vaddr = data_start;
2583 md.md_size = data_end - data_start;
2586 /* 3rd: kernel VM. */
2587 va = prev->md_vaddr + prev->md_size;
2588 /* Find start of next chunk (from va). */
2589 while (va < virtual_end) {
2590 /* Don't dump the buffer cache. */
2591 if (va >= kmi.buffer_sva &&
2592 va < kmi.buffer_eva) {
2593 va = kmi.buffer_eva;
2596 pte = pte_find(mmu, kernel_pmap, va);
2597 if (pte != NULL && PTE_ISVALID(pte))
2601 if (va < virtual_end) {
2604 /* Find last page in chunk. */
2605 while (va < virtual_end) {
2606 /* Don't run into the buffer cache. */
2607 if (va == kmi.buffer_sva)
2609 pte = pte_find(mmu, kernel_pmap, va);
2610 if (pte == NULL || !PTE_ISVALID(pte))
2614 md.md_size = va - md.md_vaddr;
2622 } else { /* minidumps */
2623 mem_regions(&physmem_regions, &physmem_regions_sz,
2624 &availmem_regions, &availmem_regions_sz);
2627 /* first physical chunk. */
2628 md.md_paddr = physmem_regions[0].mr_start;
2629 md.md_size = physmem_regions[0].mr_size;
2632 } else if (md.md_index < physmem_regions_sz) {
2633 md.md_paddr = physmem_regions[md.md_index].mr_start;
2634 md.md_size = physmem_regions[md.md_index].mr_size;
2638 /* There's no next physical chunk. */
2647 * Map a set of physical memory pages into the kernel virtual address space.
2648 * Return a pointer to where it is mapped. This routine is intended to be used
2649 * for mapping device memory, NOT real memory.
2652 mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2655 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2659 mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2667 * Check if this is premapped in TLB1. Note: this should probably also
2668 * check whether a sequence of TLB1 entries exist that match the
2669 * requirement, but now only checks the easy case.
2671 if (ma == VM_MEMATTR_DEFAULT) {
2672 for (i = 0; i < tlb1_idx; i++) {
2673 if (!(tlb1[i].mas1 & MAS1_VALID))
2675 if (pa >= tlb1[i].phys &&
2676 (pa + size) <= (tlb1[i].phys + tlb1[i].size))
2677 return (void *)(tlb1[i].virt +
2678 (pa - tlb1[i].phys));
2682 size = roundup(size, PAGE_SIZE);
2684 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) &&
2685 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS)
2688 va = kva_alloc(size);
2692 sz = 1 << (ilog2(size) & ~1);
2694 printf("Wiring VA=%x to PA=%x (size=%x), "
2695 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2696 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma));
2706 * 'Unmap' a range mapped by mmu_booke_mapdev().
2709 mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2711 #ifdef SUPPORTS_SHRINKING_TLB1
2712 vm_offset_t base, offset;
2715 * Unmap only if this is inside kernel virtual space.
2717 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2718 base = trunc_page(va);
2719 offset = va & PAGE_MASK;
2720 size = roundup(offset + size, PAGE_SIZE);
2721 kva_free(base, size);
2727 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2728 * specified pmap. This eliminates the blast of soft faults on process startup
2729 * and immediately after an mmap.
2732 mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2733 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2736 VM_OBJECT_ASSERT_WLOCKED(object);
2737 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2738 ("mmu_booke_object_init_pt: non-device object"));
2742 * Perform the pmap work for mincore.
2745 mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2746 vm_paddr_t *locked_pa)
2753 /**************************************************************************/
2755 /**************************************************************************/
2758 * Allocate a TID. If necessary, steal one from someone else.
2759 * The new TID is flushed from the TLB before returning.
2762 tid_alloc(pmap_t pmap)
2767 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2769 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2771 thiscpu = PCPU_GET(cpuid);
2773 tid = PCPU_GET(tid_next);
2776 PCPU_SET(tid_next, tid + 1);
2778 /* If we are stealing TID then clear the relevant pmap's field */
2779 if (tidbusy[thiscpu][tid] != NULL) {
2781 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2783 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2785 /* Flush all entries from TLB0 matching this TID. */
2789 tidbusy[thiscpu][tid] = pmap;
2790 pmap->pm_tid[thiscpu] = tid;
2791 __asm __volatile("msync; isync");
2793 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2794 PCPU_GET(tid_next));
2799 /**************************************************************************/
2801 /**************************************************************************/
2804 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2814 if (mas1 & MAS1_VALID)
2819 if (mas1 & MAS1_IPROT)
2824 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2825 tid = MAS1_GETTID(mas1);
2827 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2830 size = tsize2size(tsize);
2832 debugf("%3d: (%s) [AS=%d] "
2833 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2834 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2835 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2838 /* Convert TLB0 va and way number to tlb0[] table index. */
2839 static inline unsigned int
2840 tlb0_tableidx(vm_offset_t va, unsigned int way)
2844 idx = (way * TLB0_ENTRIES_PER_WAY);
2845 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2850 * Invalidate TLB0 entry.
2853 tlb0_flush_entry(vm_offset_t va)
2856 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2858 mtx_assert(&tlbivax_mutex, MA_OWNED);
2860 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2861 __asm __volatile("isync; msync");
2862 __asm __volatile("tlbsync; msync");
2864 CTR1(KTR_PMAP, "%s: e", __func__);
2867 /* Print out contents of the MAS registers for each TLB0 entry */
2869 tlb0_print_tlbentries(void)
2871 uint32_t mas0, mas1, mas2, mas3, mas7;
2872 int entryidx, way, idx;
2874 debugf("TLB0 entries:\n");
2875 for (way = 0; way < TLB0_WAYS; way ++)
2876 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2878 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2879 mtspr(SPR_MAS0, mas0);
2880 __asm __volatile("isync");
2882 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2883 mtspr(SPR_MAS2, mas2);
2885 __asm __volatile("isync; tlbre");
2887 mas1 = mfspr(SPR_MAS1);
2888 mas2 = mfspr(SPR_MAS2);
2889 mas3 = mfspr(SPR_MAS3);
2890 mas7 = mfspr(SPR_MAS7);
2892 idx = tlb0_tableidx(mas2, way);
2893 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2897 /**************************************************************************/
2899 /**************************************************************************/
2902 * TLB1 mapping notes:
2904 * TLB1[0] Kernel text and data.
2905 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2906 * windows, other devices mappings.
2910 * Write given entry to TLB1 hardware.
2911 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2914 tlb1_write_entry(unsigned int idx)
2916 uint32_t mas0, mas7;
2918 //debugf("tlb1_write_entry: s\n");
2920 /* Clear high order RPN bits */
2924 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2925 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2927 mtspr(SPR_MAS0, mas0);
2928 __asm __volatile("isync");
2929 mtspr(SPR_MAS1, tlb1[idx].mas1);
2930 __asm __volatile("isync");
2931 mtspr(SPR_MAS2, tlb1[idx].mas2);
2932 __asm __volatile("isync");
2933 mtspr(SPR_MAS3, tlb1[idx].mas3);
2934 __asm __volatile("isync");
2935 mtspr(SPR_MAS7, mas7);
2936 __asm __volatile("isync; tlbwe; isync; msync");
2938 //debugf("tlb1_write_entry: e\n");
2942 * Return the largest uint value log such that 2^log <= num.
2945 ilog2(unsigned int num)
2949 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2954 * Convert TLB TSIZE value to mapped region size.
2957 tsize2size(unsigned int tsize)
2962 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2965 return ((1 << (2 * tsize)) * 1024);
2969 * Convert region size (must be power of 4) to TLB TSIZE value.
2972 size2tsize(vm_size_t size)
2975 return (ilog2(size) / 2 - 5);
2979 * Register permanent kernel mapping in TLB1.
2981 * Entries are created starting from index 0 (current free entry is
2982 * kept in tlb1_idx) and are not supposed to be invalidated.
2985 tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
2991 index = atomic_fetchadd_int(&tlb1_idx, 1);
2992 if (index >= TLB1_ENTRIES) {
2993 printf("tlb1_set_entry: TLB1 full!\n");
2997 /* Convert size to TSIZE */
2998 tsize = size2tsize(size);
3000 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3001 /* XXX TS is hard coded to 0 for now as we only use single address space */
3002 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3005 * Atomicity is preserved by the atomic increment above since nothing
3006 * is ever removed from tlb1.
3009 tlb1[index].phys = pa;
3010 tlb1[index].virt = va;
3011 tlb1[index].size = size;
3012 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3013 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3014 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags;
3016 /* Set supervisor RWX permission bits */
3017 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3019 tlb1_write_entry(index);
3022 * XXX in general TLB1 updates should be propagated between CPUs,
3023 * since current design assumes to have the same TLB1 set-up on all
3030 * Map in contiguous RAM region into the TLB1 using maximum of
3031 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3033 * If necessary round up last entry size and return total size
3034 * used by all allocated entries.
3037 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3039 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3040 vm_size_t mapped, pgsz, base, mask;
3043 /* Round up to the next 1M */
3044 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
3049 pgsz = 64*1024*1024;
3050 while (mapped < size) {
3051 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3052 while (pgsz > (size - mapped))
3058 /* We under-map. Correct for this. */
3059 if (mapped < size) {
3060 while (pgs[idx - 1] == pgsz) {
3064 /* XXX We may increase beyond out starting point. */
3073 /* Align address to the boundary */
3075 va = (va + mask) & ~mask;
3076 pa = (pa + mask) & ~mask;
3079 for (idx = 0; idx < nents; idx++) {
3081 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3082 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3087 mapped = (va - base);
3088 debugf("mapped size 0x%08x (wasted space 0x%08x)\n",
3089 mapped, mapped - size);
3094 * TLB1 initialization routine, to be called after the very first
3095 * assembler level setup done in locore.S.
3100 uint32_t mas0, mas1, mas2, mas3;
3104 if (bootinfo != NULL && bootinfo[0] != 1) {
3105 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3109 /* The first entry/entries are used to map the kernel. */
3110 for (i = 0; i < tlb1_idx; i++) {
3111 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3112 mtspr(SPR_MAS0, mas0);
3113 __asm __volatile("isync; tlbre");
3115 mas1 = mfspr(SPR_MAS1);
3116 if ((mas1 & MAS1_VALID) == 0)
3119 mas2 = mfspr(SPR_MAS2);
3120 mas3 = mfspr(SPR_MAS3);
3122 tlb1[i].mas1 = mas1;
3123 tlb1[i].mas2 = mfspr(SPR_MAS2);
3124 tlb1[i].mas3 = mas3;
3125 tlb1[i].virt = mas2 & MAS2_EPN_MASK;
3126 tlb1[i].phys = mas3 & MAS3_RPN;
3129 kernload = mas3 & MAS3_RPN;
3131 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3132 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0;
3133 kernsize += tlb1[i].size;
3137 bp_ntlb1s = tlb1_idx;
3140 /* Purge the remaining entries */
3141 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3142 tlb1_write_entry(i);
3144 /* Setup TLB miss defaults */
3145 set_mas4_defaults();
3149 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
3151 static vm_offset_t early_io_map_base = VM_MAX_KERNEL_ADDRESS;
3156 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
3158 for (i = 0; i < tlb1_idx; i++) {
3159 if (!(tlb1[i].mas1 & MAS1_VALID))
3161 if (pa >= tlb1[i].phys && (pa + size) <=
3162 (tlb1[i].phys + tlb1[i].size))
3163 return (tlb1[i].virt + (pa - tlb1[i].phys));
3166 pa_base = trunc_page(pa);
3167 size = roundup(size + (pa - pa_base), PAGE_SIZE);
3168 va = early_io_map_base + (pa - pa_base);
3171 sz = 1 << (ilog2(size) & ~1);
3172 tlb1_set_entry(early_io_map_base, pa_base, sz, _TLB_ENTRY_IO);
3175 early_io_map_base += sz;
3179 bp_ntlb1s = tlb1_idx;
3186 * Setup MAS4 defaults.
3187 * These values are loaded to MAS0-2 on a TLB miss.
3190 set_mas4_defaults(void)
3194 /* Defaults: TLB0, PID0, TSIZED=4K */
3195 mas4 = MAS4_TLBSELD0;
3196 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3200 mtspr(SPR_MAS4, mas4);
3201 __asm __volatile("isync");
3205 * Print out contents of the MAS registers for each TLB1 entry
3208 tlb1_print_tlbentries(void)
3210 uint32_t mas0, mas1, mas2, mas3, mas7;
3213 debugf("TLB1 entries:\n");
3214 for (i = 0; i < TLB1_ENTRIES; i++) {
3216 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3217 mtspr(SPR_MAS0, mas0);
3219 __asm __volatile("isync; tlbre");
3221 mas1 = mfspr(SPR_MAS1);
3222 mas2 = mfspr(SPR_MAS2);
3223 mas3 = mfspr(SPR_MAS3);
3224 mas7 = mfspr(SPR_MAS7);
3226 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3231 * Print out contents of the in-ram tlb1 table.
3234 tlb1_print_entries(void)
3238 debugf("tlb1[] table entries:\n");
3239 for (i = 0; i < TLB1_ENTRIES; i++)
3240 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3244 * Return 0 if the physical IO range is encompassed by one of the
3245 * the TLB1 entries, otherwise return related error code.
3248 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3251 vm_paddr_t pa_start;
3253 unsigned int entry_tsize;
3254 vm_size_t entry_size;
3256 *va = (vm_offset_t)NULL;
3258 /* Skip invalid entries */
3259 if (!(tlb1[i].mas1 & MAS1_VALID))
3263 * The entry must be cache-inhibited, guarded, and r/w
3264 * so it can function as an i/o page
3266 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3267 if (prot != (MAS2_I | MAS2_G))
3270 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3271 if (prot != (MAS3_SR | MAS3_SW))
3274 /* The address should be within the entry range. */
3275 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3276 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3278 entry_size = tsize2size(entry_tsize);
3279 pa_start = tlb1[i].mas3 & MAS3_RPN;
3280 pa_end = pa_start + entry_size - 1;
3282 if ((pa < pa_start) || ((pa + size) > pa_end))
3285 /* Return virtual address of this mapping. */
3286 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);