1 /* $NetBSD: fpu_div.c,v 1.4 2005/12/11 12:18:42 christos Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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40 * @(#)fpu_div.c 8.1 (Berkeley) 6/11/93
44 * Perform an FPU divide (return x / y).
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
50 #include <sys/types.h>
51 #include <sys/systm.h>
53 #include <machine/fpu.h>
54 #include <machine/reg.h>
56 #include <powerpc/fpu/fpu_arith.h>
57 #include <powerpc/fpu/fpu_emu.h>
60 * Division of normal numbers is done as follows:
62 * x and y are floating point numbers, i.e., in the form 1.bbbb * 2^e.
63 * If X and Y are the mantissas (1.bbbb's), the quotient is then:
65 * q = (X / Y) * 2^((x exponent) - (y exponent))
67 * Since X and Y are both in [1.0,2.0), the quotient's mantissa (X / Y)
68 * will be in [0.5,2.0). Moreover, it will be less than 1.0 if and only
69 * if X < Y. In that case, it will have to be shifted left one bit to
70 * become a normal number, and the exponent decremented. Thus, the
71 * desired exponent is:
73 * left_shift = x->fp_mant < y->fp_mant;
74 * result_exp = x->fp_exp - y->fp_exp - left_shift;
76 * The quotient mantissa X/Y can then be computed one bit at a time
77 * using the following algorithm:
79 * Q = 0; -- Initial quotient.
80 * R = X; -- Initial remainder,
81 * if (left_shift) -- but fixed up in advance.
83 * for (bit = FP_NMANT; --bit >= 0; R *= 2) {
90 * The subtraction R -= Y always removes the uppermost bit from R (and
91 * can sometimes remove additional lower-order 1 bits); this proof is
94 * This loop correctly calculates the guard and round bits since they are
95 * included in the expanded internal representation. The sticky bit
96 * is to be set if and only if any other bits beyond guard and round
97 * would be set. From the above it is obvious that this is true if and
98 * only if the remainder R is nonzero when the loop terminates.
100 * Examining the loop above, we can see that the quotient Q is built
101 * one bit at a time ``from the top down''. This means that we can
102 * dispense with the multi-word arithmetic and just build it one word
103 * at a time, writing each result word when it is done.
105 * Furthermore, since X and Y are both in [1.0,2.0), we know that,
106 * initially, R >= Y. (Recall that, if X < Y, R is set to X * 2 and
107 * is therefore at in [2.0,4.0).) Thus Q is sure to have bit FP_NMANT-1
108 * set, and R can be set initially to either X - Y (when X >= Y) or
109 * 2X - Y (when X < Y). In addition, comparing R and Y is difficult,
110 * so we will simply calculate R - Y and see if that underflows.
111 * This leads to the following revised version of the algorithm:
117 * result_exp = x->fp_exp - y->fp_exp;
122 * result_exp = x->fp_exp - y->fp_exp - 1;
133 * } while ((bit >>= 1) != 0);
135 * for (i = 1; i < 4; i++) {
136 * q = 0, bit = 1 << 31;
144 * } while ((bit >>= 1) != 0);
148 * This can be refined just a bit further by moving the `R <<= 1'
149 * calculations to the front of the do-loops and eliding the first one.
150 * The process can be terminated immediately whenever R becomes 0, but
151 * this is relatively rare, and we do not bother.
155 fpu_div(struct fpemu *fe)
157 struct fpn *x = &fe->fe_f1, *y = &fe->fe_f2;
159 u_int r0, r1, r2, r3, d0, d1, d2, d3, y0, y1, y2, y3;
163 * Since divide is not commutative, we cannot just use ORDER.
164 * Check either operand for NaN first; if there is at least one,
165 * order the signalling one (if only one) onto the right, then
166 * return it. Otherwise we have the following cases:
168 * Inf / Inf = NaN, plus NV exception
169 * Inf / num = Inf [i.e., return x]
170 * Inf / 0 = Inf [i.e., return x]
171 * 0 / Inf = 0 [i.e., return x]
172 * 0 / num = 0 [i.e., return x]
173 * 0 / 0 = NaN, plus NV exception
175 * num / num = num (do the divide)
176 * num / 0 = Inf, plus DZ exception
178 DPRINTF(FPE_REG, ("fpu_div:\n"));
181 DPRINTF(FPE_REG, ("=>\n"));
182 if (ISNAN(x) || ISNAN(y)) {
184 fe->fe_cx |= FPSCR_VXSNAN;
189 * Need to split the following out cause they generate different
193 if (x->fp_class == y->fp_class) {
194 fe->fe_cx |= FPSCR_VXIDI;
195 return (fpu_newnan(fe));
201 fe->fe_cx |= FPSCR_ZX;
202 if (x->fp_class == y->fp_class) {
203 fe->fe_cx |= FPSCR_VXZDZ;
204 return (fpu_newnan(fe));
210 /* all results at this point use XOR of operand signs */
211 x->fp_sign ^= y->fp_sign;
213 x->fp_class = FPC_ZERO;
218 fe->fe_cx = FPSCR_ZX;
219 x->fp_class = FPC_INF;
225 * Macros for the divide. See comments at top for algorithm.
226 * Note that we expand R, D, and Y here.
229 #define SUBTRACT /* D = R - Y */ \
230 FPU_SUBS(d3, r3, y3); FPU_SUBCS(d2, r2, y2); \
231 FPU_SUBCS(d1, r1, y1); FPU_SUBC(d0, r0, y0)
233 #define NONNEGATIVE /* D >= 0 */ \
236 #ifdef FPU_SHL1_BY_ADD
237 #define SHL1 /* R <<= 1 */ \
238 FPU_ADDS(r3, r3, r3); FPU_ADDCS(r2, r2, r2); \
239 FPU_ADDCS(r1, r1, r1); FPU_ADDC(r0, r0, r0)
242 r0 = (r0 << 1) | (r1 >> 31), r1 = (r1 << 1) | (r2 >> 31), \
243 r2 = (r2 << 1) | (r3 >> 31), r3 <<= 1
246 #define LOOP /* do ... while (bit >>= 1) */ \
252 r0 = d0, r1 = d1, r2 = d2, r3 = d3; \
254 } while ((bit >>= 1) != 0)
256 #define WORD(r, i) /* calculate r->fp_mant[i] */ \
262 /* Setup. Note that we put our result in x. */
275 x->fp_exp -= y->fp_exp;
276 r0 = d0, r1 = d1, r2 = d2, r3 = d3;
280 x->fp_exp -= y->fp_exp + 1;
288 x->fp_sticky = r0 | r1 | r2 | r3;