2 * Copyright (c) 1998 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_CPUFUNC_H_
30 #define _MACHINE_CPUFUNC_H_
33 * Required for user-space atomic.h includes
39 __asm __volatile("eieio; sync" : : : "memory");
44 #include <sys/types.h>
46 #include <machine/psl.h>
47 #include <machine/spr.h>
52 void breakpoint(void);
62 /* CPU register mangling inlines */
65 mtmsr(register_t value)
68 __asm __volatile ("mtmsr %0; isync" :: "r"(value));
73 mtmsrd(register_t value)
76 __asm __volatile ("mtmsrd %0; isync" :: "r"(value));
80 static __inline register_t
85 __asm __volatile ("mfmsr %0" : "=r"(value));
92 mtsrin(vm_offset_t va, register_t value)
95 __asm __volatile ("mtsrin %0,%1" :: "r"(value), "r"(va));
98 static __inline register_t
99 mfsrin(vm_offset_t va)
103 __asm __volatile ("mfsrin %0,%1" : "=r"(value) : "r"(va));
109 static __inline register_t
114 __asm __volatile ("mfspr %0,136" : "=r"(value));
121 mtdec(register_t value)
124 __asm __volatile ("mtdec %0" :: "r"(value));
127 static __inline register_t
132 __asm __volatile ("mfdec %0" : "=r"(value));
137 static __inline register_t
142 __asm __volatile ("mfpvr %0" : "=r"(value));
147 static __inline u_quad_t
152 __asm __volatile ("mftb %0" : "=r"(tb));
154 uint32_t *tbup = (uint32_t *)&tb;
155 uint32_t *tblp = tbup + 1;
158 *tbup = mfspr(TBR_TBU);
159 *tblp = mfspr(TBR_TBL);
160 } while (*tbup != mfspr(TBR_TBU));
171 mtspr(TBR_TBWU, (uint32_t)(time >> 32));
172 mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff));
179 __asm __volatile ("eieio" : : : "memory");
186 __asm __volatile ("isync" : : : "memory");
193 __asm __volatile ("sync" : : : "memory");
196 static __inline register_t
202 mtmsr(msr & ~PSL_EE);
207 intr_restore(register_t msr)
213 static __inline struct pcpu *
214 powerpc_get_pcpup(void)
218 __asm __volatile("mfsprg %0, 0" : "=r"(ret));
225 #endif /* !_MACHINE_CPUFUNC_H_ */