2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $
35 #ifndef _MACHINE_PSL_H_
36 #define _MACHINE_PSL_H_
38 #if defined(BOOKE_E500)
40 * Machine State Register (MSR) - e500 core
42 * The PowerPC e500 does not implement the following bits:
44 * FP, FE0, FE1 - reserved, always cleared, setting has no effect.
47 #define PSL_UCLE 0x04000000UL /* User mode cache lock enable */
48 #define PSL_SPE 0x02000000UL /* SPE enable */
49 #define PSL_WE 0x00040000UL /* Wait state enable */
50 #define PSL_CE 0x00020000UL /* Critical interrupt enable */
51 #define PSL_EE 0x00008000UL /* External interrupt enable */
52 #define PSL_PR 0x00004000UL /* User mode */
53 #define PSL_FP 0x00002000UL /* Floating point available */
54 #define PSL_ME 0x00001000UL /* Machine check interrupt enable */
55 #define PSL_FE0 0x00000800UL /* Floating point exception mode 0 */
56 #define PSL_UBLE 0x00000400UL /* BTB lock enable */
57 #define PSL_DE 0x00000200UL /* Debug interrupt enable */
58 #define PSL_FE1 0x00000100UL /* Floating point exception mode 1 */
59 #define PSL_IS 0x00000020UL /* Instruction address space */
60 #define PSL_DS 0x00000010UL /* Data address space */
61 #define PSL_PMM 0x00000004UL /* Performance monitor mark */
63 #define PSL_FE_DFLT 0x00000000UL /* default == none */
65 /* Initial kernel MSR, use IS=1 ad DS=1. */
66 #define PSL_KERNSET_INIT (PSL_IS | PSL_DS)
67 #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE)
68 #define PSL_USERSET (PSL_KERNSET | PSL_PR)
70 #elif defined(BOOKE_PPC4XX)
72 * Machine State Register (MSR) - PPC4xx core
74 #define PSL_WE (0x80000000 >> 13) /* Wait State Enable */
75 #define PSL_CE (0x80000000 >> 14) /* Critical Interrupt Enable */
76 #define PSL_EE (0x80000000 >> 16) /* External Interrupt Enable */
77 #define PSL_PR (0x80000000 >> 17) /* Problem State */
78 #define PSL_FP (0x80000000 >> 18) /* Floating Point Available */
79 #define PSL_ME (0x80000000 >> 19) /* Machine Check Enable */
80 #define PSL_FE0 (0x80000000 >> 20) /* Floating-point exception mode 0 */
81 #define PSL_DWE (0x80000000 >> 21) /* Debug Wait Enable */
82 #define PSL_DE (0x80000000 >> 22) /* Debug interrupt Enable */
83 #define PSL_FE1 (0x80000000 >> 23) /* Floating-point exception mode 1 */
84 #define PSL_IS (0x80000000 >> 26) /* Instruction Address Space */
85 #define PSL_DS (0x80000000 >> 27) /* Data Address Space */
87 #define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP)
88 #define PSL_USERSET (PSL_KERNSET | PSL_PR)
90 #define PSL_FE_DFLT 0x00000000UL /* default == none */
92 #else /* if defined(BOOKE_*) */
94 * Machine State Register (MSR)
96 * The PowerPC 601 does not implement the following bits:
98 * VEC, POW, ILE, BE, RI, LE[*]
100 * [*] Little-endian mode on the 601 is implemented in the HID0 register.
104 #define PSL_SF 0x8000000000000000UL /* 64-bit addressing */
105 #define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */
108 #define PSL_VEC 0x02000000UL /* AltiVec vector unit available */
109 #define PSL_POW 0x00040000UL /* power management */
110 #define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */
111 #define PSL_EE 0x00008000UL /* external interrupt enable */
112 #define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
113 #define PSL_FP 0x00002000UL /* floating point enable */
114 #define PSL_ME 0x00001000UL /* machine check enable */
115 #define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */
116 #define PSL_SE 0x00000400UL /* single-step trace enable */
117 #define PSL_BE 0x00000200UL /* branch trace enable */
118 #define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */
119 #define PSL_IP 0x00000040UL /* interrupt prefix */
120 #define PSL_IR 0x00000020UL /* instruction address relocation */
121 #define PSL_DR 0x00000010UL /* data address relocation */
122 #define PSL_PMM 0x00000004UL /* performance monitor mark */
123 #define PSL_RI 0x00000002UL /* recoverable interrupt */
124 #define PSL_LE 0x00000001UL /* endian mode (1 == le) */
126 #define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE)
129 * Floating-point exception modes:
131 #define PSL_FE_DIS 0 /* none */
132 #define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
133 #define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
134 #define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
135 #define PSL_FE_DFLT PSL_FE_DIS /* default == none */
138 * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR
144 #define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
146 #define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
148 #define PSL_USERSET (PSL_KERNSET | PSL_PR)
150 #define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c)
152 #endif /* if defined(BOOKE_E500) */
153 #endif /* _MACHINE_PSL_H_ */