sys/powerpc/mpc85xx/fsl_sdhc.h

   1 /*-
   2  * Copyright (c) 2011-2012 Semihalf
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  */
  28
  29 #ifndef FSL_SDHC_H_
  30 #define FSL_SDHC_H_
  31
  32 #include <sys/cdefs.h>
  33
  34 #include <sys/param.h>
  35 #include <sys/bus.h>
  36 #include <sys/kernel.h>
  37 #include <sys/lock.h>
  38 #include <sys/module.h>
  39 #include <sys/mutex.h>
  40 #include <sys/rman.h>
  41 #include <sys/sysctl.h>
  42 #include <sys/systm.h>
  43 #include <sys/taskqueue.h>
  44
  45 #include <machine/bus.h>
  46
  47 #include <dev/mmc/bridge.h>
  48 #include <dev/mmc/mmcreg.h>
  49 #include <dev/mmc/mmcbrvar.h>
  50
  51 /*****************************************************************************
  52  * Private defines
  53  *****************************************************************************/
  54 struct slot {
  55         uint32_t        clock;
  56 };
  57
  58 struct fsl_sdhc_softc {
  59         device_t                self;
  60         device_t                child;
  61
  62         bus_space_handle_t      bsh;
  63         bus_space_tag_t         bst;
  64
  65         struct resource         *mem_resource;
  66         int                     mem_rid;
  67         struct resource         *irq_resource;
  68         int                     irq_rid;
  69         void                    *ihl;
  70
  71         bus_dma_tag_t           dma_tag;
  72         bus_dmamap_t            dma_map;
  73         uint32_t*               dma_mem;
  74         bus_addr_t              dma_phys;
  75
  76         struct mtx              mtx;
  77
  78         struct task             card_detect_task;
  79         struct callout          card_detect_callout;
  80
  81         struct mmc_host         mmc_host;
  82
  83         struct slot             slot;
  84         uint32_t                bus_busy;
  85         uint32_t                platform_clock;
  86
  87         struct mmc_request      *request;
  88         int                     data_done;
  89         int                     command_done;
  90         int                     use_dma;
  91         uint32_t*               data_ptr;
  92         uint32_t                data_offset;
  93 };
  94
  95 #define FSL_SDHC_RESET_DELAY 50
  96
  97 #define FSL_SDHC_BASE_CLOCK_DIV         (2)
  98 #define FSL_SDHC_MAX_DIV                (FSL_SDHC_BASE_CLOCK_DIV * 256 * 16)
  99 #define FSL_SDHC_MIN_DIV                (FSL_SDHC_BASE_CLOCK_DIV * 2)
 100 #define FSL_SDHC_MAX_CLOCK              (50000000)
 101
 102 #define FSL_SDHC_MAX_BLOCK_COUNT        (65535)
 103 #define FSL_SDHC_MAX_BLOCK_SIZE         (4096)
 104
 105 #define FSL_SDHC_FIFO_BUF_SIZE          (64)    /* Water-mark level. */
 106 #define FSL_SDHC_FIFO_BUF_WORDS         (FSL_SDHC_FIFO_BUF_SIZE / 4)
 107
 108 #define FSL_SDHC_DMA_SEGMENT_SIZE       (1024)
 109 #define FSL_SDHC_DMA_ALIGNMENT          (4)
 110 #define FSL_SDHC_DMA_BLOCK_SIZE         FSL_SDHC_MAX_BLOCK_SIZE
 111
 112 /*
 113  * Offsets of SD HC registers
 114  */
 115 enum sdhc_reg_off {
 116         SDHC_DSADDR     = 0x000,
 117         SDHC_BLKATTR    = 0x004,
 118         SDHC_CMDARG     = 0x008,
 119         SDHC_XFERTYP    = 0x00c,
 120         SDHC_CMDRSP0    = 0x010,
 121         SDHC_CMDRSP1    = 0x014,
 122         SDHC_CMDRSP2    = 0x018,
 123         SDHC_CMDRSP3    = 0x01c,
 124         SDHC_DATPORT    = 0x020,
 125         SDHC_PRSSTAT    = 0x024,
 126         SDHC_PROCTL     = 0x028,
 127         SDHC_SYSCTL     = 0x02c,
 128         SDHC_IRQSTAT    = 0x030,
 129         SDHC_IRQSTATEN  = 0x034,
 130         SDHC_IRQSIGEN   = 0x038,
 131         SDHC_AUTOC12ERR = 0x03c,
 132         SDHC_HOSTCAPBLT = 0x040,
 133         SDHC_WML        = 0x044,
 134         SDHC_FEVT       = 0x050,
 135         SDHC_HOSTVER    = 0x0fc,
 136         SDHC_DCR        = 0x40c
 137 };
 138
 139 enum sysctl_bit {
 140         SYSCTL_INITA    = 0x08000000,
 141         SYSCTL_RSTD     = 0x04000000,
 142         SYSCTL_RSTC     = 0x02000000,
 143         SYSCTL_RSTA     = 0x01000000,
 144         SYSCTL_DTOCV    = 0x000f0000,
 145         SYSCTL_SDCLKFS  = 0x0000ff00,
 146         SYSCTL_DVS      = 0x000000f0,
 147         SYSCTL_PEREN    = 0x00000004,
 148         SYSCTL_HCKEN    = 0x00000002,
 149         SYSCTL_IPGEN    = 0x00000001
 150 };
 151
 152 #define HEX_LEFT_SHIFT(x)       (4 * x)
 153 enum sysctl_shift {
 154         SHIFT_DTOCV     = HEX_LEFT_SHIFT(4),
 155         SHIFT_SDCLKFS   = HEX_LEFT_SHIFT(2),
 156         SHIFT_DVS       = HEX_LEFT_SHIFT(1)
 157 };
 158
 159 enum proctl_bit {
 160         PROCTL_WECRM    = 0x04000000,
 161         PROCTL_WECINS   = 0x02000000,
 162         PROCTL_WECINT   = 0x01000000,
 163         PROCTL_RWCTL    = 0x00040000,
 164         PROCTL_CREQ     = 0x00020000,
 165         PROCTL_SABGREQ  = 0x00010000,
 166         PROCTL_CDSS     = 0x00000080,
 167         PROCTL_CDTL     = 0x00000040,
 168         PROCTL_EMODE    = 0x00000030,
 169         PROCTL_D3CD     = 0x00000008,
 170         PROCTL_DTW      = 0x00000006
 171 };
 172
 173 enum dtw {
 174         DTW_1   = 0x00000000,
 175         DTW_4   = 0x00000002,
 176         DTW_8   = 0x00000004
 177 };
 178
 179 enum prsstat_bit {
 180         PRSSTAT_DLSL    = 0xff000000,
 181         PRSSTAT_CLSL    = 0x00800000,
 182         PRSSTAT_WPSPL   = 0x00080000,
 183         PRSSTAT_CDPL    = 0x00040000,
 184         PRSSTAT_CINS    = 0x00010000,
 185         PRSSTAT_BREN    = 0x00000800,
 186         PRSSTAT_BWEN    = 0x00000400,
 187         PRSSTAT_RTA     = 0x00000200,
 188         PRSSTAT_WTA     = 0x00000100,
 189         PRSSTAT_SDOFF   = 0x00000080,
 190         PRSSTAT_PEROFF  = 0x00000040,
 191         PRSSTAT_HCKOFF  = 0x00000020,
 192         PRSSTAT_IPGOFF  = 0x00000010,
 193         PRSSTAT_DLA     = 0x00000004,
 194         PRSSTAT_CDIHB   = 0x00000002,
 195         PRSSTAT_CIHB    = 0x00000001
 196
 197 };
 198
 199 enum irq_bits {
 200         IRQ_DMAE        = 0x10000000,
 201         IRQ_AC12E       = 0x01000000,
 202         IRQ_DEBE        = 0x00400000,
 203         IRQ_DCE         = 0x00200000,
 204         IRQ_DTOE        = 0x00100000,
 205         IRQ_CIE         = 0x00080000,
 206         IRQ_CEBE        = 0x00040000,
 207         IRQ_CCE         = 0x00020000,
 208         IRQ_CTOE        = 0x00010000,
 209         IRQ_CINT        = 0x00000100,
 210         IRQ_CRM         = 0x00000080,
 211         IRQ_CINS        = 0x00000040,
 212         IRQ_BRR         = 0x00000020,
 213         IRQ_BWR         = 0x00000010,
 214         IRQ_DINT        = 0x00000008,
 215         IRQ_BGE         = 0x00000004,
 216         IRQ_TC          = 0x00000002,
 217         IRQ_CC          = 0x00000001
 218 };
 219
 220 enum irq_masks {
 221         IRQ_ERROR_DATA_MASK     = IRQ_DMAE | IRQ_DEBE | IRQ_DCE | IRQ_DTOE,
 222         IRQ_ERROR_CMD_MASK      = IRQ_AC12E | IRQ_CIE | IRQ_CTOE | IRQ_CCE |
 223                                   IRQ_CEBE
 224 };
 225
 226 enum dcr_bits {
 227         DCR_PRI                 = 0x0000c000,
 228         DCR_SNOOP               = 0x00000040,
 229         DCR_AHB2MAG_BYPASS      = 0x00000020,
 230         DCR_RD_SAFE             = 0x00000004,
 231         DCR_RD_PFE              = 0x00000002,
 232         DCR_RD_PF_SIZE          = 0x00000001
 233 };
 234
 235 #define DCR_PRI_SHIFT   (14)
 236
 237 enum xfertyp_bits {
 238         XFERTYP_CMDINX  = 0x3f000000,
 239         XFERTYP_CMDTYP  = 0x00c00000,
 240         XFERTYP_DPSEL   = 0x00200000,
 241         XFERTYP_CICEN   = 0x00100000,
 242         XFERTYP_CCCEN   = 0x00080000,
 243         XFERTYP_RSPTYP  = 0x00030000,
 244         XFERTYP_MSBSEL  = 0x00000020,
 245         XFERTYP_DTDSEL  = 0x00000010,
 246         XFERTYP_AC12EN  = 0x00000004,
 247         XFERTYP_BCEN    = 0x00000002,
 248         XFERTYP_DMAEN   = 0x00000001
 249 };
 250
 251 #define CMDINX_SHIFT    (24)
 252
 253 enum xfertyp_cmdtyp {
 254         CMDTYP_NORMAL   = 0x00000000,
 255         CMDYTP_SUSPEND  = 0x00400000,
 256         CMDTYP_RESUME   = 0x00800000,
 257         CMDTYP_ABORT    = 0x00c00000
 258 };
 259
 260 enum xfertyp_rsptyp {
 261         RSPTYP_NONE     = 0x00000000,
 262         RSPTYP_136      = 0x00010000,
 263         RSPTYP_48       = 0x00020000,
 264         RSPTYP_48_BUSY  = 0x00030000
 265 };
 266
 267 enum blkattr_bits {
 268         BLKATTR_BLKSZE  = 0x00001fff,
 269         BLKATTR_BLKCNT  = 0xffff0000
 270 };
 271 #define BLKATTR_BLOCK_COUNT(x)  (x << 16)
 272
 273 enum wml_bits {
 274         WR_WML  = 0x00ff0000,
 275         RD_WML  = 0x000000ff,
 276 };
 277
 278 enum sdhc_bit_mask {
 279         MASK_CLOCK_CONTROL      = 0x0000ffff,
 280         MASK_IRQ_ALL            = IRQ_DMAE | IRQ_AC12E | IRQ_DEBE | IRQ_DCE |
 281                                   IRQ_DTOE | IRQ_CIE | IRQ_CEBE | IRQ_CCE |
 282                                   IRQ_CTOE | IRQ_CINT | IRQ_CRM | IRQ_CINS |
 283                                   IRQ_BRR | IRQ_BWR | IRQ_DINT | IRQ_BGE |
 284                                   IRQ_TC | IRQ_CC,
 285 };
 286
 287 enum sdhc_line {
 288         SDHC_DAT_LINE   = 0x2,
 289         SDHC_CMD_LINE   = 0x1
 290 };
 291
 292 #endif /* FSL_SDHC_H_ */