2 * Copyright (C) 2008-2010 Nathan Whitehorn
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
34 #include <sys/kernel.h>
36 #include <dev/ofw/openfirm.h>
37 #include <dev/ofw/ofw_pci.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
42 #include <machine/bus.h>
43 #include <machine/intr_machdep.h>
44 #include <machine/md_var.h>
45 #include <machine/openpicvar.h>
46 #include <machine/pio.h>
47 #include <machine/resource.h>
51 #include <dev/ofw/ofw_bus.h>
52 #include <dev/ofw/ofw_bus_subr.h>
61 * IBM CPC9X5 Hypertransport Device interface.
63 static int cpcht_probe(device_t);
64 static int cpcht_attach(device_t);
66 static void cpcht_configure_htbridge(device_t, phandle_t);
71 static int cpcht_read_ivar(device_t, device_t, int,
73 static struct resource *cpcht_alloc_resource(device_t bus, device_t child,
74 int type, int *rid, u_long start, u_long end,
75 u_long count, u_int flags);
76 static int cpcht_activate_resource(device_t bus, device_t child,
77 int type, int rid, struct resource *res);
78 static int cpcht_release_resource(device_t bus, device_t child,
79 int type, int rid, struct resource *res);
80 static int cpcht_deactivate_resource(device_t bus, device_t child,
81 int type, int rid, struct resource *res);
86 static int cpcht_maxslots(device_t);
87 static u_int32_t cpcht_read_config(device_t, u_int, u_int, u_int,
89 static void cpcht_write_config(device_t, u_int, u_int, u_int,
90 u_int, u_int32_t, int);
91 static int cpcht_route_interrupt(device_t bus, device_t dev,
98 static phandle_t cpcht_get_node(device_t bus, device_t child);
103 static device_method_t cpcht_methods[] = {
104 /* Device interface */
105 DEVMETHOD(device_probe, cpcht_probe),
106 DEVMETHOD(device_attach, cpcht_attach),
109 DEVMETHOD(bus_read_ivar, cpcht_read_ivar),
110 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
111 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
112 DEVMETHOD(bus_alloc_resource, cpcht_alloc_resource),
113 DEVMETHOD(bus_release_resource, cpcht_release_resource),
114 DEVMETHOD(bus_activate_resource, cpcht_activate_resource),
115 DEVMETHOD(bus_deactivate_resource, cpcht_deactivate_resource),
118 DEVMETHOD(pcib_maxslots, cpcht_maxslots),
119 DEVMETHOD(pcib_read_config, cpcht_read_config),
120 DEVMETHOD(pcib_write_config, cpcht_write_config),
121 DEVMETHOD(pcib_route_interrupt, cpcht_route_interrupt),
123 /* ofw_bus interface */
124 DEVMETHOD(ofw_bus_get_node, cpcht_get_node),
133 vm_offset_t apple_eoi;
138 static struct cpcht_irq *cpcht_irqmap = NULL;
144 uint64_t sc_populated_slots;
145 struct rman sc_mem_rman;
146 struct rman sc_io_rman;
148 struct cpcht_irq htirq_map[128];
151 static driver_t cpcht_driver = {
154 sizeof(struct cpcht_softc)
157 static devclass_t cpcht_devclass;
159 DRIVER_MODULE(cpcht, nexus, cpcht_driver, cpcht_devclass, 0, 0);
161 #define CPCHT_IOPORT_BASE 0xf4000000UL /* Hardwired */
162 #define CPCHT_IOPORT_SIZE 0x00400000UL
164 #define HTAPIC_REQUEST_EOI 0x20
165 #define HTAPIC_TRIGGER_LEVEL 0x02
166 #define HTAPIC_MASK 0x01
180 cpcht_probe(device_t dev)
182 const char *type, *compatible;
184 type = ofw_bus_get_type(dev);
185 compatible = ofw_bus_get_compat(dev);
187 if (type == NULL || compatible == NULL)
190 if (strcmp(type, "ht") != 0)
193 if (strcmp(compatible, "u3-ht") != 0)
197 device_set_desc(dev, "IBM CPC9X5 HyperTransport Tunnel");
202 cpcht_attach(device_t dev)
204 struct cpcht_softc *sc;
205 phandle_t node, child;
209 node = ofw_bus_get_node(dev);
210 sc = device_get_softc(dev);
212 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 12)
217 sc->sc_populated_slots = 0;
218 sc->sc_data = (vm_offset_t)pmap_mapdev(reg[1], reg[2]);
220 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
221 sc->sc_mem_rman.rm_descr = "CPCHT Device Memory";
222 error = rman_init(&sc->sc_mem_rman);
224 device_printf(dev, "rman_init() failed. error = %d\n", error);
228 sc->sc_io_rman.rm_type = RMAN_ARRAY;
229 sc->sc_io_rman.rm_descr = "CPCHT I/O Memory";
230 error = rman_init(&sc->sc_io_rman);
232 device_printf(dev, "rman_init() failed. error = %d\n", error);
237 * Set up the resource manager and the HT->MPIC mapping. For cpcht,
238 * the ranges are properties of the child bridges, and this is also
239 * where we get the HT interrupts properties.
242 /* I/O port mappings are usually not in the device tree */
243 rman_manage_region(&sc->sc_io_rman, 0, CPCHT_IOPORT_SIZE - 1);
245 bzero(sc->htirq_map, sizeof(sc->htirq_map));
246 for (child = OF_child(node); child != 0; child = OF_peer(child))
247 cpcht_configure_htbridge(dev, child);
249 /* Now make the mapping table available to the MPIC */
250 cpcht_irqmap = sc->htirq_map;
252 device_add_child(dev, "pci", device_get_unit(dev));
254 return (bus_generic_attach(dev));
258 cpcht_configure_htbridge(device_t dev, phandle_t child)
260 struct cpcht_softc *sc;
261 struct ofw_pci_register pcir;
262 struct cpcht_range ranges[6], *rp;
263 int nranges, ptr, nextptr;
268 sc = device_get_softc(dev);
269 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
272 s = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
273 f = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
276 * Mark this slot is populated. The remote south bridge does
277 * not like us talking to unpopulated slots on the root bus.
279 sc->sc_populated_slots |= (1 << s);
282 * Next grab this child bus's bus ranges.
284 bzero(ranges, sizeof(ranges));
285 nranges = OF_getprop(child, "ranges", ranges, sizeof(ranges));
287 ranges[6].pci_hi = 0;
288 for (rp = ranges; rp->pci_hi != 0; rp++) {
289 switch (rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) {
290 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
292 case OFW_PCI_PHYS_HI_SPACE_IO:
293 rman_manage_region(&sc->sc_io_rman, rp->pci_lo,
294 rp->pci_lo + rp->size_lo - 1);
296 case OFW_PCI_PHYS_HI_SPACE_MEM32:
297 rman_manage_region(&sc->sc_mem_rman, rp->pci_lo,
298 rp->pci_lo + rp->size_lo - 1);
300 case OFW_PCI_PHYS_HI_SPACE_MEM64:
301 panic("64-bit CPCHT reserved memory!");
307 * Next build up any HT->MPIC mappings for this sub-bus. One would
308 * naively hope that enabling, disabling, and EOIing interrupts would
309 * cause the appropriate HT bus transactions to that effect. This is
312 * Instead, we have to muck about on the HT peer's root PCI bridges,
313 * figure out what interrupts they send, enable them, and cache
314 * the location of their WaitForEOI registers so that we can
318 /* All the devices we are interested in have caps */
319 if (!(PCIB_READ_CONFIG(dev, 0, s, f, PCIR_STATUS, 2)
320 & PCIM_STATUS_CAPPRESENT))
323 nextptr = PCIB_READ_CONFIG(dev, 0, s, f, PCIR_CAP_PTR, 1);
324 while (nextptr != 0) {
326 nextptr = PCIB_READ_CONFIG(dev, 0, s, f,
327 ptr + PCICAP_NEXTPTR, 1);
329 /* Find the HT IRQ capabilities */
330 if (PCIB_READ_CONFIG(dev, 0, s, f,
331 ptr + PCICAP_ID, 1) != PCIY_HT)
334 val = PCIB_READ_CONFIG(dev, 0, s, f, ptr + PCIR_HT_COMMAND, 2);
335 if ((val & PCIM_HTCMD_CAP_MASK) != PCIM_HTCAP_INTERRUPT)
338 /* Ask for the IRQ count */
339 PCIB_WRITE_CONFIG(dev, 0, s, f, ptr + PCIR_HT_COMMAND, 0x1, 1);
340 nirq = PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4);
341 nirq = ((nirq >> 16) & 0xff) + 1;
343 device_printf(dev, "%d HT IRQs on device %d.%d\n", nirq, s, f);
345 for (i = 0; i < nirq; i++) {
346 PCIB_WRITE_CONFIG(dev, 0, s, f,
347 ptr + PCIR_HT_COMMAND, 0x10 + (i << 1), 1);
348 irq = PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4);
351 * Mask this interrupt for now.
353 PCIB_WRITE_CONFIG(dev, 0, s, f, ptr + 4,
354 irq | HTAPIC_MASK, 4);
355 irq = (irq >> 16) & 0xff;
357 sc->htirq_map[irq].ht_source = i;
358 sc->htirq_map[irq].ht_base = sc->sc_data +
359 (((((s & 0x1f) << 3) | (f & 0x07)) << 8) | (ptr));
361 PCIB_WRITE_CONFIG(dev, 0, s, f,
362 ptr + PCIR_HT_COMMAND, 0x11 + (i << 1), 1);
363 sc->htirq_map[irq].eoi_data =
364 PCIB_READ_CONFIG(dev, 0, s, f, ptr + 4, 4) |
368 * Apple uses a non-compliant IO/APIC that differs
369 * in how we signal EOIs. Check if this device was
370 * made by Apple, and act accordingly.
372 vend = PCIB_READ_CONFIG(dev, 0, s, f,
374 if ((vend & 0xffff) == 0x106b)
375 sc->htirq_map[irq].apple_eoi =
376 (sc->htirq_map[irq].ht_base - ptr) + 0x60;
382 cpcht_maxslots(device_t dev)
385 return (PCI_SLOTMAX);
389 cpcht_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
392 struct cpcht_softc *sc;
395 sc = device_get_softc(dev);
396 caoff = sc->sc_data +
397 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);
399 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0))
403 caoff += 0x01000000UL + (bus << 16);
407 return (in8rb(caoff));
410 return (in16rb(caoff));
413 return (in32rb(caoff));
421 cpcht_write_config(device_t dev, u_int bus, u_int slot, u_int func,
422 u_int reg, u_int32_t val, int width)
424 struct cpcht_softc *sc;
427 sc = device_get_softc(dev);
428 caoff = sc->sc_data +
429 (((((slot & 0x1f) << 3) | (func & 0x07)) << 8) | reg);
431 if (bus == 0 && (!(sc->sc_populated_slots & (1 << slot)) || func > 0))
435 caoff += 0x01000000UL + (bus << 16);
451 cpcht_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
453 struct cpcht_softc *sc;
455 sc = device_get_softc(dev);
458 case PCIB_IVAR_DOMAIN:
459 *result = device_get_unit(dev);
462 *result = 0; /* Root bus */
470 cpcht_get_node(device_t bus, device_t dev)
472 struct cpcht_softc *sc;
474 sc = device_get_softc(bus);
475 /* We only have one child, the PCI bus, which needs our own node. */
476 return (sc->sc_node);
480 cpcht_route_interrupt(device_t bus, device_t dev, int pin)
485 static struct resource *
486 cpcht_alloc_resource(device_t bus, device_t child, int type, int *rid,
487 u_long start, u_long end, u_long count, u_int flags)
489 struct cpcht_softc *sc;
492 int needactivate, err;
494 needactivate = flags & RF_ACTIVE;
497 sc = device_get_softc(bus);
502 end = min(end, start + count);
503 rm = &sc->sc_io_rman;
507 rm = &sc->sc_mem_rman;
511 return (bus_alloc_resource(bus, type, rid, start, end, count,
515 device_printf(bus, "unknown resource request from %s\n",
516 device_get_nameunit(child));
520 rv = rman_reserve_resource(rm, start, end, count, flags, child);
522 device_printf(bus, "failed to reserve resource for %s\n",
523 device_get_nameunit(child));
527 rman_set_rid(rv, *rid);
530 if (bus_activate_resource(child, type, *rid, rv) != 0) {
532 "failed to activate resource for %s\n",
533 device_get_nameunit(child));
534 rman_release_resource(rv);
543 cpcht_activate_resource(device_t bus, device_t child, int type, int rid,
544 struct resource *res)
547 struct cpcht_softc *sc;
549 sc = device_get_softc(bus);
551 if (type == SYS_RES_IRQ)
552 return (bus_activate_resource(bus, type, rid, res));
554 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
557 start = (vm_offset_t)rman_get_start(res);
559 if (type == SYS_RES_IOPORT)
560 start += CPCHT_IOPORT_BASE;
563 printf("cpcht mapdev: start %zx, len %ld\n", start,
566 p = pmap_mapdev(start, (vm_size_t)rman_get_size(res));
569 rman_set_virtual(res, p);
570 rman_set_bustag(res, &bs_le_tag);
571 rman_set_bushandle(res, (u_long)p);
574 return (rman_activate_resource(res));
578 cpcht_release_resource(device_t bus, device_t child, int type, int rid,
579 struct resource *res)
582 if (rman_get_flags(res) & RF_ACTIVE) {
583 int error = bus_deactivate_resource(child, type, rid, res);
588 return (rman_release_resource(res));
592 cpcht_deactivate_resource(device_t bus, device_t child, int type, int rid,
593 struct resource *res)
597 * If this is a memory resource, unmap it.
599 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
602 psize = rman_get_size(res);
603 pmap_unmapdev((vm_offset_t)rman_get_virtual(res), psize);
606 return (rman_deactivate_resource(res));
610 * Driver for the integrated MPIC on U3/U4 (CPC925/CPC945)
613 static int openpic_cpcht_probe(device_t);
614 static int openpic_cpcht_attach(device_t);
615 static void openpic_cpcht_config(device_t, u_int irq,
616 enum intr_trigger trig, enum intr_polarity pol);
617 static void openpic_cpcht_enable(device_t, u_int irq, u_int vector);
618 static void openpic_cpcht_unmask(device_t, u_int irq);
619 static void openpic_cpcht_eoi(device_t, u_int irq);
621 static device_method_t openpic_cpcht_methods[] = {
622 /* Device interface */
623 DEVMETHOD(device_probe, openpic_cpcht_probe),
624 DEVMETHOD(device_attach, openpic_cpcht_attach),
627 DEVMETHOD(pic_config, openpic_cpcht_config),
628 DEVMETHOD(pic_dispatch, openpic_dispatch),
629 DEVMETHOD(pic_enable, openpic_cpcht_enable),
630 DEVMETHOD(pic_eoi, openpic_cpcht_eoi),
631 DEVMETHOD(pic_ipi, openpic_ipi),
632 DEVMETHOD(pic_mask, openpic_mask),
633 DEVMETHOD(pic_unmask, openpic_cpcht_unmask),
638 struct openpic_cpcht_softc {
639 struct openpic_softc sc_openpic;
641 struct mtx sc_ht_mtx;
644 static driver_t openpic_cpcht_driver = {
646 openpic_cpcht_methods,
647 sizeof(struct openpic_cpcht_softc),
650 DRIVER_MODULE(openpic, unin, openpic_cpcht_driver, openpic_devclass, 0, 0);
653 openpic_cpcht_probe(device_t dev)
655 const char *type = ofw_bus_get_type(dev);
657 if (strcmp(type, "open-pic") != 0)
660 device_set_desc(dev, OPENPIC_DEVSTR);
665 openpic_cpcht_attach(device_t dev)
667 struct openpic_cpcht_softc *sc;
670 err = openpic_attach(dev);
675 * The HT APIC stuff is not thread-safe, so we need a mutex to
678 sc = device_get_softc(dev);
679 mtx_init(&sc->sc_ht_mtx, "htpic", NULL, MTX_SPIN);
682 * Interrupts 0-3 are internally sourced and are level triggered
683 * active low. Interrupts 4-123 are connected to a pulse generator
684 * and should be programmed as edge triggered low-to-high.
686 * IBM CPC945 Manual, Section 9.3.
689 for (irq = 0; irq < 4; irq++)
690 openpic_config(dev, irq, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
691 for (irq = 4; irq < 124; irq++)
692 openpic_config(dev, irq, INTR_TRIGGER_EDGE, INTR_POLARITY_LOW);
698 openpic_cpcht_config(device_t dev, u_int irq, enum intr_trigger trig,
699 enum intr_polarity pol)
701 struct openpic_cpcht_softc *sc;
705 * The interrupt settings for the MPIC are completely determined
706 * by the internal wiring in the northbridge. Real changes to these
707 * settings need to be negotiated with the remote IO-APIC on the HT
711 sc = device_get_softc(dev);
713 if (cpcht_irqmap != NULL && irq < 128 &&
714 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) {
715 mtx_lock_spin(&sc->sc_ht_mtx);
717 /* Program the data port */
718 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
719 0x10 + (cpcht_irqmap[irq].ht_source << 1));
721 /* Grab the IRQ config register */
722 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
724 /* Mask the IRQ while we fiddle settings */
725 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq | HTAPIC_MASK);
727 /* Program the interrupt sense */
728 ht_irq &= ~(HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI);
729 if (trig == INTR_TRIGGER_EDGE) {
730 cpcht_irqmap[irq].edge = 1;
732 cpcht_irqmap[irq].edge = 0;
733 ht_irq |= HTAPIC_TRIGGER_LEVEL | HTAPIC_REQUEST_EOI;
735 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
737 mtx_unlock_spin(&sc->sc_ht_mtx);
742 openpic_cpcht_enable(device_t dev, u_int irq, u_int vec)
744 struct openpic_cpcht_softc *sc;
747 openpic_enable(dev, irq, vec);
749 sc = device_get_softc(dev);
751 if (cpcht_irqmap != NULL && irq < 128 &&
752 cpcht_irqmap[irq].ht_base > 0) {
753 mtx_lock_spin(&sc->sc_ht_mtx);
755 /* Program the data port */
756 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
757 0x10 + (cpcht_irqmap[irq].ht_source << 1));
759 /* Unmask the interrupt */
760 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
761 ht_irq &= ~HTAPIC_MASK;
762 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
764 mtx_unlock_spin(&sc->sc_ht_mtx);
767 openpic_cpcht_eoi(dev, irq);
771 openpic_cpcht_unmask(device_t dev, u_int irq)
773 struct openpic_cpcht_softc *sc;
776 openpic_unmask(dev, irq);
778 sc = device_get_softc(dev);
780 if (cpcht_irqmap != NULL && irq < 128 &&
781 cpcht_irqmap[irq].ht_base > 0) {
782 mtx_lock_spin(&sc->sc_ht_mtx);
784 /* Program the data port */
785 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
786 0x10 + (cpcht_irqmap[irq].ht_source << 1));
788 /* Unmask the interrupt */
789 ht_irq = in32rb(cpcht_irqmap[irq].ht_base + 4);
790 ht_irq &= ~HTAPIC_MASK;
791 out32rb(cpcht_irqmap[irq].ht_base + 4, ht_irq);
793 mtx_unlock_spin(&sc->sc_ht_mtx);
796 openpic_cpcht_eoi(dev, irq);
800 openpic_cpcht_eoi(device_t dev, u_int irq)
802 struct openpic_cpcht_softc *sc;
808 sc = device_get_softc(dev);
810 if (cpcht_irqmap != NULL && irq < 128 &&
811 cpcht_irqmap[irq].ht_base > 0 && !cpcht_irqmap[irq].edge) {
812 /* If this is an HT IRQ, acknowledge it at the remote APIC */
814 if (cpcht_irqmap[irq].apple_eoi) {
815 off = (cpcht_irqmap[irq].ht_source >> 3) & ~3;
816 mask = 1 << (cpcht_irqmap[irq].ht_source & 0x1f);
817 out32rb(cpcht_irqmap[irq].apple_eoi + off, mask);
819 mtx_lock_spin(&sc->sc_ht_mtx);
821 out8rb(cpcht_irqmap[irq].ht_base + PCIR_HT_COMMAND,
822 0x11 + (cpcht_irqmap[irq].ht_source << 1));
823 out32rb(cpcht_irqmap[irq].ht_base + 4,
824 cpcht_irqmap[irq].eoi_data);
826 mtx_unlock_spin(&sc->sc_ht_mtx);
830 openpic_eoi(dev, irq);