2 * Copyright (c) 2008 Nathan Whitehorn
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6 * modification, are permitted provided that the following conditions
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29 #ifndef _POWERPC_POWERMAC_DBDMAVAR_H_
30 #define _POWERPC_POWERMAC_DBDMAVAR_H_
32 struct dbdma_command {
33 uint8_t cmd:4; /* DBDMA command */
36 uint8_t key:3; /* Stream number, or 6 for KEY_SYSTEM */
39 /* Interrupt, branch, and wait flags */
44 uint16_t reqCount; /* Bytes to transfer */
46 uint32_t address; /* 32-bit system physical address */
47 uint32_t cmdDep; /* Branch address or quad word to load/store */
49 uint16_t xferStatus; /* Contents of channel status after completion */
50 uint16_t resCount; /* Number of residual bytes outstanding */
53 struct dbdma_channel {
54 struct resource *sc_regs;
57 struct dbdma_command *sc_slots;
59 bus_addr_t sc_slots_pa;
61 bus_dma_tag_t sc_dmatag;
62 bus_dmamap_t sc_dmamap;
67 DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
68 and are laid out as follows within each block:
70 Address: Description: Length (bytes):
71 0x000 Channel Control 4
72 0x004 Channel Status 4
73 0x00C Command Phys Addr 4
74 0x010 Interrupt Select 4
79 #define CHAN_CONTROL_REG 0x00
80 #define CHAN_STATUS_REG 0x04
81 #define CHAN_CMDPTR_HI 0x08
82 #define CHAN_CMDPTR 0x0C
83 #define CHAN_INTR_SELECT 0x10
84 #define CHAN_BRANCH_SELECT 0x14
85 #define CHAN_WAIT_SELECT 0x18
87 /* Channel control is the write channel to channel status, the upper 16 bits
88 are a mask of which bytes to change */
90 #define DBDMA_REG_MASK_SHIFT 16
92 /* Status bits 0-7 are device dependent status bits */
95 The Interrupt/Branch/Wait Select triggers the corresponding condition bits
96 in the event that (select.mask & device dependent status) == select.value
98 They are defined a follows:
105 #endif /* _POWERPC_POWERMAC_DBDMAVAR_H_ */