2 * Copyright (c) 2001 Tsubai Masanari. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * NetBSD: ki2c.c,v 1.11 2007/12/06 17:00:33 ad Exp
28 * Id: ki2c.c,v 1.7 2002/10/05 09:56:05 tsubai Exp
32 * Support routines for the Keywest I2C controller.
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
42 #include <machine/resource.h>
43 #include <machine/bus.h>
46 #include <dev/iicbus/iicbus.h>
47 #include <dev/iicbus/iiconf.h>
48 #include <dev/ofw/ofw_bus.h>
49 #include "iicbus_if.h"
51 /* Keywest I2C Register offsets */
63 #define I2C_SPEED 0x03 /* Speed mask */
64 #define I2C_100kHz 0x00
65 #define I2C_50kHz 0x01
66 #define I2C_25kHz 0x02
67 #define I2C_MODE 0x0c /* Mode mask */
68 #define I2C_DUMBMODE 0x00 /* Dumb mode */
69 #define I2C_STDMODE 0x04 /* Standard mode */
70 #define I2C_STDSUBMODE 0x08 /* Standard mode + sub address */
71 #define I2C_COMBMODE 0x0c /* Combined mode */
72 #define I2C_PORT 0xf0 /* Port mask */
75 #define I2C_CT_AAK 0x01 /* Send AAK */
76 #define I2C_CT_ADDR 0x02 /* Send address(es) */
77 #define I2C_CT_STOP 0x04 /* Send STOP */
78 #define I2C_CT_START 0x08 /* Send START */
81 #define I2C_ST_BUSY 0x01 /* Busy */
82 #define I2C_ST_LASTAAK 0x02 /* Last AAK */
83 #define I2C_ST_LASTRW 0x04 /* Last R/W */
84 #define I2C_ST_SDA 0x08 /* SDA */
85 #define I2C_ST_SCL 0x10 /* SCL */
88 #define I2C_INT_DATA 0x01 /* Data byte sent/received */
89 #define I2C_INT_ADDR 0x02 /* Address sent */
90 #define I2C_INT_STOP 0x04 /* STOP condition sent */
91 #define I2C_INT_START 0x08 /* START condition sent */
95 #define I2C_READING 0x02
96 #define I2C_ERROR 0x04
97 #define I2C_SELECTED 0x08
103 struct resource *sc_reg;
105 struct resource *sc_irq;
111 uint16_t sc_i2c_base;
115 static int kiic_probe(device_t dev);
116 static int kiic_attach(device_t dev);
117 static void kiic_writereg(struct kiic_softc *sc, u_int, u_int);
118 static u_int kiic_readreg(struct kiic_softc *, u_int);
119 static void kiic_setport(struct kiic_softc *, u_int);
120 static void kiic_setmode(struct kiic_softc *, u_int);
121 static void kiic_setspeed(struct kiic_softc *, u_int);
122 static void kiic_intr(void *xsc);
123 static int kiic_transfer(device_t dev, struct iic_msg *msgs,
125 static phandle_t kiic_get_node(device_t bus, device_t dev);
127 static device_method_t kiic_methods[] = {
128 /* device interface */
129 DEVMETHOD(device_probe, kiic_probe),
130 DEVMETHOD(device_attach, kiic_attach),
132 /* iicbus interface */
133 DEVMETHOD(iicbus_callback, iicbus_null_callback),
134 DEVMETHOD(iicbus_transfer, kiic_transfer),
136 /* ofw_bus interface */
137 DEVMETHOD(ofw_bus_get_node, kiic_get_node),
142 static driver_t kiic_driver = {
145 sizeof(struct kiic_softc)
147 static devclass_t kiic_devclass;
149 DRIVER_MODULE(kiic, macio, kiic_driver, kiic_devclass, 0, 0);
150 DRIVER_MODULE(kiic, unin, kiic_driver, kiic_devclass, 0, 0);
153 kiic_probe(device_t self)
157 name = ofw_bus_get_name(self);
158 if (name && strcmp(name, "i2c") == 0) {
159 device_set_desc(self, "Keywest I2C controller");
167 kiic_attach(device_t self)
169 struct kiic_softc *sc = device_get_softc(self);
174 bzero(sc, sizeof(*sc));
177 node = ofw_bus_get_node(self);
178 if (node == 0 || node == -1) {
183 sc->sc_reg = bus_alloc_resource_any(self, SYS_RES_MEMORY,
185 if (sc->sc_reg == NULL) {
189 if (OF_getprop(node, "AAPL,i2c-rate", &rate, 4) != 4) {
190 device_printf(self, "cannot get i2c-rate\n");
193 if (OF_getprop(node, "AAPL,address-step", &sc->sc_regstep, 4) != 4) {
194 device_printf(self, "unable to find i2c address step\n");
199 * Some Keywest I2C devices have their children attached directly
200 * underneath them. Some have a single 'iicbus' child with the
201 * devices underneath that. Sort this out, and make sure that the
202 * OFW I2C layer has the correct node.
204 * Note: the I2C children of the Uninorth bridges have two ports.
205 * In general, the port is designated in the 9th bit of the I2C
206 * address. However, for kiic devices with children attached below
207 * an i2c-bus node, the port is indicated in the 'reg' property
208 * of the i2c-bus node.
213 node = OF_child(node);
214 if (OF_getprop(node, "name", name, sizeof(name)) > 0) {
215 if (strcmp(name,"i2c-bus") == 0) {
217 if (OF_getprop(node, "reg", ®, sizeof(reg)) > 0)
218 sc->sc_i2c_base = reg << 8;
224 mtx_init(&sc->sc_mutex, "kiic", NULL, MTX_DEF);
226 sc->sc_irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &sc->sc_irqrid,
228 bus_setup_intr(self, sc->sc_irq, INTR_TYPE_MISC | INTR_MPSAFE, NULL,
229 kiic_intr, sc, &sc->sc_ih);
231 kiic_writereg(sc, ISR, kiic_readreg(sc, ISR));
232 kiic_writereg(sc, STATUS, 0);
233 kiic_writereg(sc, IER, 0);
235 kiic_setmode(sc, I2C_STDMODE);
236 kiic_setspeed(sc, I2C_100kHz); /* XXX rate */
238 kiic_writereg(sc, IER, I2C_INT_DATA | I2C_INT_ADDR | I2C_INT_STOP);
241 device_printf(self, "Revision: %02X\n", kiic_readreg(sc, REV));
243 /* Add the IIC bus layer */
244 sc->sc_iicbus = device_add_child(self, "iicbus", -1);
246 return (bus_generic_attach(self));
250 kiic_writereg(struct kiic_softc *sc, u_int reg, u_int val)
252 bus_write_4(sc->sc_reg, sc->sc_regstep * reg, val);
253 DELAY(100); /* register access delay */
257 kiic_readreg(struct kiic_softc *sc, u_int reg)
259 return bus_read_4(sc->sc_reg, sc->sc_regstep * reg) & 0xff;
263 kiic_setmode(struct kiic_softc *sc, u_int mode)
267 KASSERT((mode & ~I2C_MODE) == 0, ("bad mode"));
268 x = kiic_readreg(sc, MODE);
271 kiic_writereg(sc, MODE, x);
275 kiic_setport(struct kiic_softc *sc, u_int port)
279 KASSERT(port == 1 || port == 0, ("bad port"));
280 x = kiic_readreg(sc, MODE);
283 kiic_writereg(sc, MODE, x);
287 kiic_setspeed(struct kiic_softc *sc, u_int speed)
291 KASSERT((speed & ~I2C_SPEED) == 0, ("bad speed"));
292 x = kiic_readreg(sc, MODE);
295 kiic_writereg(sc, MODE, x);
301 struct kiic_softc *sc = xsc;
305 mtx_lock(&sc->sc_mutex);
306 isr = kiic_readreg(sc, ISR);
308 if (isr & I2C_INT_ADDR) {
309 sc->sc_flags |= I2C_SELECTED;
311 if (sc->sc_flags & I2C_READING) {
312 if (sc->sc_resid > 1) {
313 x = kiic_readreg(sc, CONTROL);
315 kiic_writereg(sc, CONTROL, x);
318 kiic_writereg(sc, DATA, *sc->sc_data++);
323 if (isr & I2C_INT_DATA) {
324 if (sc->sc_flags & I2C_READING) {
325 if (sc->sc_resid > 0) {
326 *sc->sc_data++ = kiic_readreg(sc, DATA);
329 if (sc->sc_resid == 0) /* done */
330 kiic_writereg(sc, CONTROL, 0);
332 if (sc->sc_resid == 0) {
333 x = kiic_readreg(sc, CONTROL);
335 kiic_writereg(sc, CONTROL, x);
337 kiic_writereg(sc, DATA, *sc->sc_data++);
343 if (isr & I2C_INT_STOP) {
344 kiic_writereg(sc, CONTROL, 0);
345 sc->sc_flags &= ~I2C_SELECTED;
349 kiic_writereg(sc, ISR, isr);
350 mtx_unlock(&sc->sc_mutex);
354 kiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
356 struct kiic_softc *sc;
361 sc = device_get_softc(dev);
365 mtx_lock(&sc->sc_mutex);
367 if (sc->sc_flags & I2C_BUSY)
368 mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo);
370 if (sc->sc_flags & I2C_BUSY) {
371 mtx_unlock(&sc->sc_mutex);
375 sc->sc_flags = I2C_BUSY;
377 /* Clear pending interrupts, and reset controller */
378 kiic_writereg(sc, ISR, kiic_readreg(sc, ISR));
379 kiic_writereg(sc, STATUS, 0);
381 for (i = 0; i < nmsgs; i++) {
382 if (msgs[i].flags & IIC_M_NOSTOP) {
383 if (msgs[i+1].flags & IIC_M_RD)
384 kiic_setmode(sc, I2C_COMBMODE);
386 kiic_setmode(sc, I2C_STDSUBMODE);
387 KASSERT(msgs[i].len == 1, ("oversize I2C message"));
388 subaddr = msgs[i].buf[0];
391 kiic_setmode(sc, I2C_STDMODE);
394 sc->sc_data = msgs[i].buf;
395 sc->sc_resid = msgs[i].len;
396 sc->sc_flags = I2C_BUSY;
397 addr = msgs[i].slave;
398 timo = 1000 + sc->sc_resid * 200;
401 if (msgs[i].flags & IIC_M_RD) {
402 sc->sc_flags |= I2C_READING;
406 addr |= sc->sc_i2c_base;
408 kiic_setport(sc, (addr & 0x100) >> 8);
409 kiic_writereg(sc, ADDR, addr & 0xff);
410 kiic_writereg(sc, SUBADDR, subaddr);
412 x = kiic_readreg(sc, CONTROL) | I2C_CT_ADDR;
413 kiic_writereg(sc, CONTROL, x);
415 err = mtx_sleep(dev, &sc->sc_mutex, 0, "kiic", timo);
417 msgs[i].len -= sc->sc_resid;
419 if ((sc->sc_flags & I2C_ERROR) || err == EWOULDBLOCK) {
420 device_printf(sc->sc_dev, "I2C error\n");
422 mtx_unlock(&sc->sc_mutex);
429 mtx_unlock(&sc->sc_mutex);
435 kiic_get_node(device_t bus, device_t dev)
437 struct kiic_softc *sc;
439 sc = device_get_softc(bus);
440 /* We only have one child, the I2C bus, which needs our own node. */