2 * Copyright (c) 2001 Jake Burkholder.
3 * Copyright (c) 2007 - 2011 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_SMP_H_
31 #define _MACHINE_SMP_H_
35 #define CPU_TICKSYNC 1
36 #define CPU_STICKSYNC 2
38 #define CPU_BOOTSTRAP 4
42 #include <sys/param.h>
43 #include <sys/cpuset.h>
45 #include <sys/mutex.h>
47 #include <sys/sched.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/tte.h>
53 #define IDR_BUSY 0x0000000000000001ULL
54 #define IDR_NACK 0x0000000000000002ULL
55 #define IDR_CHEETAH_ALL_BUSY 0x5555555555555555ULL
56 #define IDR_CHEETAH_ALL_NACK (~IDR_CHEETAH_ALL_BUSY)
57 #define IDR_CHEETAH_MAX_BN_PAIRS 32
58 #define IDR_JALAPENO_MAX_BN_PAIRS 4
60 #define IDC_ITID_SHIFT 14
61 #define IDC_BN_SHIFT 24
63 #define IPI_AST PIL_AST
64 #define IPI_RENDEZVOUS PIL_RENDEZVOUS
65 #define IPI_PREEMPT PIL_PREEMPT
66 #define IPI_HARDCLOCK PIL_HARDCLOCK
67 #define IPI_STOP PIL_STOP
68 #define IPI_STOP_HARD PIL_STOP
70 #define IPI_RETRIES 5000
72 struct cpu_start_args {
80 struct tte csa_ttes[PCPU_PAGES];
83 struct ipi_cache_args {
95 struct pmap *ita_pmap;
99 #define ita_va ita_start
104 extern struct pcb stoppcbs[];
106 void cpu_mp_bootstrap(struct pcpu *pc);
107 void cpu_mp_shutdown(void);
109 typedef void cpu_ipi_selected_t(cpuset_t, u_long, u_long, u_long);
110 extern cpu_ipi_selected_t *cpu_ipi_selected;
111 typedef void cpu_ipi_single_t(u_int, u_long, u_long, u_long);
112 extern cpu_ipi_single_t *cpu_ipi_single;
116 extern struct mtx ipi_mtx;
117 extern struct ipi_cache_args ipi_cache_args;
118 extern struct ipi_rd_args ipi_rd_args;
119 extern struct ipi_tlb_args ipi_tlb_args;
121 extern char *mp_tramp_code;
122 extern u_long mp_tramp_code_len;
123 extern u_long mp_tramp_tlb_slots;
124 extern u_long mp_tramp_func;
126 extern void mp_startup(void);
128 extern char tl_ipi_cheetah_dcache_page_inval[];
129 extern char tl_ipi_spitfire_dcache_page_inval[];
130 extern char tl_ipi_spitfire_icache_page_inval[];
132 extern char tl_ipi_level[];
134 extern char tl_ipi_stick_rd[];
135 extern char tl_ipi_tick_rd[];
137 extern char tl_ipi_tlb_context_demap[];
138 extern char tl_ipi_tlb_page_demap[];
139 extern char tl_ipi_tlb_range_demap[];
142 ipi_all_but_self(u_int ipi)
146 if (__predict_false(smp_started == 0))
150 CPU_CLR(PCPU_GET(cpuid), &cpus);
151 mtx_lock_spin(&ipi_mtx);
152 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
153 mtx_unlock_spin(&ipi_mtx);
158 ipi_selected(cpuset_t cpus, u_int ipi)
161 if (__predict_false(smp_started == 0 || CPU_EMPTY(&cpus)))
163 mtx_lock_spin(&ipi_mtx);
164 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
165 mtx_unlock_spin(&ipi_mtx);
169 ipi_cpu(int cpu, u_int ipi)
172 if (__predict_false(smp_started == 0))
174 mtx_lock_spin(&ipi_mtx);
175 cpu_ipi_single(cpu, 0, (u_long)tl_ipi_level, ipi);
176 mtx_unlock_spin(&ipi_mtx);
179 #if defined(_MACHINE_PMAP_H_) && defined(_SYS_MUTEX_H_)
181 static __inline void *
182 ipi_dcache_page_inval(void *func, vm_paddr_t pa)
184 struct ipi_cache_args *ica;
186 if (__predict_false(smp_started == 0))
189 ica = &ipi_cache_args;
190 mtx_lock_spin(&ipi_mtx);
191 ica->ica_mask = all_cpus;
192 CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
194 cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
195 return (&ica->ica_mask);
198 static __inline void *
199 ipi_icache_page_inval(void *func, vm_paddr_t pa)
201 struct ipi_cache_args *ica;
203 if (__predict_false(smp_started == 0))
206 ica = &ipi_cache_args;
207 mtx_lock_spin(&ipi_mtx);
208 ica->ica_mask = all_cpus;
209 CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
211 cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
212 return (&ica->ica_mask);
215 static __inline void *
216 ipi_rd(u_int cpu, void *func, u_long *val)
218 struct ipi_rd_args *ira;
220 if (__predict_false(smp_started == 0))
224 mtx_lock_spin(&ipi_mtx);
225 CPU_SETOF(cpu, &ira->ira_mask);
227 cpu_ipi_single(cpu, 0, (u_long)func, (u_long)ira);
228 return (&ira->ira_mask);
231 static __inline void *
232 ipi_tlb_context_demap(struct pmap *pm)
234 struct ipi_tlb_args *ita;
237 if (__predict_false(smp_started == 0))
240 cpus = pm->pm_active;
241 CPU_AND(&cpus, &all_cpus);
242 CPU_CLR(PCPU_GET(cpuid), &cpus);
243 if (CPU_EMPTY(&cpus)) {
248 mtx_lock_spin(&ipi_mtx);
249 ita->ita_mask = cpus;
251 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
253 return (&ita->ita_mask);
256 static __inline void *
257 ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
259 struct ipi_tlb_args *ita;
262 if (__predict_false(smp_started == 0))
265 cpus = pm->pm_active;
266 CPU_AND(&cpus, &all_cpus);
267 CPU_CLR(PCPU_GET(cpuid), &cpus);
268 if (CPU_EMPTY(&cpus)) {
273 mtx_lock_spin(&ipi_mtx);
274 ita->ita_mask = cpus;
277 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
278 return (&ita->ita_mask);
281 static __inline void *
282 ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
284 struct ipi_tlb_args *ita;
287 if (__predict_false(smp_started == 0))
290 cpus = pm->pm_active;
291 CPU_AND(&cpus, &all_cpus);
292 CPU_CLR(PCPU_GET(cpuid), &cpus);
293 if (CPU_EMPTY(&cpus)) {
298 mtx_lock_spin(&ipi_mtx);
299 ita->ita_mask = cpus;
301 ita->ita_start = start;
303 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap,
305 return (&ita->ita_mask);
309 ipi_wait(void *cookie)
311 volatile cpuset_t *mask;
313 if (__predict_false((mask = cookie) != NULL)) {
314 while (!CPU_EMPTY(mask))
316 mtx_unlock_spin(&ipi_mtx);
321 #endif /* _MACHINE_PMAP_H_ && _SYS_MUTEX_H_ */
329 static __inline void *
330 ipi_dcache_page_inval(void *func __unused, vm_paddr_t pa __unused)
336 static __inline void *
337 ipi_icache_page_inval(void *func __unused, vm_paddr_t pa __unused)
343 static __inline void *
344 ipi_rd(u_int cpu __unused, void *func __unused, u_long *val __unused)
350 static __inline void *
351 ipi_tlb_context_demap(struct pmap *pm __unused)
357 static __inline void *
358 ipi_tlb_page_demap(struct pmap *pm __unused, vm_offset_t va __unused)
364 static __inline void *
365 ipi_tlb_range_demap(struct pmap *pm __unused, vm_offset_t start __unused,
366 __unused vm_offset_t end)
373 ipi_wait(void *cookie __unused)
379 tl_ipi_cheetah_dcache_page_inval(void)
385 tl_ipi_spitfire_dcache_page_inval(void)
391 tl_ipi_spitfire_icache_page_inval(void)
400 #endif /* !_MACHINE_SMP_H_ */