2 * Copyright (c) 1990 The Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
7 * This code is derived from software contributed to Berkeley by
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11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
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18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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34 * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91
35 * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30
39 #ifndef _MACHINE_VMPARAM_H_
40 #define _MACHINE_VMPARAM_H_
43 * Virtual memory related constants, all in bytes
46 #define MAXTSIZ (1*1024*1024*1024) /* max text size */
49 #define DFLDSIZ (128*1024*1024) /* initial data size limit */
52 #define MAXDSIZ (1*1024*1024*1024) /* max data size */
55 #define DFLSSIZ (128*1024*1024) /* initial stack size limit */
58 #define MAXSSIZ (1*1024*1024*1024) /* max stack size */
61 #define SGROWSIZ (128*1024) /* amount to grow stack */
65 * The physical address space is sparsely populated.
67 #define VM_PHYSSEG_SPARSE
70 * The number of PHYSSEG entries must be one greater than the number
71 * of phys_avail entries because the phys_avail entry that spans the
72 * largest physical address that is accessible by ISA DMA is split
73 * into two PHYSSEG entries.
75 #define VM_PHYSSEG_MAX 64
78 * Create three free page pools: VM_FREEPOOL_DEFAULT is the default pool
79 * from which physical pages are allocated and VM_FREEPOOL_DIRECT is
80 * the pool from which physical pages for small UMA objects are
83 #define VM_NFREEPOOL 3
84 #define VM_FREEPOOL_CACHE 2
85 #define VM_FREEPOOL_DEFAULT 0
86 #define VM_FREEPOOL_DIRECT 1
89 * Create two free page lists: VM_FREELIST_DEFAULT is for physical
90 * pages that are above the largest physical address that is
91 * accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages
92 * that are below that address.
94 #define VM_NFREELIST 2
95 #define VM_FREELIST_DEFAULT 0
96 #define VM_FREELIST_ISADMA 1
99 * An allocation size of 16MB is supported in order to optimize the
100 * use of the direct map by UMA. Specifically, a cache line contains
101 * at most four TTEs, collectively mapping 16MB of physical memory.
102 * By reducing the number of distinct 16MB "pages" that are used by UMA,
103 * the physical memory allocator reduces the likelihood of both 4MB
104 * page TLB misses and cache misses caused by 4MB page TLB misses.
106 #define VM_NFREEORDER 12
109 * Enable superpage reservations: 1 level.
111 #ifndef VM_NRESERVLEVEL
112 #define VM_NRESERVLEVEL 1
116 * Level 0 reservations consist of 512 pages.
118 #ifndef VM_LEVEL_0_ORDER
119 #define VM_LEVEL_0_ORDER 9
123 * Address space layout.
125 * UltraSPARC I and II implement a 44 bit virtual address space. The address
126 * space is split into 2 regions at each end of the 64 bit address space, with
127 * an out of range "hole" in the middle. UltraSPARC III implements the full
128 * 64 bit virtual address space, but we don't really have any use for it and
129 * 43 bits of user address space is considered to be "enough", so we ignore it.
131 * Upper region: 0xffffffffffffffff
134 * Hole: 0xfffff7ffffffffff
137 * Lower region: 0x000007ffffffffff
140 * In general we ignore the upper region, and use the lower region as mappable
143 * We define some interesting address constants:
145 * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire
146 * 64 bit address space, mostly just for convenience.
148 * VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end
149 * of the direct mapped region. This maps virtual addresses to physical
150 * addresses directly using 4mb tlb entries, with the physical address encoded
151 * in the lower 43 bits of virtual address. These mappings are convenient
152 * because they do not require page tables, and because they never change they
153 * do not require tlb flushes. However, since these mappings are cacheable,
154 * we must ensure that all pages accessed this way are either not double
155 * mapped, or that all other mappings have virtual color equal to physical
156 * color, in order to avoid creating illegal aliases in the data cache.
158 * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of
159 * mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically
160 * arbitrary, a convenient address is chosen which allows both the kernel text
161 * and data and the prom's address space to be mapped with 1 4mb tsb page.
162 * VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the
163 * amount of physical memory available. Each 4mb tsb page provides 1g of
164 * virtual address space, with the only practical limit being available
167 * VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the
168 * prom address space. On startup the prom's mappings are duplicated in the
169 * kernel tsb, to allow prom memory to be accessed normally by the kernel.
171 * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the
172 * user address space. There are some hardware errata about using addresses
173 * at the boundary of the va hole, so we allow just under 43 bits of user
174 * address space. Note that the kernel and user address spaces overlap, but
175 * this doesn't matter because they use different tlb contexts, and because
176 * the kernel address space is not mapped into each process' address space.
178 #define VM_MIN_ADDRESS (0x0000000000000000UL)
179 #define VM_MAX_ADDRESS (0xffffffffffffffffUL)
181 #define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL)
182 #define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS)
184 #define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL)
185 #define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address)
187 #define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL)
188 #define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL)
190 #define VM_MIN_USER_ADDRESS (0x0000000000000000UL)
191 #define VM_MAX_USER_ADDRESS (0x000007fe00000000UL)
193 #define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS)
194 #define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS)
196 #define KERNBASE (VM_MIN_KERNEL_ADDRESS)
197 #define PROMBASE (VM_MIN_PROM_ADDRESS)
198 #define USRSTACK (VM_MAX_USER_ADDRESS)
201 * How many physical pages per kmem arena virtual page.
203 #ifndef VM_KMEM_SIZE_SCALE
204 #define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2)
208 * Optional floor (in bytes) on the size of the kmem arena.
210 #ifndef VM_KMEM_SIZE_MIN
211 #define VM_KMEM_SIZE_MIN (16 * 1024 * 1024)
215 * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the
218 #ifndef VM_KMEM_SIZE_MAX
219 #define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \
220 VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5)
224 * Initial pagein size of beginning of executable file.
226 #ifndef VM_INITIAL_PAGEIN
227 #define VM_INITIAL_PAGEIN 16
230 #define UMA_MD_SMALL_ALLOC
232 extern u_int tsb_kernel_ldd_phys;
233 extern vm_offset_t vm_max_kernel_address;
236 * Older sparc64 machines have a virtually indexed L1 data cache of 16KB.
237 * Consequently, mapping the same physical page multiple times may have
240 #define ZERO_REGION_SIZE PAGE_SIZE
242 #endif /* !_MACHINE_VMPARAM_H_ */