2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/psychoreg.h>
75 #include <sparc64/pci/psychovar.h>
79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
81 static const struct psycho_desc *psycho_get_desc(device_t);
82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86 static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
88 static void psycho_intr_enable(void *);
89 static void psycho_intr_disable(void *);
90 static void psycho_intr_assign(void *);
91 static void psycho_intr_clear(void *);
92 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
94 /* Interrupt handlers */
95 static driver_filter_t psycho_ue;
96 static driver_filter_t psycho_ce;
97 static driver_filter_t psycho_pci_bus;
98 static driver_filter_t psycho_powerfail;
99 static driver_intr_t psycho_overtemp;
100 #ifdef PSYCHO_MAP_WAKEUP
101 static driver_filter_t psycho_wakeup;
105 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
110 static device_probe_t psycho_probe;
111 static device_attach_t psycho_attach;
112 static bus_read_ivar_t psycho_read_ivar;
113 static bus_setup_intr_t psycho_setup_intr;
114 static bus_alloc_resource_t psycho_alloc_resource;
115 static bus_activate_resource_t psycho_activate_resource;
116 static bus_deactivate_resource_t psycho_deactivate_resource;
117 static bus_release_resource_t psycho_release_resource;
118 static bus_get_dma_tag_t psycho_get_dma_tag;
119 static pcib_maxslots_t psycho_maxslots;
120 static pcib_read_config_t psycho_read_config;
121 static pcib_write_config_t psycho_write_config;
122 static pcib_route_interrupt_t psycho_route_interrupt;
123 static ofw_bus_get_node_t psycho_get_node;
124 static ofw_pci_setup_device_t psycho_setup_device;
126 static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130 DEVMETHOD(device_shutdown, bus_generic_shutdown),
131 DEVMETHOD(device_suspend, bus_generic_suspend),
132 DEVMETHOD(device_resume, bus_generic_resume),
135 DEVMETHOD(bus_print_child, bus_generic_print_child),
136 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
137 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
138 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
139 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
140 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
141 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
142 DEVMETHOD(bus_release_resource, psycho_release_resource),
143 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr),
144 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
147 DEVMETHOD(pcib_maxslots, psycho_maxslots),
148 DEVMETHOD(pcib_read_config, psycho_read_config),
149 DEVMETHOD(pcib_write_config, psycho_write_config),
150 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
152 /* ofw_bus interface */
153 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
155 /* ofw_pci interface */
156 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
161 static devclass_t psycho_devclass;
163 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
164 sizeof(struct psycho_softc));
165 EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0,
168 static SLIST_HEAD(, psycho_softc) psycho_softcs =
169 SLIST_HEAD_INITIALIZER(psycho_softcs);
171 static const struct intr_controller psycho_ic = {
178 struct psycho_icarg {
179 struct psycho_softc *pica_sc;
184 #define PSYCHO_READ8(sc, off) \
185 bus_read_8((sc)->sc_mem_res, (off))
186 #define PSYCHO_WRITE8(sc, off, v) \
187 bus_write_8((sc)->sc_mem_res, (off), (v))
188 #define PCICTL_READ8(sc, off) \
189 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
190 #define PCICTL_WRITE8(sc, off, v) \
191 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
194 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
195 * single PCI bus and does not have a streaming buffer. It often has an APB
196 * (advanced PCI bridge) connected to it, which was designed specifically for
197 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
198 * appears as two "Simba"'s underneath the Sabre.
200 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
201 * basically the same as Sabre but without an APB underneath it.
203 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
204 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
205 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
206 * will usually find a "Psycho+" since I don't think the original "Psycho"
207 * ever shipped, and if it did it would be in the U30.
209 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
210 * both part of the same IC, they only have a single register space. As such,
211 * they need to be configured together, even though the autoconfiguration will
212 * attach them separately.
214 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
215 * as pci1 and pci2, although they have been implemented with other PCI bus
216 * numbers on some machines.
218 * On UltraII machines, there can be any number of "Psycho+" ICs, each
219 * providing two PCI buses.
223 const char *pd_string;
228 static const struct psycho_desc const psycho_compats[] = {
229 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
230 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
231 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
235 static const struct psycho_desc const psycho_models[] = {
236 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
237 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
241 static const struct psycho_desc *
242 psycho_find_desc(const struct psycho_desc *table, const char *string)
244 const struct psycho_desc *desc;
248 for (desc = table; desc->pd_string != NULL; desc++)
249 if (strcmp(desc->pd_string, string) == 0)
254 static const struct psycho_desc *
255 psycho_get_desc(device_t dev)
257 const struct psycho_desc *rv;
259 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
261 rv = psycho_find_desc(psycho_compats,
262 ofw_bus_get_compat(dev));
267 psycho_probe(device_t dev)
271 dtype = ofw_bus_get_type(dev);
272 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
273 psycho_get_desc(dev) != NULL) {
274 device_set_desc(dev, "U2P UPA-PCI bridge");
281 psycho_attach(device_t dev)
283 struct psycho_icarg *pica;
284 struct psycho_softc *asc, *sc, *osc;
285 struct ofw_pci_ranges *range;
286 const struct psycho_desc *desc;
287 bus_addr_t intrclr, intrmap;
290 uint32_t dvmabase, prop, prop_array[2];
294 node = ofw_bus_get_node(dev);
295 sc = device_get_softc(dev);
296 desc = psycho_get_desc(dev);
300 sc->sc_mode = desc->pd_mode;
303 * The Psycho gets three register banks:
304 * (0) per-PBM configuration and status registers
305 * (1) per-PBM PCI configuration space, containing only the
306 * PBM 256-byte PCI header
307 * (2) the shared Psycho configuration registers
309 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
312 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
313 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
314 switch (sc->sc_pcictl) {
322 panic("%s: bogus PCI control register location",
328 sc->sc_pcictl = PSR_PCICTL0;
331 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
332 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
334 if (sc->sc_mem_res == NULL)
335 panic("%s: could not allocate registers", __func__);
338 * Match other Psychos that are already configured against
339 * the base physical address. This will be the same for a
340 * pair of devices that share register space.
343 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
344 if (rman_get_start(asc->sc_mem_res) ==
345 rman_get_start(sc->sc_mem_res)) {
352 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
354 if (sc->sc_mtx == NULL)
355 panic("%s: could not malloc mutex", __func__);
356 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
358 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
359 panic("%s: no partner expected", __func__);
360 if (mtx_initialized(osc->sc_mtx) == 0)
361 panic("%s: mutex not initialized", __func__);
362 sc->sc_mtx = osc->sc_mtx;
365 csr = PSYCHO_READ8(sc, PSR_CS);
366 ver = PSYCHO_GCSR_VERS(csr);
367 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
368 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
369 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
370 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
374 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
375 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
376 'A' + sc->sc_half, prop / 1000 / 1000);
378 /* Set up the PCI control and PCI diagnostic registers. */
380 csr = PCICTL_READ8(sc, PCR_CS);
381 csr &= ~PCICTL_ARB_PARK;
382 if (OF_getproplen(node, "no-bus-parking") < 0)
383 csr |= PCICTL_ARB_PARK;
385 /* Workarounds for version specific bugs. */
386 dr = PCICTL_READ8(sc, PCR_DIAG);
390 dr &= ~DIAG_DWSYNC_DIS;
394 csr &= ~PCICTL_ARB_PARK;
395 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
399 dr |= DIAG_DWSYNC_DIS;
400 dr &= ~DIAG_RTRY_DIS;
405 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
406 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
408 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
409 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
410 (unsigned long long)csr);
412 PCICTL_WRITE8(sc, PCR_CS, csr);
414 dr &= ~DIAG_ISYNC_DIS;
416 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
417 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
418 (unsigned long long)dr);
420 PCICTL_WRITE8(sc, PCR_DIAG, dr);
422 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
423 /* Use the PROM preset for now. */
424 csr = PCICTL_READ8(sc, PCR_TAS);
426 panic("%s: Hummingbird/Sabre TAS not initialized.",
428 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
432 /* Initialize memory and I/O rmans. */
433 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
434 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
435 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
436 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
437 panic("%s: failed to set up I/O rman", __func__);
438 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
439 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
440 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
441 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
442 panic("%s: failed to set up memory rman", __func__);
444 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
446 * Make sure that the expected ranges are present. The
447 * OFW_PCI_CS_MEM64 one is not currently used though.
449 if (i != PSYCHO_NRANGE)
450 panic("%s: unsupported number of ranges", __func__);
452 * Find the addresses of the various bus spaces.
453 * There should not be multiple ones of one kind.
454 * The physical start addresses of the ranges are the configuration,
455 * memory and I/O handles.
457 for (i = 0; i < PSYCHO_NRANGE; i++) {
458 j = OFW_PCI_RANGE_CS(&range[i]);
459 if (sc->sc_pci_bh[j] != 0)
460 panic("%s: duplicate range for space %d",
462 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
464 free(range, M_OFWPROP);
466 /* Register the softc, this is needed for paired Psychos. */
467 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
470 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
471 * to arrive here, do the interrupt setup and start up the IOMMU.
475 * Hunt through all the interrupt mapping regs and register
476 * our interrupt controller for the corresponding interrupt
477 * vectors. We do this early in order to be able to catch
480 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
481 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
484 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
486 panic("%s: could not allocate interrupt "
487 "controller argument", __func__);
489 pica->pica_map = intrmap;
490 pica->pica_clr = intrclr;
493 * Enable all interrupts and clear all interrupt
494 * states. This aids the debugging of interrupt
498 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
499 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
500 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
501 intrmap), (u_long)intrclr);
502 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
503 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
504 PSYCHO_WRITE8(sc, intrmap,
505 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
508 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
509 i), &psycho_ic, pica);
511 device_printf(dev, "could not register "
512 "interrupt controller for INO %d (%d)\n",
516 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
517 sparc64_counter_init(device_get_nameunit(dev),
518 rman_get_bustag(sc->sc_mem_res),
519 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
522 * Set up IOMMU and PCI configuration if we're the first
523 * of a pair of Psychos to arrive here or a Hummingbird
526 * We should calculate a TSB size based on amount of RAM
527 * and number of bus controllers and number and type of
530 * For the moment, 32KB should be more than enough.
532 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
534 if (sc->sc_is == NULL)
535 panic("%s: could not malloc IOMMU state", __func__);
536 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
537 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
539 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
541 if (sc->sc_dma_methods == NULL)
542 panic("%s: could not malloc DMA methods",
544 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
545 sizeof(*sc->sc_dma_methods));
546 sc->sc_dma_methods->dm_dmamap_sync =
548 sc->sc_is->is_pmaxaddr =
549 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
551 sc->sc_dma_methods = &iommu_dma_methods;
552 sc->sc_is->is_pmaxaddr =
553 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
555 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
556 if (OF_getproplen(node, "no-streaming-cache") < 0)
557 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
558 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
559 psycho_iommu_init(sc, 3, dvmabase);
561 /* Just copy IOMMU state, config tag and address. */
562 sc->sc_dma_methods = &iommu_dma_methods;
563 sc->sc_is = osc->sc_is;
564 if (OF_getproplen(node, "no-streaming-cache") < 0)
565 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
566 iommu_reset(sc->sc_is);
569 /* Allocate our tags. */
570 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
571 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
572 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
573 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
574 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
575 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
576 panic("%s: bus_dma_tag_create failed", __func__);
577 /* Customize the tag. */
578 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
579 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods;
581 i = OF_getprop(node, "bus-range", (void *)prop_array,
584 panic("%s: could not get bus-range", __func__);
585 if (i != sizeof(prop_array))
586 panic("%s: broken bus-range (%d)", __func__, i);
587 sc->sc_pci_secbus = prop_array[0];
588 sc->sc_pci_subbus = prop_array[1];
590 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
591 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
593 /* Clear any pending PCI error bits. */
594 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
595 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
596 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
597 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
598 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
602 * Establish handlers for interesting interrupts...
604 * XXX We need to remember these and remove this to support
605 * hotplug on the UPA/FHC bus.
607 * XXX Not all controllers have these, but installing them
608 * is better than trying to sort through this mess.
610 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
611 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
612 #ifdef DEBUGGER_ON_POWERFAIL
613 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
616 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
617 (driver_intr_t *)psycho_powerfail);
619 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
621 * Hummingbirds/Sabres do not have the following two
626 * The spare hardware interrupt is used for the
627 * over-temperature interrupt.
629 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
630 NULL, psycho_overtemp);
631 #ifdef PSYCHO_MAP_WAKEUP
633 * psycho_wakeup() doesn't do anything useful right
636 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
637 psycho_wakeup, NULL);
638 #endif /* PSYCHO_MAP_WAKEUP */
642 * Register a PCI bus error interrupt handler according to which
643 * half this is. Hummingbird/Sabre don't have a PCI bus B error
644 * interrupt but they are also only used for PCI bus A.
646 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
647 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
650 * Set the latency timer register as this isn't always done by the
653 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
654 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
656 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
657 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
658 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
659 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
661 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
662 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
663 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
664 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
666 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
668 * On E250 the interrupt map entry for the EBus bridge is wrong,
669 * causing incorrect interrupts to be assigned to some devices on
670 * the EBus. Work around it by changing our copy of the interrupt
671 * map mask to perform a full comparison of the INO. That way
672 * the interrupt map entry for the EBus bridge won't match at all
673 * and the INOs specified in the "interrupts" properties of the
674 * EBus devices will be used directly instead.
676 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
677 sc->sc_pci_iinfo.opi_imapmsk != NULL)
678 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
679 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
681 device_add_child(dev, "pci", -1);
682 return (bus_generic_attach(dev));
686 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
687 driver_filter_t filt, driver_intr_t intr)
693 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
694 SYS_RES_IRQ, &rid, RF_ACTIVE);
695 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
697 * These interrupts aren't mandatory and not available
698 * with all controllers (not even Psychos).
702 if (sc->sc_irq_res[index] == NULL ||
703 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
705 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
706 intr_vectors[vec].iv_ic != &psycho_ic ||
707 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
708 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc,
709 &sc->sc_ihand[index]) != 0)
710 panic("%s: failed to set up interrupt %d", __func__, index);
714 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
715 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
717 bus_addr_t intrclr, intrmap;
722 * XXX we only compare INOs rather than INRs since the firmware may
723 * not provide the IGN and the IGN is constant for all devices on
724 * that PCI controller.
725 * This could cause problems for the FFB/external interrupt which
726 * has a full vector that can be set arbitrarily.
729 if (ino > PSYCHO_MAX_INO) {
730 device_printf(sc->sc_dev, "out of range INO %d requested\n",
736 /* Hunt through OBIO first. */
737 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
738 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
739 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
741 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
742 (intrmap == PSR_TIMER0_INT_MAP ||
743 intrmap == PSR_TIMER1_INT_MAP ||
744 intrmap == PSR_PCIBERR_INT_MAP ||
745 intrmap == PSR_PWRMGT_INT_MAP))
747 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
755 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
756 /* Now do PCI interrupts. */
757 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
758 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
760 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
761 (intrmap == PSR_PCIA2_INT_MAP ||
762 intrmap == PSR_PCIA3_INT_MAP))
764 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
765 intrclr += 8 * (ino & 3);
766 diag = (diag >> ((ino & 3) * 2)) & 2;
772 if (intrmapptr != NULL)
773 *intrmapptr = intrmap;
774 if (intrclrptr != NULL)
775 *intrclrptr = intrclr;
776 if (intrdiagptr != NULL)
787 struct psycho_softc *sc = arg;
790 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
791 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
793 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
794 * the AFAR to be set to the physical address of the TTE entry that
795 * was invalid/write protected. Call into the IOMMU code to have
796 * them decoded to virtual I/O addresses.
798 if ((afsr & UEAFSR_P_DTE) != 0)
799 iommu_decode_fault(sc->sc_is, afar);
800 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
801 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
802 return (FILTER_HANDLED);
808 struct psycho_softc *sc = arg;
811 mtx_lock_spin(sc->sc_mtx);
812 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
813 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
814 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
815 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
816 /* Clear the error bits that we caught. */
817 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
818 mtx_unlock_spin(sc->sc_mtx);
819 return (FILTER_HANDLED);
823 psycho_pci_bus(void *arg)
825 struct psycho_softc *sc = arg;
828 afar = PCICTL_READ8(sc, PCR_AFA);
829 afsr = PCICTL_READ8(sc, PCR_AFS);
830 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
831 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
833 return (FILTER_HANDLED);
837 psycho_powerfail(void *arg)
839 #ifdef DEBUGGER_ON_POWERFAIL
840 struct psycho_softc *sc = arg;
842 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
846 /* As the interrupt is cleared we may be called multiple times. */
848 return (FILTER_HANDLED);
850 printf("Power Failure Detected: Shutting down NOW.\n");
853 return (FILTER_HANDLED);
857 psycho_overtemp(void *arg)
861 /* As the interrupt is cleared we may be called multiple times. */
865 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
866 shutdown_nice(RB_POWEROFF);
869 #ifdef PSYCHO_MAP_WAKEUP
871 psycho_wakeup(void *arg)
873 struct psycho_softc *sc = arg;
875 /* We don't really have a framework to deal with this properly. */
876 device_printf(sc->sc_dev, "power management wakeup\n");
877 return (FILTER_HANDLED);
879 #endif /* PSYCHO_MAP_WAKEUP */
882 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
884 struct iommu_state *is = sc->sc_is;
886 /* Punch in our copies. */
887 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
888 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
889 is->is_iommu = PSR_IOMMU;
890 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
891 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
892 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
893 is->is_dva = PSR_IOMMU_SVADIAG;
894 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
896 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
900 psycho_maxslots(device_t dev)
903 /* XXX: is this correct? */
904 return (PCI_SLOTMAX);
908 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
911 struct psycho_softc *sc;
912 bus_space_handle_t bh;
919 sc = device_get_softc(dev);
920 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
921 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
924 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
927 * The Hummingbird and Sabre bridges are picky in that they
928 * only allow their config space to be accessed using the
929 * "native" width of the respective register being accessed
930 * and return semi-random other content of their config space
931 * otherwise. Given that the PCI specs don't say anything
932 * about such a (unusual) limitation and lots of stuff expects
933 * to be able to access the contents of the config space at
934 * any width we allow just that. We do this by using a copy
935 * of the header of the bridge (the rest is all zero anyway)
936 * read during attach (expect for PCIR_STATUS) in order to
938 * The Psycho bridges contain a dupe of their header at 0x80
939 * which we nullify that way also.
941 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
943 if (offset % width != 0)
946 if (reg >= sizeof(sc->sc_pci_hpbcfg))
949 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
950 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
951 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
952 bus_space_read_2(sc->sc_pci_cfgt, bh,
953 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
954 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
958 return (sc->sc_pci_hpbcfg[reg]);
960 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
962 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
966 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
969 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
973 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
977 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
981 panic("%s: bad width", __func__);
987 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
988 __func__, bus, slot, func, reg);
996 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
997 u_int reg, uint32_t val, int width)
999 struct psycho_softc *sc;
1000 bus_space_handle_t bh;
1003 sc = device_get_softc(dev);
1004 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1005 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1008 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1009 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1012 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1015 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1018 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1021 panic("%s: bad width", __func__);
1027 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1029 struct psycho_softc *sc;
1030 struct ofw_pci_register reg;
1032 ofw_pci_intr_t pintr, mintr;
1033 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1035 sc = device_get_softc(bridge);
1037 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1038 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1042 * If this is outside of the range for an intpin, it's likely a full
1043 * INO, and no mapping is required at all; this happens on the U30,
1044 * where there's no interrupt map at the Psycho node. Fortunately,
1045 * there seem to be no INOs in the intpin range on this boxen, so
1046 * this easy heuristics will do.
1051 * Guess the INO; we always assume that this is a non-OBIO
1052 * device, and that pin is a "real" intpin number. Determine
1053 * the mapping register to be used by the slot number.
1054 * We only need to do this on E450s, it seems; here, the slot numbers
1055 * for bus A are one-based, while those for bus B seemingly have an
1056 * offset of 2 (hence the factor of 3 below).
1058 intrmap = PSR_PCIA0_INT_MAP +
1059 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1060 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1061 device_printf(bridge,
1062 "guessing interrupt %d for device %d.%d pin %d\n",
1063 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1068 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1070 struct psycho_softc *sc;
1072 sc = device_get_softc(dev);
1074 case PCIB_IVAR_DOMAIN:
1075 *result = device_get_unit(dev);
1078 *result = sc->sc_pci_secbus;
1085 sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1087 struct iommu_state *is = dt->dt_cookie;
1089 if ((map->dm_flags & DMF_LOADED) == 0)
1092 if ((op & BUS_DMASYNC_POSTREAD) != 0)
1093 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
1094 PSR_DMA_WRITE_SYNC);
1096 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1101 psycho_intr_enable(void *arg)
1103 struct intr_vector *iv = arg;
1104 struct psycho_icarg *pica = iv->iv_icarg;
1106 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1107 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1111 psycho_intr_disable(void *arg)
1113 struct intr_vector *iv = arg;
1114 struct psycho_icarg *pica = iv->iv_icarg;
1116 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1120 psycho_intr_assign(void *arg)
1122 struct intr_vector *iv = arg;
1123 struct psycho_icarg *pica = iv->iv_icarg;
1125 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1126 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1130 psycho_intr_clear(void *arg)
1132 struct intr_vector *iv = arg;
1133 struct psycho_icarg *pica = iv->iv_icarg;
1135 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1139 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1140 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1143 struct psycho_softc *sc;
1146 sc = device_get_softc(dev);
1148 * Make sure the vector is fully specified and we registered
1149 * our interrupt controller for it.
1151 vec = rman_get_start(ires);
1152 if (INTIGN(vec) != sc->sc_ign ||
1153 intr_vectors[vec].iv_ic != &psycho_ic) {
1154 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1157 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1161 static struct resource *
1162 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1163 u_long start, u_long end, u_long count, u_int flags)
1165 struct psycho_softc *sc;
1166 struct resource *rv;
1169 bus_space_handle_t bh;
1170 int needactivate = flags & RF_ACTIVE;
1172 flags &= ~RF_ACTIVE;
1174 sc = device_get_softc(bus);
1175 if (type == SYS_RES_IRQ) {
1177 * XXX: Don't accept blank ranges for now, only single
1178 * interrupts. The other case should not happen with
1179 * the MI PCI code...
1180 * XXX: This may return a resource that is out of the
1181 * range that was specified. Is this correct...?
1184 panic("%s: XXX: interrupt range", __func__);
1185 start = end = INTMAP_VEC(sc->sc_ign, end);
1186 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
1187 type, rid, start, end, count, flags));
1190 case SYS_RES_MEMORY:
1191 rm = &sc->sc_pci_mem_rman;
1192 bt = sc->sc_pci_memt;
1193 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1195 case SYS_RES_IOPORT:
1196 rm = &sc->sc_pci_io_rman;
1197 bt = sc->sc_pci_iot;
1198 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1205 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1208 rman_set_rid(rv, *rid);
1209 bh += rman_get_start(rv);
1210 rman_set_bustag(rv, bt);
1211 rman_set_bushandle(rv, bh);
1214 if (bus_activate_resource(child, type, *rid, rv)) {
1215 rman_release_resource(rv);
1223 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1229 if (type == SYS_RES_IRQ)
1230 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1232 if (type == SYS_RES_MEMORY) {
1234 * Need to memory-map the device space, as some drivers
1235 * depend on the virtual address being set and usable.
1237 error = sparc64_bus_mem_map(rman_get_bustag(r),
1238 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1241 rman_set_virtual(r, p);
1243 return (rman_activate_resource(r));
1247 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
1251 if (type == SYS_RES_IRQ)
1252 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1254 if (type == SYS_RES_MEMORY) {
1255 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1256 rman_set_virtual(r, NULL);
1258 return (rman_deactivate_resource(r));
1262 psycho_release_resource(device_t bus, device_t child, int type, int rid,
1267 if (type == SYS_RES_IRQ)
1268 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1270 if (rman_get_flags(r) & RF_ACTIVE) {
1271 error = bus_deactivate_resource(child, type, rid, r);
1275 return (rman_release_resource(r));
1278 static bus_dma_tag_t
1279 psycho_get_dma_tag(device_t bus, device_t child __unused)
1281 struct psycho_softc *sc;
1283 sc = device_get_softc(bus);
1284 return (sc->sc_pci_dmat);
1288 psycho_get_node(device_t bus, device_t child __unused)
1290 struct psycho_softc *sc;
1292 sc = device_get_softc(bus);
1293 /* We only have one child, the PCI bus, which needs our own node. */
1294 return (sc->sc_node);
1298 psycho_setup_device(device_t bus, device_t child)
1300 struct psycho_softc *sc;
1303 sc = device_get_softc(bus);
1305 * Revision 0 EBus bridges have a bug which prevents them from
1306 * working when bus parking is enabled.
1308 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1309 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1310 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1311 sizeof(rev)) > 0 && rev == 0)
1312 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1316 static bus_space_tag_t
1317 psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1321 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1324 panic("%s: out of memory", __func__);
1326 bt->bst_cookie = sc;
1327 bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
1328 bt->bst_type = type;