2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/reboot.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/psychoreg.h>
75 #include <sparc64/pci/psychovar.h>
79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
81 static const struct psycho_desc *psycho_get_desc(device_t);
82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86 static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
88 static void psycho_intr_enable(void *);
89 static void psycho_intr_disable(void *);
90 static void psycho_intr_assign(void *);
91 static void psycho_intr_clear(void *);
92 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int);
94 /* Interrupt handlers */
95 static driver_filter_t psycho_ue;
96 static driver_filter_t psycho_ce;
97 static driver_filter_t psycho_pci_bus;
98 static driver_filter_t psycho_powerfail;
99 static driver_intr_t psycho_overtemp;
100 #ifdef PSYCHO_MAP_WAKEUP
101 static driver_filter_t psycho_wakeup;
105 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
110 static device_probe_t psycho_probe;
111 static device_attach_t psycho_attach;
112 static bus_read_ivar_t psycho_read_ivar;
113 static bus_setup_intr_t psycho_setup_intr;
114 static bus_alloc_resource_t psycho_alloc_resource;
115 static bus_activate_resource_t psycho_activate_resource;
116 static bus_deactivate_resource_t psycho_deactivate_resource;
117 static bus_release_resource_t psycho_release_resource;
118 static bus_get_dma_tag_t psycho_get_dma_tag;
119 static pcib_maxslots_t psycho_maxslots;
120 static pcib_read_config_t psycho_read_config;
121 static pcib_write_config_t psycho_write_config;
122 static pcib_route_interrupt_t psycho_route_interrupt;
123 static ofw_bus_get_node_t psycho_get_node;
124 static ofw_pci_setup_device_t psycho_setup_device;
126 static device_method_t psycho_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, psycho_probe),
129 DEVMETHOD(device_attach, psycho_attach),
130 DEVMETHOD(device_shutdown, bus_generic_shutdown),
131 DEVMETHOD(device_suspend, bus_generic_suspend),
132 DEVMETHOD(device_resume, bus_generic_resume),
135 DEVMETHOD(bus_read_ivar, psycho_read_ivar),
136 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
137 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
139 DEVMETHOD(bus_activate_resource, psycho_activate_resource),
140 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource),
141 DEVMETHOD(bus_release_resource, psycho_release_resource),
142 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag),
145 DEVMETHOD(pcib_maxslots, psycho_maxslots),
146 DEVMETHOD(pcib_read_config, psycho_read_config),
147 DEVMETHOD(pcib_write_config, psycho_write_config),
148 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
150 /* ofw_bus interface */
151 DEVMETHOD(ofw_bus_get_node, psycho_get_node),
153 /* ofw_pci interface */
154 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
159 static devclass_t psycho_devclass;
161 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
162 sizeof(struct psycho_softc));
163 EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0,
166 static SLIST_HEAD(, psycho_softc) psycho_softcs =
167 SLIST_HEAD_INITIALIZER(psycho_softcs);
169 static const struct intr_controller psycho_ic = {
176 struct psycho_icarg {
177 struct psycho_softc *pica_sc;
182 #define PSYCHO_READ8(sc, off) \
183 bus_read_8((sc)->sc_mem_res, (off))
184 #define PSYCHO_WRITE8(sc, off, v) \
185 bus_write_8((sc)->sc_mem_res, (off), (v))
186 #define PCICTL_READ8(sc, off) \
187 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
188 #define PCICTL_WRITE8(sc, off, v) \
189 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
192 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
193 * single PCI bus and does not have a streaming buffer. It often has an APB
194 * (advanced PCI bridge) connected to it, which was designed specifically for
195 * the IIi. The APB let's the IIi handle two independednt PCI buses, and
196 * appears as two "Simba"'s underneath the Sabre.
198 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
199 * basically the same as Sabre but without an APB underneath it.
201 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
202 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
203 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
204 * will usually find a "Psycho+" since I don't think the original "Psycho"
205 * ever shipped, and if it did it would be in the U30.
207 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
208 * both part of the same IC, they only have a single register space. As such,
209 * they need to be configured together, even though the autoconfiguration will
210 * attach them separately.
212 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
213 * as pci1 and pci2, although they have been implemented with other PCI bus
214 * numbers on some machines.
216 * On UltraII machines, there can be any number of "Psycho+" ICs, each
217 * providing two PCI buses.
221 const char *pd_string;
226 static const struct psycho_desc const psycho_compats[] = {
227 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
228 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
229 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
233 static const struct psycho_desc const psycho_models[] = {
234 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
235 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
239 static const struct psycho_desc *
240 psycho_find_desc(const struct psycho_desc *table, const char *string)
242 const struct psycho_desc *desc;
246 for (desc = table; desc->pd_string != NULL; desc++)
247 if (strcmp(desc->pd_string, string) == 0)
252 static const struct psycho_desc *
253 psycho_get_desc(device_t dev)
255 const struct psycho_desc *rv;
257 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
259 rv = psycho_find_desc(psycho_compats,
260 ofw_bus_get_compat(dev));
265 psycho_probe(device_t dev)
269 dtype = ofw_bus_get_type(dev);
270 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
271 psycho_get_desc(dev) != NULL) {
272 device_set_desc(dev, "U2P UPA-PCI bridge");
279 psycho_attach(device_t dev)
281 struct psycho_icarg *pica;
282 struct psycho_softc *asc, *sc, *osc;
283 struct ofw_pci_ranges *range;
284 const struct psycho_desc *desc;
285 bus_addr_t intrclr, intrmap;
288 uint32_t dvmabase, prop, prop_array[2];
292 node = ofw_bus_get_node(dev);
293 sc = device_get_softc(dev);
294 desc = psycho_get_desc(dev);
298 sc->sc_mode = desc->pd_mode;
301 * The Psycho gets three register banks:
302 * (0) per-PBM configuration and status registers
303 * (1) per-PBM PCI configuration space, containing only the
304 * PBM 256-byte PCI header
305 * (2) the shared Psycho configuration registers
307 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
310 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
311 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
312 switch (sc->sc_pcictl) {
320 panic("%s: bogus PCI control register location",
326 sc->sc_pcictl = PSR_PCICTL0;
329 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
330 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
332 if (sc->sc_mem_res == NULL)
333 panic("%s: could not allocate registers", __func__);
336 * Match other Psychos that are already configured against
337 * the base physical address. This will be the same for a
338 * pair of devices that share register space.
341 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
342 if (rman_get_start(asc->sc_mem_res) ==
343 rman_get_start(sc->sc_mem_res)) {
350 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
352 if (sc->sc_mtx == NULL)
353 panic("%s: could not malloc mutex", __func__);
354 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
356 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
357 panic("%s: no partner expected", __func__);
358 if (mtx_initialized(osc->sc_mtx) == 0)
359 panic("%s: mutex not initialized", __func__);
360 sc->sc_mtx = osc->sc_mtx;
363 csr = PSYCHO_READ8(sc, PSR_CS);
364 ver = PSYCHO_GCSR_VERS(csr);
365 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
366 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
367 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
368 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
372 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
373 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
374 'A' + sc->sc_half, prop / 1000 / 1000);
376 /* Set up the PCI control and PCI diagnostic registers. */
378 csr = PCICTL_READ8(sc, PCR_CS);
379 csr &= ~PCICTL_ARB_PARK;
380 if (OF_getproplen(node, "no-bus-parking") < 0)
381 csr |= PCICTL_ARB_PARK;
383 /* Workarounds for version specific bugs. */
384 dr = PCICTL_READ8(sc, PCR_DIAG);
388 dr &= ~DIAG_DWSYNC_DIS;
392 csr &= ~PCICTL_ARB_PARK;
393 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
397 dr |= DIAG_DWSYNC_DIS;
398 dr &= ~DIAG_RTRY_DIS;
403 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
404 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
406 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
407 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
408 (unsigned long long)csr);
410 PCICTL_WRITE8(sc, PCR_CS, csr);
412 dr &= ~DIAG_ISYNC_DIS;
414 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
415 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
416 (unsigned long long)dr);
418 PCICTL_WRITE8(sc, PCR_DIAG, dr);
420 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
421 /* Use the PROM preset for now. */
422 csr = PCICTL_READ8(sc, PCR_TAS);
424 panic("%s: Hummingbird/Sabre TAS not initialized.",
426 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
430 /* Initialize memory and I/O rmans. */
431 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
432 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports";
433 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
434 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0)
435 panic("%s: failed to set up I/O rman", __func__);
436 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
437 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory";
438 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
439 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0)
440 panic("%s: failed to set up memory rman", __func__);
442 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
444 * Make sure that the expected ranges are present. The
445 * OFW_PCI_CS_MEM64 one is not currently used though.
447 if (i != PSYCHO_NRANGE)
448 panic("%s: unsupported number of ranges", __func__);
450 * Find the addresses of the various bus spaces.
451 * There should not be multiple ones of one kind.
452 * The physical start addresses of the ranges are the configuration,
453 * memory and I/O handles.
455 for (i = 0; i < PSYCHO_NRANGE; i++) {
456 j = OFW_PCI_RANGE_CS(&range[i]);
457 if (sc->sc_pci_bh[j] != 0)
458 panic("%s: duplicate range for space %d",
460 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
462 free(range, M_OFWPROP);
464 /* Register the softc, this is needed for paired Psychos. */
465 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
468 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
469 * to arrive here, do the interrupt setup and start up the IOMMU.
473 * Hunt through all the interrupt mapping regs and register
474 * our interrupt controller for the corresponding interrupt
475 * vectors. We do this early in order to be able to catch
478 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
479 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
482 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
484 panic("%s: could not allocate interrupt "
485 "controller argument", __func__);
487 pica->pica_map = intrmap;
488 pica->pica_clr = intrclr;
491 * Enable all interrupts and clear all interrupt
492 * states. This aids the debugging of interrupt
496 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
497 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
498 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
499 intrmap), (u_long)intrclr);
500 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
501 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
502 PSYCHO_WRITE8(sc, intrmap,
503 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
506 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
507 i), &psycho_ic, pica);
509 device_printf(dev, "could not register "
510 "interrupt controller for INO %d (%d)\n",
514 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
515 sparc64_counter_init(device_get_nameunit(dev),
516 rman_get_bustag(sc->sc_mem_res),
517 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
520 * Set up IOMMU and PCI configuration if we're the first
521 * of a pair of Psychos to arrive here or a Hummingbird
524 * We should calculate a TSB size based on amount of RAM
525 * and number of bus controllers and number and type of
528 * For the moment, 32KB should be more than enough.
530 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
532 if (sc->sc_is == NULL)
533 panic("%s: could not malloc IOMMU state", __func__);
534 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
535 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
537 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
539 if (sc->sc_dma_methods == NULL)
540 panic("%s: could not malloc DMA methods",
542 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
543 sizeof(*sc->sc_dma_methods));
544 sc->sc_dma_methods->dm_dmamap_sync =
546 sc->sc_is->is_pmaxaddr =
547 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
549 sc->sc_dma_methods = &iommu_dma_methods;
550 sc->sc_is->is_pmaxaddr =
551 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
553 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
554 if (OF_getproplen(node, "no-streaming-cache") < 0)
555 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
556 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
557 psycho_iommu_init(sc, 3, dvmabase);
559 /* Just copy IOMMU state, config tag and address. */
560 sc->sc_dma_methods = &iommu_dma_methods;
561 sc->sc_is = osc->sc_is;
562 if (OF_getproplen(node, "no-streaming-cache") < 0)
563 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
564 iommu_reset(sc->sc_is);
567 /* Allocate our tags. */
568 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
569 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
570 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
571 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
572 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
573 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
574 panic("%s: bus_dma_tag_create failed", __func__);
575 /* Customize the tag. */
576 sc->sc_pci_dmat->dt_cookie = sc->sc_is;
577 sc->sc_pci_dmat->dt_mt = sc->sc_dma_methods;
579 i = OF_getprop(node, "bus-range", (void *)prop_array,
582 panic("%s: could not get bus-range", __func__);
583 if (i != sizeof(prop_array))
584 panic("%s: broken bus-range (%d)", __func__, i);
585 sc->sc_pci_secbus = prop_array[0];
586 sc->sc_pci_subbus = prop_array[1];
588 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
589 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
591 /* Clear any pending PCI error bits. */
592 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
593 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
594 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
595 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
596 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
600 * Establish handlers for interesting interrupts...
602 * XXX We need to remember these and remove this to support
603 * hotplug on the UPA/FHC bus.
605 * XXX Not all controllers have these, but installing them
606 * is better than trying to sort through this mess.
608 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
609 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
610 #ifdef DEBUGGER_ON_POWERFAIL
611 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
614 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
615 (driver_intr_t *)psycho_powerfail);
617 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
619 * Hummingbirds/Sabres do not have the following two
624 * The spare hardware interrupt is used for the
625 * over-temperature interrupt.
627 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
628 NULL, psycho_overtemp);
629 #ifdef PSYCHO_MAP_WAKEUP
631 * psycho_wakeup() doesn't do anything useful right
634 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
635 psycho_wakeup, NULL);
636 #endif /* PSYCHO_MAP_WAKEUP */
640 * Register a PCI bus error interrupt handler according to which
641 * half this is. Hummingbird/Sabre don't have a PCI bus B error
642 * interrupt but they are also only used for PCI bus A.
644 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
645 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
648 * Set the latency timer register as this isn't always done by the
651 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
652 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
654 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
655 le16enc(&sc->sc_pci_hpbcfg[i], bus_space_read_2(
656 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
657 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
659 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
660 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_pci_cfgt,
661 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
662 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
664 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
666 * On E250 the interrupt map entry for the EBus bridge is wrong,
667 * causing incorrect interrupts to be assigned to some devices on
668 * the EBus. Work around it by changing our copy of the interrupt
669 * map mask to perform a full comparison of the INO. That way
670 * the interrupt map entry for the EBus bridge won't match at all
671 * and the INOs specified in the "interrupts" properties of the
672 * EBus devices will be used directly instead.
674 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
675 sc->sc_pci_iinfo.opi_imapmsk != NULL)
676 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[
677 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
679 device_add_child(dev, "pci", -1);
680 return (bus_generic_attach(dev));
684 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
685 driver_filter_t filt, driver_intr_t intr)
691 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
692 SYS_RES_IRQ, &rid, RF_ACTIVE);
693 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
695 * These interrupts aren't mandatory and not available
696 * with all controllers (not even Psychos).
700 if (sc->sc_irq_res[index] == NULL ||
701 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
703 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
704 intr_vectors[vec].iv_ic != &psycho_ic ||
705 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
706 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc,
707 &sc->sc_ihand[index]) != 0)
708 panic("%s: failed to set up interrupt %d", __func__, index);
712 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
713 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
715 bus_addr_t intrclr, intrmap;
720 * XXX we only compare INOs rather than INRs since the firmware may
721 * not provide the IGN and the IGN is constant for all devices on
722 * that PCI controller.
723 * This could cause problems for the FFB/external interrupt which
724 * has a full vector that can be set arbitrarily.
727 if (ino > PSYCHO_MAX_INO) {
728 device_printf(sc->sc_dev, "out of range INO %d requested\n",
734 /* Hunt through OBIO first. */
735 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
736 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
737 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
739 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
740 (intrmap == PSR_TIMER0_INT_MAP ||
741 intrmap == PSR_TIMER1_INT_MAP ||
742 intrmap == PSR_PCIBERR_INT_MAP ||
743 intrmap == PSR_PWRMGT_INT_MAP))
745 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
753 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
754 /* Now do PCI interrupts. */
755 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
756 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
758 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
759 (intrmap == PSR_PCIA2_INT_MAP ||
760 intrmap == PSR_PCIA3_INT_MAP))
762 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
763 intrclr += 8 * (ino & 3);
764 diag = (diag >> ((ino & 3) * 2)) & 2;
770 if (intrmapptr != NULL)
771 *intrmapptr = intrmap;
772 if (intrclrptr != NULL)
773 *intrclrptr = intrclr;
774 if (intrdiagptr != NULL)
785 struct psycho_softc *sc = arg;
788 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
789 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
791 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
792 * the AFAR to be set to the physical address of the TTE entry that
793 * was invalid/write protected. Call into the IOMMU code to have
794 * them decoded to virtual I/O addresses.
796 if ((afsr & UEAFSR_P_DTE) != 0)
797 iommu_decode_fault(sc->sc_is, afar);
798 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
799 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
800 return (FILTER_HANDLED);
806 struct psycho_softc *sc = arg;
809 mtx_lock_spin(sc->sc_mtx);
810 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
811 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
812 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
813 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
814 /* Clear the error bits that we caught. */
815 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
816 mtx_unlock_spin(sc->sc_mtx);
817 return (FILTER_HANDLED);
821 psycho_pci_bus(void *arg)
823 struct psycho_softc *sc = arg;
826 afar = PCICTL_READ8(sc, PCR_AFA);
827 afsr = PCICTL_READ8(sc, PCR_AFS);
828 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
829 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
831 return (FILTER_HANDLED);
835 psycho_powerfail(void *arg)
837 #ifdef DEBUGGER_ON_POWERFAIL
838 struct psycho_softc *sc = arg;
840 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
844 /* As the interrupt is cleared we may be called multiple times. */
846 return (FILTER_HANDLED);
848 printf("Power Failure Detected: Shutting down NOW.\n");
851 return (FILTER_HANDLED);
855 psycho_overtemp(void *arg)
859 /* As the interrupt is cleared we may be called multiple times. */
863 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
864 shutdown_nice(RB_POWEROFF);
867 #ifdef PSYCHO_MAP_WAKEUP
869 psycho_wakeup(void *arg)
871 struct psycho_softc *sc = arg;
873 /* We don't really have a framework to deal with this properly. */
874 device_printf(sc->sc_dev, "power management wakeup\n");
875 return (FILTER_HANDLED);
877 #endif /* PSYCHO_MAP_WAKEUP */
880 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
882 struct iommu_state *is = sc->sc_is;
884 /* Punch in our copies. */
885 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
886 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
887 is->is_iommu = PSR_IOMMU;
888 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
889 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
890 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
891 is->is_dva = PSR_IOMMU_SVADIAG;
892 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
894 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
898 psycho_maxslots(device_t dev)
901 /* XXX: is this correct? */
902 return (PCI_SLOTMAX);
906 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
909 struct psycho_softc *sc;
910 bus_space_handle_t bh;
917 sc = device_get_softc(dev);
918 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
919 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
922 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
925 * The Hummingbird and Sabre bridges are picky in that they
926 * only allow their config space to be accessed using the
927 * "native" width of the respective register being accessed
928 * and return semi-random other content of their config space
929 * otherwise. Given that the PCI specs don't say anything
930 * about such a (unusual) limitation and lots of stuff expects
931 * to be able to access the contents of the config space at
932 * any width we allow just that. We do this by using a copy
933 * of the header of the bridge (the rest is all zero anyway)
934 * read during attach (expect for PCIR_STATUS) in order to
936 * The Psycho bridges contain a dupe of their header at 0x80
937 * which we nullify that way also.
939 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE &&
941 if (offset % width != 0)
944 if (reg >= sizeof(sc->sc_pci_hpbcfg))
947 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
948 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
949 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
950 bus_space_read_2(sc->sc_pci_cfgt, bh,
951 PSYCHO_CONF_OFF(sc->sc_pci_secbus,
952 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
956 return (sc->sc_pci_hpbcfg[reg]);
958 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
960 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
964 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
967 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
971 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
975 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
979 panic("%s: bad width", __func__);
985 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
986 __func__, bus, slot, func, reg);
994 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
995 u_int reg, uint32_t val, int width)
997 struct psycho_softc *sc;
998 bus_space_handle_t bh;
1001 sc = device_get_softc(dev);
1002 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
1003 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
1006 offset = PSYCHO_CONF_OFF(bus, slot, func, reg);
1007 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
1010 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
1013 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
1016 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1019 panic("%s: bad width", __func__);
1025 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1027 struct psycho_softc *sc;
1028 struct ofw_pci_register reg;
1030 ofw_pci_intr_t pintr, mintr;
1031 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1033 sc = device_get_softc(bridge);
1035 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1036 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1040 * If this is outside of the range for an intpin, it's likely a full
1041 * INO, and no mapping is required at all; this happens on the U30,
1042 * where there's no interrupt map at the Psycho node. Fortunately,
1043 * there seem to be no INOs in the intpin range on this boxen, so
1044 * this easy heuristics will do.
1049 * Guess the INO; we always assume that this is a non-OBIO
1050 * device, and that pin is a "real" intpin number. Determine
1051 * the mapping register to be used by the slot number.
1052 * We only need to do this on E450s, it seems; here, the slot numbers
1053 * for bus A are one-based, while those for bus B seemingly have an
1054 * offset of 2 (hence the factor of 3 below).
1056 intrmap = PSR_PCIA0_INT_MAP +
1057 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
1058 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
1059 device_printf(bridge,
1060 "guessing interrupt %d for device %d.%d pin %d\n",
1061 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
1066 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1068 struct psycho_softc *sc;
1070 sc = device_get_softc(dev);
1072 case PCIB_IVAR_DOMAIN:
1073 *result = device_get_unit(dev);
1076 *result = sc->sc_pci_secbus;
1083 sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
1085 struct iommu_state *is = dt->dt_cookie;
1087 if ((map->dm_flags & DMF_LOADED) == 0)
1090 if ((op & BUS_DMASYNC_POSTREAD) != 0)
1091 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
1092 PSR_DMA_WRITE_SYNC);
1094 if ((op & BUS_DMASYNC_PREWRITE) != 0)
1099 psycho_intr_enable(void *arg)
1101 struct intr_vector *iv = arg;
1102 struct psycho_icarg *pica = iv->iv_icarg;
1104 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
1105 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1109 psycho_intr_disable(void *arg)
1111 struct intr_vector *iv = arg;
1112 struct psycho_icarg *pica = iv->iv_icarg;
1114 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
1118 psycho_intr_assign(void *arg)
1120 struct intr_vector *iv = arg;
1121 struct psycho_icarg *pica = iv->iv_icarg;
1123 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1124 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1128 psycho_intr_clear(void *arg)
1130 struct intr_vector *iv = arg;
1131 struct psycho_icarg *pica = iv->iv_icarg;
1133 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1137 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1138 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1141 struct psycho_softc *sc;
1144 sc = device_get_softc(dev);
1146 * Make sure the vector is fully specified and we registered
1147 * our interrupt controller for it.
1149 vec = rman_get_start(ires);
1150 if (INTIGN(vec) != sc->sc_ign ||
1151 intr_vectors[vec].iv_ic != &psycho_ic) {
1152 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1155 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1159 static struct resource *
1160 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1161 u_long start, u_long end, u_long count, u_int flags)
1163 struct psycho_softc *sc;
1164 struct resource *rv;
1167 bus_space_handle_t bh;
1168 int needactivate = flags & RF_ACTIVE;
1170 flags &= ~RF_ACTIVE;
1172 sc = device_get_softc(bus);
1173 if (type == SYS_RES_IRQ) {
1175 * XXX: Don't accept blank ranges for now, only single
1176 * interrupts. The other case should not happen with
1177 * the MI PCI code...
1178 * XXX: This may return a resource that is out of the
1179 * range that was specified. Is this correct...?
1182 panic("%s: XXX: interrupt range", __func__);
1183 start = end = INTMAP_VEC(sc->sc_ign, end);
1184 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
1185 type, rid, start, end, count, flags));
1188 case SYS_RES_MEMORY:
1189 rm = &sc->sc_pci_mem_rman;
1190 bt = sc->sc_pci_memt;
1191 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1193 case SYS_RES_IOPORT:
1194 rm = &sc->sc_pci_io_rman;
1195 bt = sc->sc_pci_iot;
1196 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1203 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1206 rman_set_rid(rv, *rid);
1207 bh += rman_get_start(rv);
1208 rman_set_bustag(rv, bt);
1209 rman_set_bushandle(rv, bh);
1212 if (bus_activate_resource(child, type, *rid, rv)) {
1213 rman_release_resource(rv);
1221 psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1227 if (type == SYS_RES_IRQ)
1228 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1230 if (type == SYS_RES_MEMORY) {
1232 * Need to memory-map the device space, as some drivers
1233 * depend on the virtual address being set and usable.
1235 error = sparc64_bus_mem_map(rman_get_bustag(r),
1236 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1239 rman_set_virtual(r, p);
1241 return (rman_activate_resource(r));
1245 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid,
1249 if (type == SYS_RES_IRQ)
1250 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1252 if (type == SYS_RES_MEMORY) {
1253 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1254 rman_set_virtual(r, NULL);
1256 return (rman_deactivate_resource(r));
1260 psycho_release_resource(device_t bus, device_t child, int type, int rid,
1265 if (type == SYS_RES_IRQ)
1266 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1268 if (rman_get_flags(r) & RF_ACTIVE) {
1269 error = bus_deactivate_resource(child, type, rid, r);
1273 return (rman_release_resource(r));
1276 static bus_dma_tag_t
1277 psycho_get_dma_tag(device_t bus, device_t child __unused)
1279 struct psycho_softc *sc;
1281 sc = device_get_softc(bus);
1282 return (sc->sc_pci_dmat);
1286 psycho_get_node(device_t bus, device_t child __unused)
1288 struct psycho_softc *sc;
1290 sc = device_get_softc(bus);
1291 /* We only have one child, the PCI bus, which needs our own node. */
1292 return (sc->sc_node);
1296 psycho_setup_device(device_t bus, device_t child)
1298 struct psycho_softc *sc;
1301 sc = device_get_softc(bus);
1303 * Revision 0 EBus bridges have a bug which prevents them from
1304 * working when bus parking is enabled.
1306 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1307 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1308 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1309 sizeof(rev)) > 0 && rev == 0)
1310 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1314 static bus_space_tag_t
1315 psycho_alloc_bus_tag(struct psycho_softc *sc, int type)
1319 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1322 panic("%s: out of memory", __func__);
1324 bt->bst_cookie = sc;
1325 bt->bst_parent = rman_get_bustag(sc->sc_mem_res);
1326 bt->bst_type = type;