2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
42 #include "opt_ofw_pci.h"
43 #include "opt_schizo.h"
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
56 #include <sys/timetc.h>
58 #include <dev/ofw/ofw_bus.h>
59 #include <dev/ofw/ofw_pci.h>
60 #include <dev/ofw/openfirm.h>
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/fsr.h>
66 #include <machine/iommureg.h>
67 #include <machine/iommuvar.h>
68 #include <machine/resource.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/schizoreg.h>
75 #include <sparc64/pci/schizovar.h>
79 static const struct schizo_desc *schizo_get_desc(device_t);
80 static void schizo_set_intr(struct schizo_softc *, u_int, u_int,
82 static driver_filter_t schizo_dma_sync_stub;
83 static driver_filter_t ichip_dma_sync_stub;
84 static void schizo_intr_enable(void *);
85 static void schizo_intr_disable(void *);
86 static void schizo_intr_assign(void *);
87 static void schizo_intr_clear(void *);
88 static int schizo_intr_register(struct schizo_softc *sc, u_int ino);
89 static int schizo_get_intrmap(struct schizo_softc *, u_int,
90 bus_addr_t *, bus_addr_t *);
91 static bus_space_tag_t schizo_alloc_bus_tag(struct schizo_softc *, int);
92 static timecounter_get_t schizo_get_timecount;
94 /* Interrupt handlers */
95 static driver_filter_t schizo_pci_bus;
96 static driver_filter_t schizo_ue;
97 static driver_filter_t schizo_ce;
98 static driver_filter_t schizo_host_bus;
99 static driver_filter_t schizo_cdma;
102 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t);
107 static device_probe_t schizo_probe;
108 static device_attach_t schizo_attach;
109 static bus_read_ivar_t schizo_read_ivar;
110 static bus_setup_intr_t schizo_setup_intr;
111 static bus_teardown_intr_t schizo_teardown_intr;
112 static bus_alloc_resource_t schizo_alloc_resource;
113 static bus_activate_resource_t schizo_activate_resource;
114 static bus_deactivate_resource_t schizo_deactivate_resource;
115 static bus_release_resource_t schizo_release_resource;
116 static bus_describe_intr_t schizo_describe_intr;
117 static bus_get_dma_tag_t schizo_get_dma_tag;
118 static pcib_maxslots_t schizo_maxslots;
119 static pcib_read_config_t schizo_read_config;
120 static pcib_write_config_t schizo_write_config;
121 static pcib_route_interrupt_t schizo_route_interrupt;
122 static ofw_bus_get_node_t schizo_get_node;
124 static device_method_t schizo_methods[] = {
125 /* Device interface */
126 DEVMETHOD(device_probe, schizo_probe),
127 DEVMETHOD(device_attach, schizo_attach),
128 DEVMETHOD(device_shutdown, bus_generic_shutdown),
129 DEVMETHOD(device_suspend, bus_generic_suspend),
130 DEVMETHOD(device_resume, bus_generic_resume),
133 DEVMETHOD(bus_print_child, bus_generic_print_child),
134 DEVMETHOD(bus_read_ivar, schizo_read_ivar),
135 DEVMETHOD(bus_setup_intr, schizo_setup_intr),
136 DEVMETHOD(bus_teardown_intr, schizo_teardown_intr),
137 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource),
138 DEVMETHOD(bus_activate_resource, schizo_activate_resource),
139 DEVMETHOD(bus_deactivate_resource, schizo_deactivate_resource),
140 DEVMETHOD(bus_release_resource, schizo_release_resource),
141 DEVMETHOD(bus_describe_intr, schizo_describe_intr),
142 DEVMETHOD(bus_get_dma_tag, schizo_get_dma_tag),
145 DEVMETHOD(pcib_maxslots, schizo_maxslots),
146 DEVMETHOD(pcib_read_config, schizo_read_config),
147 DEVMETHOD(pcib_write_config, schizo_write_config),
148 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt),
150 /* ofw_bus interface */
151 DEVMETHOD(ofw_bus_get_node, schizo_get_node),
156 static devclass_t schizo_devclass;
158 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods,
159 sizeof(struct schizo_softc));
160 DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0);
162 static SLIST_HEAD(, schizo_softc) schizo_softcs =
163 SLIST_HEAD_INITIALIZER(schizo_softcs);
165 static const struct intr_controller schizo_ic = {
172 struct schizo_icarg {
173 struct schizo_softc *sica_sc;
178 struct schizo_dma_sync {
179 struct schizo_softc *sds_sc;
180 driver_filter_t *sds_handler;
183 uint64_t sds_syncval;
184 device_t sds_ppb; /* farest PCI-PCI bridge */
185 uint8_t sds_bus; /* bus of farest PCI dev. */
186 uint8_t sds_slot; /* slot of farest PCI dev. */
187 uint8_t sds_func; /* func. of farest PCI dev. */
190 #define SCHIZO_PERF_CNT_QLTY 100
192 #define SCHIZO_SPC_READ_8(spc, sc, offs) \
193 bus_read_8((sc)->sc_mem_res[(spc)], (offs))
194 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \
195 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v))
197 #define SCHIZO_PCI_READ_8(sc, offs) \
198 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs))
199 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \
200 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v))
201 #define SCHIZO_CTRL_READ_8(sc, offs) \
202 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs))
203 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \
204 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v))
205 #define SCHIZO_PCICFG_READ_8(sc, offs) \
206 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs))
207 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \
208 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v))
209 #define SCHIZO_ICON_READ_8(sc, offs) \
210 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs))
211 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \
212 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v))
215 const char *sd_string;
220 static const struct schizo_desc const schizo_compats[] = {
221 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" },
222 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" },
226 static const struct schizo_desc *
227 schizo_get_desc(device_t dev)
229 const struct schizo_desc *desc;
232 compat = ofw_bus_get_compat(dev);
235 for (desc = schizo_compats; desc->sd_string != NULL; desc++)
236 if (strcmp(desc->sd_string, compat) == 0)
242 schizo_probe(device_t dev)
246 dtype = ofw_bus_get_type(dev);
247 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
248 schizo_get_desc(dev) != NULL) {
249 device_set_desc(dev, "Sun Host-PCI bridge");
256 schizo_attach(device_t dev)
258 struct ofw_pci_ranges *range;
259 const struct schizo_desc *desc;
260 struct schizo_softc *asc, *sc, *osc;
261 struct timecounter *tc;
262 uint64_t ino_bitmap, reg;
264 uint32_t prop, prop_array[2];
265 int i, j, mode, rid, tsbsize;
267 sc = device_get_softc(dev);
268 node = ofw_bus_get_node(dev);
269 desc = schizo_get_desc(dev);
270 mode = desc->sd_mode;
278 * The Schizo has three register banks:
279 * (0) per-PBM PCI configuration and status registers, but for bus B
280 * shared with the UPA64s interrupt mapping register banks
281 * (1) shared Schizo controller configuration and status registers
282 * (2) per-PBM PCI configuration space
284 * The Tomatillo has four register banks:
285 * (0) per-PBM PCI configuration and status registers
286 * (1) per-PBM Tomatillo controller configuration registers, but on
287 * machines having the `jbusppm' device shared with its Estar
288 * register bank for bus A
289 * (2) per-PBM PCI configuration space
290 * (3) per-PBM interrupt concentrator registers
292 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >>
294 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG);
297 sc->sc_mem_res[i] = bus_alloc_resource_any(dev,
298 SYS_RES_MEMORY, &rid,
299 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 &&
300 i == STX_PCI) || i == STX_CTRL)) ||
301 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 &&
302 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE);
303 if (sc->sc_mem_res[i] == NULL)
304 panic("%s: could not allocate register bank %d",
309 * Match other Schizos that are already configured against
310 * the controller base physical address. This will be the
311 * same for a pair of devices that share register space.
314 SLIST_FOREACH(asc, &schizo_softcs, sc_link) {
315 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) ==
316 rman_get_start(sc->sc_mem_res[STX_CTRL])) {
323 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
325 if (sc->sc_mtx == NULL)
326 panic("%s: could not malloc mutex", __func__);
327 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
329 if (sc->sc_mode != SCHIZO_MODE_SCZ)
330 panic("%s: no partner expected", __func__);
331 if (mtx_initialized(osc->sc_mtx) == 0)
332 panic("%s: mutex not initialized", __func__);
333 sc->sc_mtx = osc->sc_mtx;
336 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1)
337 panic("%s: could not determine IGN", __func__);
338 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) ==
340 panic("%s: could not determine version", __func__);
341 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
344 device_printf(dev, "%s, version %d, IGN %#x, bus %c, %dMHz\n",
345 desc->sd_name, sc->sc_ver, sc->sc_ign, 'A' + sc->sc_half,
348 /* Set up the PCI interrupt retry timer. */
350 device_printf(dev, "PCI IRT 0x%016llx\n", (unsigned long long)
351 SCHIZO_PCI_READ_8(sc, STX_PCI_INTR_RETRY_TIM));
353 SCHIZO_PCI_WRITE_8(sc, STX_PCI_INTR_RETRY_TIM, 5);
355 /* Set up the PCI control register. */
356 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
357 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN |
358 STX_PCI_CTRL_ERR_IEN | STX_PCI_CTRL_ARB_MASK;
359 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK);
360 if (OF_getproplen(node, "no-bus-parking") < 0)
361 reg |= STX_PCI_CTRL_ARB_PARK;
362 if (mode == SCHIZO_MODE_TOM) {
363 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL;
364 if (sc->sc_ver <= 1) /* revision <= 2.0 */
365 reg |= TOM_PCI_CTRL_DTO_IEN;
367 reg |= STX_PCI_CTRL_PTO;
370 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
371 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL),
372 (unsigned long long)reg);
374 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, reg);
376 /* Set up the PCI diagnostic register. */
377 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG);
378 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS |
379 STX_PCI_DIAG_INTRSYNC_DIS);
381 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
382 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
383 (unsigned long long)reg);
385 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
388 * On Tomatillo clear the I/O prefetch lengths (workaround for a
391 if (mode == SCHIZO_MODE_TOM)
392 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
393 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
394 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
397 * Hunt through all the interrupt mapping regs and register
398 * the interrupt controller for our interrupt vectors. We do
399 * this early in order to be able to catch stray interrupts.
400 * This is complicated by the fact that a pair of Schizo PBMs
403 i = OF_getprop(node, "ino-bitmap", (void *)prop_array,
406 panic("%s: could not get ino-bitmap", __func__);
407 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0];
408 for (i = 0; i <= STX_MAX_INO; i++) {
409 if ((ino_bitmap & (1ULL << i)) == 0)
411 if (i == STX_FB0_INO || i == STX_FB1_INO)
412 /* Leave for upa(4). */
414 j = schizo_intr_register(sc, i);
416 device_printf(dev, "could not register interrupt "
417 "controller for INO %d (%d)\n", i, j);
421 * Setup Safari/JBus performance counter 0 in bus cycle counting
422 * mode as timecounter. Unfortunately, this is broken with at
423 * least the version 4 Tomatillos found in Fire V120 and Blade
424 * 1500, which apparently actually count some different event at
425 * ~0.5 and 3MHz respectively instead (also when running in full
426 * power mode). Besides, one counter seems to be shared by a
427 * "pair" of Tomatillos, too.
429 if (sc->sc_half == 0) {
430 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_PERF,
431 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) |
432 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT));
433 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO);
435 panic("%s: could not malloc timecounter", __func__);
436 tc->tc_get_timecount = schizo_get_timecount;
437 tc->tc_poll_pps = NULL;
438 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK;
439 if (OF_getprop(OF_peer(0), "clock-frequency", &prop,
441 panic("%s: could not determine clock frequency",
443 tc->tc_frequency = prop;
444 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF);
445 if (mode == SCHIZO_MODE_SCZ)
446 tc->tc_quality = SCHIZO_PERF_CNT_QLTY;
448 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY;
454 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have
455 * one per PBM. Schizo and XMITS additionally have a streaming
456 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's
457 * affected by several errata and basically unusable though.
459 sc->sc_is.is_flags = IOMMU_PRESERVE_PROM;
460 sc->sc_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS);
461 sc->sc_is.is_sb[0] = sc->sc_is.is_sb[1] = 0;
462 if (OF_getproplen(node, "no-streaming-cache") < 0 &&
463 !(sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver < 5))
464 sc->sc_is.is_sb[0] = STX_PCI_STRBUF;
467 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \
471 i = OF_getprop(node, "virtual-dma", (void *)prop_array,
473 if (i == -1 || i != sizeof(prop_array))
474 schizo_iommu_init(sc, 7, -1);
476 switch (prop_array[1]) {
486 panic("%s: unsupported DVMA size 0x%x",
487 __func__, prop_array[1]);
490 schizo_iommu_init(sc, tsbsize, prop_array[0]);
495 /* Initialize memory and I/O rmans. */
496 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY;
497 sc->sc_pci_io_rman.rm_descr = "Schizo PCI I/O Ports";
498 if (rman_init(&sc->sc_pci_io_rman) != 0 ||
499 rman_manage_region(&sc->sc_pci_io_rman, 0, STX_IO_SIZE) != 0)
500 panic("%s: failed to set up I/O rman", __func__);
501 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY;
502 sc->sc_pci_mem_rman.rm_descr = "Schizo PCI Memory";
503 if (rman_init(&sc->sc_pci_mem_rman) != 0 ||
504 rman_manage_region(&sc->sc_pci_mem_rman, 0, STX_MEM_SIZE) != 0)
505 panic("%s: failed to set up memory rman", __func__);
507 i = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range);
509 * Make sure that the expected ranges are present. The
510 * OFW_PCI_CS_MEM64 one is not currently used though.
513 panic("%s: unsupported number of ranges", __func__);
515 * Find the addresses of the various bus spaces.
516 * There should not be multiple ones of one kind.
517 * The physical start addresses of the ranges are the configuration,
518 * memory and I/O handles.
520 for (i = 0; i < STX_NRANGE; i++) {
521 j = OFW_PCI_RANGE_CS(&range[i]);
522 if (sc->sc_pci_bh[j] != 0)
523 panic("%s: duplicate range for space %d",
525 sc->sc_pci_bh[j] = OFW_PCI_RANGE_PHYS(&range[i]);
527 free(range, M_OFWPROP);
529 /* Register the softc, this is needed for paired Schizos. */
530 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link);
532 /* Allocate our tags. */
533 sc->sc_pci_memt = schizo_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
534 sc->sc_pci_iot = schizo_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
535 sc->sc_pci_cfgt = schizo_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE);
536 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
537 sc->sc_is.is_pmaxaddr, ~0, NULL, NULL, sc->sc_is.is_pmaxaddr,
538 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
539 panic("%s: bus_dma_tag_create failed", __func__);
540 /* Customize the tag. */
541 sc->sc_pci_dmat->dt_cookie = &sc->sc_is;
542 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods;
545 * Get the bus range from the firmware.
546 * NB: Tomatillos don't support PCI bus reenumeration.
548 i = OF_getprop(node, "bus-range", (void *)prop_array,
551 panic("%s: could not get bus-range", __func__);
552 if (i != sizeof(prop_array))
553 panic("%s: broken bus-range (%d)", __func__, i);
554 sc->sc_pci_secbus = prop_array[0];
555 sc->sc_pci_subbus = prop_array[1];
557 device_printf(dev, "bus range %u to %u; PCI bus %d\n",
558 sc->sc_pci_secbus, sc->sc_pci_subbus, sc->sc_pci_secbus);
560 /* Clear any pending PCI error bits. */
561 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
562 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
563 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2), 2);
564 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL,
565 SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL));
566 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR,
567 SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR));
570 * Establish handlers for interesting interrupts...
571 * Someone at Sun clearly was smoking crack; with Schizos PCI
572 * bus error interrupts for one PBM can be routed to the other
573 * PBM though we obviously need to use the softc of the former
574 * as the argument for the interrupt handler and the softc of
575 * the latter as the argument for the interrupt controller.
577 if (sc->sc_half == 0) {
578 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 ||
579 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
580 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)->
583 * We are the driver for PBM A and either also
584 * registered the interrupt controller for us or
585 * the driver for PBM B has probed first and
586 * registered it for us.
588 schizo_set_intr(sc, 0, STX_PCIERR_A_INO,
590 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 &&
593 * We are the driver for PBM A but registered
594 * the interrupt controller for PBM B, i.e. the
595 * driver for PBM B attached first but couldn't
596 * set up a handler for PBM B.
598 schizo_set_intr(osc, 0, STX_PCIERR_B_INO,
601 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 ||
602 (osc != NULL && ((struct schizo_icarg *)intr_vectors[
603 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)->
606 * We are the driver for PBM B and either also
607 * registered the interrupt controller for us or
608 * the driver for PBM A has probed first and
609 * registered it for us.
611 schizo_set_intr(sc, 0, STX_PCIERR_B_INO,
613 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 &&
616 * We are the driver for PBM B but registered
617 * the interrupt controller for PBM A, i.e. the
618 * driver for PBM A attached first but couldn't
619 * set up a handler for PBM A.
621 schizo_set_intr(osc, 0, STX_PCIERR_A_INO,
624 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0)
625 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue);
626 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0)
627 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce);
628 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0)
629 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus);
632 * According to the Schizo Errata I-13, consistent DMA flushing/
633 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges,
634 * so we can't use it and need to live with the consequences. With
635 * Schizo version >= 5, CDMA flushing/syncing is usable but requires
636 * the workaround described in Schizo Errata I-23. With Tomatillo
637 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo
638 * version <= 4 (i.e. revision <= 2.3) bridges additionally require
639 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though.
641 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) ||
642 sc->sc_mode == SCHIZO_MODE_TOM ||
643 sc->sc_mode == SCHIZO_MODE_XMS) {
644 sc->sc_flags |= SCHIZO_FLAGS_CDMA;
645 if (sc->sc_mode == SCHIZO_MODE_SCZ) {
646 sc->sc_cdma_state = SCHIZO_CDMA_STATE_DONE;
648 * Some firmware versions include the CDMA interrupt
649 * at RID 4 but most don't. With the latter we add
650 * it ourselves at the spare RID 5.
652 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ,
654 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) {
655 (void)schizo_get_intrmap(sc, i, NULL,
657 schizo_set_intr(sc, 4, i, schizo_cdma);
659 i = STX_CDMA_A_INO + sc->sc_half;
660 if (bus_set_resource(dev, SYS_RES_IRQ, 5,
661 INTMAP_VEC(sc->sc_ign, i), 1) != 0)
662 panic("%s: failed to add CDMA "
663 "interrupt", __func__);
664 j = schizo_intr_register(sc, i);
666 panic("%s: could not register "
667 "interrupt controller for CDMA "
668 "(%d)", __func__, j);
669 (void)schizo_get_intrmap(sc, i, NULL,
671 schizo_set_intr(sc, 5, i, schizo_cdma);
674 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4)
675 sc->sc_flags |= SCHIZO_FLAGS_BSWAR;
679 * Set the latency timer register as this isn't always done by the
682 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
683 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
685 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
687 device_add_child(dev, "pci", -1);
688 return (bus_generic_attach(dev));
692 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
693 driver_filter_t handler)
699 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
700 SYS_RES_IRQ, &rid, RF_ACTIVE);
701 if (sc->sc_irq_res[index] == NULL ||
702 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino ||
703 INTIGN(vec) != sc->sc_ign ||
704 intr_vectors[vec].iv_ic != &schizo_ic ||
705 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
706 INTR_TYPE_MISC | INTR_FAST, handler, NULL, sc,
707 &sc->sc_ihand[index]) != 0)
708 panic("%s: failed to set up interrupt %d", __func__, index);
712 schizo_intr_register(struct schizo_softc *sc, u_int ino)
714 struct schizo_icarg *sica;
715 bus_addr_t intrclr, intrmap;
718 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0)
720 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT);
724 sica->sica_map = intrmap;
725 sica->sica_clr = intrclr;
727 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n",
728 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap),
731 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino),
734 free(sica, M_DEVBUF);
739 schizo_get_intrmap(struct schizo_softc *sc, u_int ino,
740 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr)
742 bus_addr_t intrclr, intrmap;
746 * XXX we only look for INOs rather than INRs since the firmware
747 * may not provide the IGN and the IGN is constant for all devices
748 * on that PCI controller.
751 if (ino > STX_MAX_INO) {
752 device_printf(sc->sc_dev, "out of range INO %d requested\n",
757 intrmap = STX_PCI_IMAP_BASE + (ino << 3);
758 intrclr = STX_PCI_ICLR_BASE + (ino << 3);
759 mr = SCHIZO_PCI_READ_8(sc, intrmap);
760 if (INTINO(mr) != ino) {
761 device_printf(sc->sc_dev,
762 "interrupt map entry does not match INO (%d != %d)\n",
763 (int)INTINO(mr), ino);
767 if (intrmapptr != NULL)
768 *intrmapptr = intrmap;
769 if (intrclrptr != NULL)
770 *intrclrptr = intrclr;
778 schizo_pci_bus(void *arg)
780 struct schizo_softc *sc = arg;
781 uint64_t afar, afsr, csr, iommu;
784 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
785 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
786 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
787 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
788 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
789 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
790 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) {
791 if ((iommu & TOM_PCI_IOMMU_ERR) == 0)
794 /* These are non-fatal if target abort was signaled. */
795 if ((status & PCIM_STATUS_STABORT) != 0 &&
796 ((iommu & TOM_PCI_IOMMU_ERRMASK) ==
797 TOM_PCI_IOMMU_INVALID_ERR ||
798 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 ||
799 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) {
800 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
805 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
806 "IOMMU %#llx STATUS %#llx", device_get_name(sc->sc_dev),
807 'A' + sc->sc_half, (unsigned long long)afar,
808 (unsigned long long)afsr, (unsigned long long)csr,
809 (unsigned long long)iommu, (unsigned long long)status);
813 device_printf(sc->sc_dev,
814 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
815 "STATUS %#llx", 'A' + sc->sc_half,
816 (unsigned long long)afar, (unsigned long long)afsr,
817 (unsigned long long)csr, (unsigned long long)status);
818 /* Clear the error bits that we caught. */
819 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
820 STX_CS_FUNC, PCIR_STATUS, status, 2);
821 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
822 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
823 return (FILTER_HANDLED);
829 struct schizo_softc *sc = arg;
833 mtx_lock_spin(sc->sc_mtx);
834 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
835 for (i = 0; i < 1000; i++)
836 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
837 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
839 mtx_unlock_spin(sc->sc_mtx);
840 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
841 device_get_name(sc->sc_dev), (unsigned long long)afar,
842 (unsigned long long)afsr);
843 return (FILTER_HANDLED);
849 struct schizo_softc *sc = arg;
853 mtx_lock_spin(sc->sc_mtx);
854 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
855 for (i = 0; i < 1000; i++)
856 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
857 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
859 device_printf(sc->sc_dev,
860 "correctable DMA error AFAR %#llx AFSR %#llx\n",
861 (unsigned long long)afar, (unsigned long long)afsr);
862 /* Clear the error bits that we caught. */
863 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
864 mtx_unlock_spin(sc->sc_mtx);
865 return (FILTER_HANDLED);
869 schizo_host_bus(void *arg)
871 struct schizo_softc *sc = arg;
874 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG);
875 panic("%s: %s error %#llx", device_get_name(sc->sc_dev),
876 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari",
877 (unsigned long long)errlog);
878 return (FILTER_HANDLED);
882 schizo_cdma(void *arg)
884 struct schizo_softc *sc = arg;
886 atomic_store_rel_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_DONE);
887 return (FILTER_HANDLED);
891 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase)
894 /* Punch in our copies. */
895 sc->sc_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
896 sc->sc_is.is_bushandle = rman_get_bushandle(sc->sc_mem_res[STX_PCI]);
897 sc->sc_is.is_iommu = STX_PCI_IOMMU;
898 sc->sc_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG;
899 sc->sc_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG;
900 sc->sc_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG;
901 sc->sc_is.is_dva = STX_PCI_IOMMU_SVADIAG;
902 sc->sc_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG;
904 iommu_init(device_get_nameunit(sc->sc_dev), &sc->sc_is, tsbsize,
909 schizo_maxslots(device_t dev)
911 struct schizo_softc *sc;
913 sc = device_get_softc(dev);
914 if (sc->sc_mode == SCHIZO_MODE_SCZ)
915 return (sc->sc_half == 0 ? 4 : 6);
917 /* XXX: is this correct? */
918 return (PCI_SLOTMAX);
922 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
925 struct schizo_softc *sc;
926 bus_space_handle_t bh;
933 sc = device_get_softc(dev);
934 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
935 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
939 * The Schizo bridges contain a dupe of their header at 0x80.
941 if (sc->sc_mode == SCHIZO_MODE_SCZ && bus == sc->sc_pci_secbus &&
942 slot == STX_CS_DEVICE && func == STX_CS_FUNC &&
946 offset = STX_CONF_OFF(bus, slot, func, reg);
947 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
950 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte);
954 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt);
958 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
962 panic("%s: bad width", __func__);
968 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
969 __func__, bus, slot, func, reg);
977 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func,
978 u_int reg, uint32_t val, int width)
980 struct schizo_softc *sc;
981 bus_space_handle_t bh;
984 sc = device_get_softc(dev);
985 if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
986 slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCI_REGMAX)
989 offset = STX_CONF_OFF(bus, slot, func, reg);
990 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
993 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
996 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
999 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1002 panic("%s: bad width", __func__);
1008 schizo_route_interrupt(device_t bridge, device_t dev, int pin)
1010 struct schizo_softc *sc;
1011 struct ofw_pci_register reg;
1012 ofw_pci_intr_t pintr, mintr;
1013 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)];
1015 sc = device_get_softc(bridge);
1017 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1018 ®, sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr),
1022 device_printf(bridge, "could not route pin %d for device %d.%d\n",
1023 pin, pci_get_slot(dev), pci_get_function(dev));
1024 return (PCI_INVALID_IRQ);
1028 schizo_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1030 struct schizo_softc *sc;
1032 sc = device_get_softc(dev);
1034 case PCIB_IVAR_DOMAIN:
1035 *result = device_get_unit(dev);
1038 *result = sc->sc_pci_secbus;
1045 schizo_dma_sync_stub(void *arg)
1047 struct timeval cur, end;
1048 struct schizo_dma_sync *sds = arg;
1049 struct schizo_softc *sc = sds->sds_sc;
1052 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot,
1053 sds->sds_func, PCIR_VENDOR, 2);
1054 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state,
1055 SCHIZO_CDMA_STATE_DONE, SCHIZO_CDMA_STATE_PENDING) == 0;)
1057 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1);
1061 timevaladd(&end, &cur);
1062 for (; (state = atomic_load_32(&sc->sc_cdma_state)) !=
1063 SCHIZO_CDMA_STATE_DONE && timevalcmp(&cur, &end, <=);)
1065 if (state != SCHIZO_CDMA_STATE_DONE)
1066 panic("%s: DMA does not sync", __func__);
1067 return (sds->sds_handler(sds->sds_arg));
1070 #define VIS_BLOCKSIZE 64
1073 ichip_dma_sync_stub(void *arg)
1075 static u_char buf[VIS_BLOCKSIZE] __aligned(VIS_BLOCKSIZE);
1076 struct timeval cur, end;
1077 struct schizo_dma_sync *sds = arg;
1078 struct schizo_softc *sc = sds->sds_sc;
1081 (void)PCIB_READ_CONFIG(sds->sds_ppb, sds->sds_bus, sds->sds_slot,
1082 sds->sds_func, PCIR_VENDOR, 2);
1083 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, sds->sds_syncval);
1087 timevaladd(&end, &cur);
1088 for (; ((reg = SCHIZO_PCI_READ_8(sc, TOMXMS_PCI_DMA_SYNC_PEND)) &
1089 sds->sds_syncval) != 0 && timevalcmp(&cur, &end, <=);)
1091 if ((reg & sds->sds_syncval) != 0)
1092 panic("%s: DMA does not sync", __func__);
1094 if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) {
1097 wr(fprs, reg | FPRS_FEF, 0);
1098 __asm __volatile("stda %%f0, [%0] %1"
1099 : : "r" (buf), "n" (ASI_BLK_COMMIT_S));
1104 return (sds->sds_handler(sds->sds_arg));
1108 schizo_intr_enable(void *arg)
1110 struct intr_vector *iv = arg;
1111 struct schizo_icarg *sica = iv->iv_icarg;
1113 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map,
1114 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
1118 schizo_intr_disable(void *arg)
1120 struct intr_vector *iv = arg;
1121 struct schizo_icarg *sica = iv->iv_icarg;
1123 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec);
1127 schizo_intr_assign(void *arg)
1129 struct intr_vector *iv = arg;
1130 struct schizo_icarg *sica = iv->iv_icarg;
1132 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID(
1133 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid));
1137 schizo_intr_clear(void *arg)
1139 struct intr_vector *iv = arg;
1140 struct schizo_icarg *sica = iv->iv_icarg;
1142 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, 0);
1146 schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
1147 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1150 devclass_t pci_devclass;
1151 device_t cdev, pdev, pcidev;
1152 struct schizo_dma_sync *sds;
1153 struct schizo_softc *sc;
1157 sc = device_get_softc(dev);
1159 * Make sure the vector is fully specified.
1161 vec = rman_get_start(ires);
1162 if (INTIGN(vec) != sc->sc_ign) {
1163 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1167 if (intr_vectors[vec].iv_ic == &schizo_ic) {
1169 * Ensure we use the right softc in case the interrupt
1170 * is routed to our companion PBM for some odd reason.
1172 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)->
1174 } else if (intr_vectors[vec].iv_ic == NULL) {
1176 * Work around broken firmware which misses entries in
1179 error = schizo_intr_register(sc, INTINO(vec));
1181 device_printf(dev, "could not register interrupt "
1182 "controller for vector 0x%lx (%d)\n", vec, error);
1186 device_printf(dev, "belatedly registered as "
1187 "interrupt controller for vector 0x%lx\n", vec);
1190 "invalid interrupt controller for vector 0x%lx\n", vec);
1195 * Install a a wrapper for CDMA flushing/syncing for devices
1196 * behind PCI-PCI bridges if possible.
1200 pci_devclass = devclass_find("pci");
1201 for (cdev = child; cdev != dev; cdev = pdev) {
1202 pdev = device_get_parent(cdev);
1203 if (pcidev == NULL) {
1204 if (device_get_devclass(pdev) != pci_devclass)
1209 if (pci_get_class(cdev) == PCIC_BRIDGE &&
1210 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI)
1213 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) {
1214 sds = malloc(sizeof(*sds), M_DEVBUF, M_NOWAIT | M_ZERO);
1217 if (found != 0 && pcidev != NULL) {
1221 device_get_parent(device_get_parent(pcidev));
1222 sds->sds_bus = pci_get_bus(pcidev);
1223 sds->sds_slot = pci_get_slot(pcidev);
1224 sds->sds_func = pci_get_function(pcidev);
1225 sds->sds_syncval = 1ULL << INTINO(vec);
1227 device_printf(dev, "installed DMA sync "
1228 "wrapper for device %d.%d on bus %d\n",
1229 sds->sds_slot, sds->sds_func,
1232 #define DMA_SYNC_STUB \
1233 (sc->sc_mode == SCHIZO_MODE_SCZ ? schizo_dma_sync_stub : \
1234 ichip_dma_sync_stub)
1237 sds->sds_handler = filt;
1238 error = bus_generic_setup_intr(dev, child,
1239 ires, flags, DMA_SYNC_STUB, intr, sds,
1242 sds->sds_handler = (driver_filter_t *)intr;
1243 error = bus_generic_setup_intr(dev, child,
1244 ires, flags, filt, (driver_intr_t *)
1245 DMA_SYNC_STUB, sds, cookiep);
1248 #undef DMA_SYNC_STUB
1251 error = bus_generic_setup_intr(dev, child, ires,
1252 flags, filt, intr, arg, cookiep);
1254 free(sds, M_DEVBUF);
1257 sds->sds_cookie = *cookiep;
1260 } else if (found != 0)
1261 device_printf(dev, "WARNING: using devices behind PCI-PCI "
1262 "bridges may cause data corruption\n");
1263 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1268 schizo_teardown_intr(device_t dev, device_t child, struct resource *vec,
1271 struct schizo_dma_sync *sds;
1272 struct schizo_softc *sc;
1275 sc = device_get_softc(dev);
1276 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0) {
1278 error = bus_generic_teardown_intr(dev, child, vec,
1281 free(sds, M_DEVBUF);
1284 return (bus_generic_teardown_intr(dev, child, vec, cookie));
1288 schizo_describe_intr(device_t dev, device_t child, struct resource *vec,
1289 void *cookie, const char *descr)
1291 struct schizo_softc *sc;
1293 sc = device_get_softc(dev);
1294 if ((sc->sc_flags & SCHIZO_FLAGS_CDMA) != 0)
1295 cookie = ((struct schizo_dma_sync *)cookie)->sds_cookie;
1296 return (bus_generic_describe_intr(dev, child, vec, cookie, descr));
1299 static struct resource *
1300 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
1301 u_long start, u_long end, u_long count, u_int flags)
1303 struct schizo_softc *sc;
1304 struct resource *rv;
1307 bus_space_handle_t bh;
1308 int needactivate = flags & RF_ACTIVE;
1310 flags &= ~RF_ACTIVE;
1312 sc = device_get_softc(bus);
1313 if (type == SYS_RES_IRQ) {
1315 * XXX: Don't accept blank ranges for now, only single
1316 * interrupts. The other case should not happen with
1317 * the MI PCI code...
1318 * XXX: This may return a resource that is out of the
1319 * range that was specified. Is this correct...?
1322 panic("%s: XXX: interrupt range", __func__);
1323 start = end = INTMAP_VEC(sc->sc_ign, end);
1324 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
1325 type, rid, start, end, count, flags));
1328 case SYS_RES_MEMORY:
1329 rm = &sc->sc_pci_mem_rman;
1330 bt = sc->sc_pci_memt;
1331 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32];
1333 case SYS_RES_IOPORT:
1334 rm = &sc->sc_pci_io_rman;
1335 bt = sc->sc_pci_iot;
1336 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1343 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1346 rman_set_rid(rv, *rid);
1347 bh += rman_get_start(rv);
1348 rman_set_bustag(rv, bt);
1349 rman_set_bushandle(rv, bh);
1352 if (bus_activate_resource(child, type, *rid, rv)) {
1353 rman_release_resource(rv);
1361 schizo_activate_resource(device_t bus, device_t child, int type, int rid,
1367 if (type == SYS_RES_IRQ)
1368 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
1370 if (type == SYS_RES_MEMORY) {
1372 * Need to memory-map the device space, as some drivers
1373 * depend on the virtual address being set and usable.
1375 error = sparc64_bus_mem_map(rman_get_bustag(r),
1376 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p);
1379 rman_set_virtual(r, p);
1381 return (rman_activate_resource(r));
1385 schizo_deactivate_resource(device_t bus, device_t child, int type, int rid,
1389 if (type == SYS_RES_IRQ)
1390 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
1392 if (type == SYS_RES_MEMORY) {
1393 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r));
1394 rman_set_virtual(r, NULL);
1396 return (rman_deactivate_resource(r));
1400 schizo_release_resource(device_t bus, device_t child, int type, int rid,
1405 if (type == SYS_RES_IRQ)
1406 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
1408 if (rman_get_flags(r) & RF_ACTIVE) {
1409 error = bus_deactivate_resource(child, type, rid, r);
1413 return (rman_release_resource(r));
1416 static bus_dma_tag_t
1417 schizo_get_dma_tag(device_t bus, device_t child)
1419 struct schizo_softc *sc;
1421 sc = device_get_softc(bus);
1422 return (sc->sc_pci_dmat);
1426 schizo_get_node(device_t bus, device_t dev)
1428 struct schizo_softc *sc;
1430 sc = device_get_softc(bus);
1431 /* We only have one child, the PCI bus, which needs our own node. */
1432 return (sc->sc_node);
1435 static bus_space_tag_t
1436 schizo_alloc_bus_tag(struct schizo_softc *sc, int type)
1440 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF,
1443 panic("%s: out of memory", __func__);
1445 bt->bst_cookie = sc;
1446 bt->bst_parent = rman_get_bustag(sc->sc_mem_res[STX_PCI]);
1447 bt->bst_type = type;
1452 schizo_get_timecount(struct timecounter *tc)
1454 struct schizo_softc *sc;
1457 return (SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) &
1458 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT));