2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (c) 2001 Jake Burkholder.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
58 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
64 #include <sys/param.h>
65 #include <sys/systm.h>
67 #include <sys/errno.h>
68 #include <sys/interrupt.h>
69 #include <sys/kernel.h>
71 #include <sys/mutex.h>
77 #include <machine/frame.h>
78 #include <machine/intr_machdep.h>
80 #define MAX_STRAY_LOG 5
82 CTASSERT((1 << IV_SHIFT) == sizeof(struct intr_vector));
84 ih_func_t *intr_handlers[PIL_MAX];
85 uint16_t pil_countp[PIL_MAX];
86 static uint16_t pil_stray_count[PIL_MAX];
88 struct intr_vector intr_vectors[IV_MAX];
89 uint16_t intr_countp[IV_MAX];
90 static uint16_t intr_stray_count[IV_MAX];
92 static const char *const pil_names[] = {
95 "preempt", /* PIL_PREEMPT */
96 "ithrd", /* PIL_ITHREAD */
97 "rndzvs", /* PIL_RENDEZVOUS */
99 "stray", "stray", "stray", "stray", "stray",
100 "filter", /* PIL_FILTER */
101 "bridge", /* PIL_BRIDGE */
102 "stop", /* PIL_STOP */
103 "tick", /* PIL_TICK */
106 /* protect the intr_vectors table */
107 static struct sx intr_table_lock;
108 /* protect intrcnt_index */
109 static struct mtx intrcnt_lock;
112 static int assign_cpu;
114 static void intr_assign_next_cpu(struct intr_vector *iv);
115 static void intr_shuffle_irqs(void *arg __unused);
118 static int intr_assign_cpu(void *arg, u_char cpu);
119 static void intr_execute_handlers(void *);
120 static void intr_stray_level(struct trapframe *);
121 static void intr_stray_vector(void *);
122 static int intrcnt_setname(const char *, int);
123 static void intrcnt_updatename(int, const char *, int);
126 intrcnt_updatename(int vec, const char *name, int ispil)
128 static int intrcnt_index, stray_pil_index, stray_vec_index;
131 mtx_lock_spin(&intrcnt_lock);
132 if (intrnames[0] == '\0') {
135 printf("initalizing intr_countp\n");
136 intrcnt_setname("???", intrcnt_index++);
138 stray_vec_index = intrcnt_index++;
139 intrcnt_setname("stray", stray_vec_index);
140 for (name_index = 0; name_index < IV_MAX; name_index++)
141 intr_countp[name_index] = stray_vec_index;
143 stray_pil_index = intrcnt_index++;
144 intrcnt_setname("pil", stray_pil_index);
145 for (name_index = 0; name_index < PIL_MAX; name_index++)
146 pil_countp[name_index] = stray_pil_index;
152 if (!ispil && intr_countp[vec] != stray_vec_index)
153 name_index = intr_countp[vec];
154 else if (ispil && pil_countp[vec] != stray_pil_index)
155 name_index = pil_countp[vec];
157 name_index = intrcnt_index++;
159 if (intrcnt_setname(name, name_index))
163 intr_countp[vec] = name_index;
165 pil_countp[vec] = name_index;
166 mtx_unlock_spin(&intrcnt_lock);
170 intrcnt_setname(const char *name, int index)
173 if (intrnames + (MAXCOMLEN + 1) * index >= eintrnames)
175 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
181 intr_setup(int pri, ih_func_t *ihf, int vec, iv_func_t *ivf, void *iva)
183 char pilname[MAXCOMLEN + 1];
188 intr_vectors[vec].iv_func = ivf;
189 intr_vectors[vec].iv_arg = iva;
190 intr_vectors[vec].iv_pri = pri;
191 intr_vectors[vec].iv_vec = vec;
193 intr_handlers[pri] = ihf;
195 snprintf(pilname, MAXCOMLEN + 1, "pil%d: %s", pri, pil_names[pri]);
196 intrcnt_updatename(pri, pilname, 1);
200 intr_stray_level(struct trapframe *tf)
204 level = tf->tf_level;
205 if (pil_stray_count[level] < MAX_STRAY_LOG) {
206 printf("stray level interrupt %ld\n", level);
207 pil_stray_count[level]++;
208 if (pil_stray_count[level] >= MAX_STRAY_LOG)
209 printf("got %d stray level interrupt %ld's: not "
210 "logging anymore\n", MAX_STRAY_LOG, level);
215 intr_stray_vector(void *cookie)
217 struct intr_vector *iv;
222 if (intr_stray_count[vec] < MAX_STRAY_LOG) {
223 printf("stray vector interrupt %d\n", vec);
224 intr_stray_count[vec]++;
225 if (intr_stray_count[vec] >= MAX_STRAY_LOG)
226 printf("got %d stray vector interrupt %d's: not "
227 "logging anymore\n", MAX_STRAY_LOG, vec);
236 /* Mark all interrupts as being stray. */
237 for (i = 0; i < PIL_MAX; i++)
238 intr_handlers[i] = intr_stray_level;
239 for (i = 0; i < IV_MAX; i++) {
240 intr_vectors[i].iv_func = intr_stray_vector;
241 intr_vectors[i].iv_arg = &intr_vectors[i];
242 intr_vectors[i].iv_pri = PIL_LOW;
243 intr_vectors[i].iv_vec = i;
244 intr_vectors[i].iv_refcnt = 0;
246 intr_handlers[PIL_LOW] = intr_fast;
253 sx_init(&intr_table_lock, "intr sources");
254 mtx_init(&intrcnt_lock, "intrcnt", NULL, MTX_SPIN);
258 intr_assign_cpu(void *arg, u_char cpu)
262 struct intr_vector *iv;
265 * Don't do anything during early boot. We will pick up the
266 * assignment once the APs are started.
268 if (assign_cpu && cpu != NOCPU) {
273 sx_xlock(&intr_table_lock);
274 iv->iv_mid = pc->pc_mid;
275 iv->iv_ic->ic_assign(iv);
276 sx_xunlock(&intr_table_lock);
285 intr_execute_handlers(void *cookie)
287 struct intr_vector *iv;
290 if (__predict_false(intr_event_handle(iv->iv_event, NULL) != 0))
291 intr_stray_vector(iv);
295 intr_controller_register(int vec, const struct intr_controller *ic,
298 struct intr_event *ie;
299 struct intr_vector *iv;
302 if (vec < 0 || vec >= IV_MAX)
304 sx_xlock(&intr_table_lock);
305 iv = &intr_vectors[vec];
307 sx_xunlock(&intr_table_lock);
310 error = intr_event_create(&ie, iv, 0, vec, NULL, ic->ic_clear,
311 ic->ic_clear, intr_assign_cpu, "vec%d:", vec);
314 sx_xlock(&intr_table_lock);
315 if (iv->iv_event != NULL) {
316 sx_xunlock(&intr_table_lock);
317 intr_event_destroy(ie);
321 iv->iv_icarg = icarg;
323 iv->iv_mid = PCPU_GET(mid);
324 sx_xunlock(&intr_table_lock);
329 inthand_add(const char *name, int vec, driver_filter_t *filt,
330 driver_intr_t *handler, void *arg, int flags, void **cookiep)
332 const struct intr_controller *ic;
333 struct intr_event *ie;
334 struct intr_handler *ih;
335 struct intr_vector *iv;
338 if (vec < 0 || vec >= IV_MAX)
341 * INTR_BRIDGE filters/handlers are special purpose only, allowing
342 * them to be shared just would complicate things unnecessarily.
344 if ((flags & INTR_BRIDGE) != 0 && (flags & INTR_EXCL) == 0)
346 sx_xlock(&intr_table_lock);
347 iv = &intr_vectors[vec];
350 sx_xunlock(&intr_table_lock);
351 if (ic == NULL || ie == NULL)
353 error = intr_event_add_handler(ie, name, filt, handler, arg,
354 intr_priority(flags), flags, cookiep);
357 sx_xlock(&intr_table_lock);
358 /* Disable the interrupt while we fiddle with it. */
361 if (iv->iv_refcnt == 1)
362 intr_setup((flags & INTR_BRIDGE) != 0 ? PIL_BRIDGE :
363 filt != NULL ? PIL_FILTER : PIL_ITHREAD, intr_fast,
364 vec, intr_execute_handlers, iv);
365 else if (filt != NULL) {
367 * Check if we need to upgrade from PIL_ITHREAD to PIL_FILTER.
368 * Given that apart from the on-board SCCs and UARTs shared
369 * interrupts are rather uncommon on sparc64 this sould be
370 * pretty rare in practice.
373 TAILQ_FOREACH(ih, &ie->ie_handlers, ih_next) {
374 if (ih->ih_filter != NULL && ih->ih_filter != filt) {
380 intr_setup(PIL_FILTER, intr_fast, vec,
381 intr_execute_handlers, iv);
383 intr_stray_count[vec] = 0;
384 intrcnt_updatename(vec, ie->ie_fullname, 0);
387 intr_assign_next_cpu(iv);
390 /* Ensure the interrupt is cleared, it might have triggered before. */
391 if (ic->ic_clear != NULL)
393 sx_xunlock(&intr_table_lock);
398 inthand_remove(int vec, void *cookie)
400 struct intr_vector *iv;
403 if (vec < 0 || vec >= IV_MAX)
405 error = intr_event_remove_handler(cookie);
408 * XXX: maybe this should be done regardless of whether
409 * intr_event_remove_handler() succeeded?
411 sx_xlock(&intr_table_lock);
412 iv = &intr_vectors[vec];
414 if (iv->iv_refcnt == 0) {
416 * Don't disable the interrupt for now, so that
417 * stray interrupts get detected...
419 intr_setup(PIL_LOW, intr_fast, vec,
420 intr_stray_vector, iv);
422 sx_xunlock(&intr_table_lock);
427 /* Add a description to an active interrupt handler. */
429 intr_describe(int vec, void *ih, const char *descr)
431 struct intr_vector *iv;
434 if (vec < 0 || vec >= IV_MAX)
436 sx_xlock(&intr_table_lock);
437 iv = &intr_vectors[vec];
439 sx_xunlock(&intr_table_lock);
442 error = intr_event_describe_handler(iv->iv_event, ih, descr);
444 sx_xunlock(&intr_table_lock);
447 intrcnt_updatename(vec, iv->iv_event->ie_fullname, 0);
448 sx_xunlock(&intr_table_lock);
454 * Support for balancing interrupt sources across CPUs. For now we just
455 * allocate CPUs round-robin.
458 /* The BSP is always a valid target. */
459 static cpumask_t intr_cpus = (1 << 0);
460 static int current_cpu;
463 intr_assign_next_cpu(struct intr_vector *iv)
467 sx_assert(&intr_table_lock, SA_XLOCKED);
470 * Assign this source to a CPU in a round-robin fashion.
472 pc = pcpu_find(current_cpu);
475 iv->iv_mid = pc->pc_mid;
476 iv->iv_ic->ic_assign(iv);
479 if (current_cpu > mp_maxid)
481 } while (!(intr_cpus & (1 << current_cpu)));
484 /* Attempt to bind the specified IRQ to the specified CPU. */
486 intr_bind(int vec, u_char cpu)
488 struct intr_vector *iv;
491 if (vec < 0 || vec >= IV_MAX)
493 sx_xlock(&intr_table_lock);
494 iv = &intr_vectors[vec];
496 sx_xunlock(&intr_table_lock);
499 error = intr_event_bind(iv->iv_event, cpu);
500 sx_xunlock(&intr_table_lock);
505 * Add a CPU to our mask of valid CPUs that can be destinations of
509 intr_add_cpu(u_int cpu)
513 panic("%s: Invalid CPU ID", __func__);
515 printf("INTR: Adding CPU %d as a target\n", cpu);
517 intr_cpus |= (1 << cpu);
521 * Distribute all the interrupt sources among the available CPUs once the
522 * APs have been launched.
525 intr_shuffle_irqs(void *arg __unused)
528 struct intr_vector *iv;
531 /* Don't bother on UP. */
535 sx_xlock(&intr_table_lock);
537 for (i = 0; i < IV_MAX; i++) {
538 iv = &intr_vectors[i];
539 if (iv != NULL && iv->iv_refcnt > 0) {
541 * If this event is already bound to a CPU,
542 * then assign the source to that CPU instead
543 * of picking one via round-robin.
545 if (iv->iv_event->ie_cpu != NOCPU &&
546 (pc = pcpu_find(iv->iv_event->ie_cpu)) != NULL) {
547 iv->iv_mid = pc->pc_mid;
548 iv->iv_ic->ic_assign(iv);
550 intr_assign_next_cpu(iv);
553 sx_xunlock(&intr_table_lock);
555 SYSINIT(intr_shuffle_irqs, SI_SUB_SMP, SI_ORDER_SECOND, intr_shuffle_irqs,